Initial commit: Matrix alignment prototype for HPC performance demonstration
- Add C implementation demonstrating memory alignment effects (matrix_alignment_prototype.c) - Include cache-blocked matrix multiplication with AVX SIMD optimizations - Add automated benchmarking framework (run_all_tests.sh, run_benchmark_sizes.sh) - Add Python visualization scripts (generate_plots.py) - Include Makefile for building with AVX support - Add benchmark results and generated plots - Add README with build and usage instructions - Configure .gitignore for C/Python project files
This commit is contained in:
Carlos Gutierrez
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README.md
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# Matrix Alignment Prototype - HPC Performance Demonstration
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This repository contains a standalone C implementation demonstrating memory alignment effects on high-performance computing performance. The prototype investigates performance variability issues related to memory alignment, specifically examining patterns described in OpenBLAS Issue #3879.
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## Project Overview
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This repository focuses on the practical implementation and benchmarking framework:
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- **C Prototype**: Custom implementation demonstrating cache-blocked matrix multiplication with AVX SIMD optimizations
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- **Memory Alignment Comparison**: Compares 64-byte cache-line aligned vs 16-byte aligned memory access patterns
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- **Benchmarking Framework**: Automated scripts for performance testing and visualization
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- **Performance Analysis**: Tools for measuring and visualizing alignment effects across different matrix sizes
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## Project Structure
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```text
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.
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├── matrix_alignment_prototype.c # C implementation demonstrating alignment effects
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├── Makefile # Build configuration for C prototype
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├── generate_plots.py # Python script for performance visualization
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├── run_benchmark_sizes.sh # Automated benchmarking script
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├── run_all_tests.sh # Complete test suite orchestrator
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├── benchmark_results.csv # Collected performance data (generated)
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├── requirements.txt # Python dependencies
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└── assets/ # Generated plots and figures
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```
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## Building and Running
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### Prerequisites
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- GCC compiler with AVX support
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- Python 3 with matplotlib and numpy
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- LaTeX distribution (for report compilation)
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- Make utility
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### Compiling the C Prototype
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```bash
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make
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```
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This will compile `matrix_alignment_prototype.c` with AVX optimizations enabled.
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### Running Benchmarks
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Run the complete test suite:
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```bash
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./run_all_tests.sh
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```
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Or run benchmarks for specific matrix sizes:
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```bash
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./run_benchmark_sizes.sh
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```
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For CSV output:
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```bash
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./matrix_alignment_prototype -s 1024 --csv
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```
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### Generating Visualizations
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After running benchmarks, generate plots:
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```bash
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python3 generate_plots.py
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```
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Plots will be saved in the `assets/` directory.
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## Key Features
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### Memory Alignment Demonstration
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The prototype demonstrates:
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- **Aligned version**: Uses 64-byte cache-line aligned memory with `_mm256_load_ps` (aligned SIMD loads)
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- **Misaligned version**: Uses 16-byte aligned memory with `_mm256_loadu_ps` (unaligned SIMD loads)
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- **Cache-blocked algorithm**: Implements tiled matrix multiplication for optimal cache utilization
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- **Performance variability analysis**: Measures and visualizes alignment effects across different matrix sizes
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### Benchmarking Framework
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The automated framework includes:
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- Multiple matrix size testing (512, 1024, 1500, 2048)
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- CSV data collection for reproducibility
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- Python visualization generating multiple analysis plots
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- Execution time, speedup ratio, variability, and GFLOPS metrics
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## Results
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The implementation demonstrates performance variability patterns consistent with OpenBLAS Issue #3879, showing:
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- Peak variability of 6.6% at matrix size 512
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- Size-dependent performance differences
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- Architecture-sensitive alignment effects
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- Reduced variability on modern hardware (Zen 3) compared to older architectures (Zen 2)
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## Technical Details
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### Memory Alignment Implementation
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The prototype demonstrates two memory allocation strategies:
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- **Aligned allocation**: Uses `posix_memalign()` to allocate memory aligned to 64-byte cache-line boundaries
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- **Misaligned allocation**: Simulates C++ default 16-byte alignment by offsetting pointers from cache-line boundaries
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### SIMD Optimizations
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When compiled with AVX support, the implementation uses:
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- `_mm256_load_ps()`: Aligned SIMD loads (faster, requires 32-byte alignment)
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- `_mm256_loadu_ps()`: Unaligned SIMD loads (slower, works with any alignment)
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### Cache-Blocked Algorithm
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The matrix multiplication uses a tiled (cache-blocked) approach:
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- Tile size: 64x64 elements (256 bytes for floats)
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- Maximizes cache line utilization
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- Reduces memory bandwidth requirements
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- Enables better spatial locality
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## Background
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This implementation was developed to investigate performance variability patterns described in OpenBLAS Issue #3879, which reported up to 2x performance differences depending on memory alignment. The prototype demonstrates that:
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- Performance variability is size-dependent and architecture-sensitive
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- Modern CPUs (Zen 3) show reduced alignment sensitivity compared to older architectures (Zen 2)
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- Proper cache-line alignment reduces performance unpredictability
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## Related Work
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This prototype is based on analysis of OpenBLAS Issue #3879, which documented performance variability in matrix multiplication operations due to memory alignment. The implementation demonstrates similar variability patterns while providing a standalone, reproducible example.
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## License
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This project is for educational and research purposes. Code implementations are provided for demonstration of HPC optimization principles related to memory alignment and SIMD vectorization.
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