From 798cd14f413324b333b9803c2a93b42226f5b961 Mon Sep 17 00:00:00 2001
From: Carlos Gutierrez <ingecarlos.gutierrez@gmail.com>
Date: Sun, 5 Oct 2025 00:31:07 -0400
Subject: [PATCH] updating

---
 scripts/simple_config.py | 61 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 scripts/simple_config.py

diff --git a/scripts/simple_config.py b/scripts/simple_config.py
new file mode 100644
index 0000000..ed12a60
--- /dev/null
+++ b/scripts/simple_config.py
@@ -0,0 +1,61 @@
+#!/usr/bin/env python3
+# Minimal SmartEdgeAI gem5 configuration
+import argparse, m5
+from m5.objects import *
+
+# Parse arguments
+ap = argparse.ArgumentParser()
+ap.add_argument("--cmd", required=True)
+ap.add_argument("--mem", default="16GB")
+ap.add_argument("--l2", default="1MB")
+ap.add_argument("--dvfs", choices=["high","low"], default="high")
+ap.add_argument("--drowsy", type=int, choices=[0,1], default=0)
+ap.add_argument("--core", choices=["big","little","hybrid"], default="big")
+ap.add_argument("--outdir", default="m5out")
+args = ap.parse_args()
+
+# Create system
+system = System()
+system.clk_domain = SrcClockDomain(clock="2GHz" if args.dvfs == "high" else "1GHz")
+system.mem_mode = "timing"
+system.mem_ranges = [AddrRange(args.mem)]
+
+# Create CPU based on core type
+if args.core == "big":
+    system.cpu = O3CPU()
+elif args.core == "little":
+    system.cpu = TimingSimpleCPU()
+else:  # hybrid
+    system.cpu = O3CPU()
+
+# Create memory bus
+system.membus = SystemXBar()
+
+# Connect CPU to memory bus directly (no caches for simplicity)
+system.cpu.icache_port = system.membus.cpu_side_ports
+system.cpu.dcache_port = system.membus.cpu_side_ports
+
+# Create memory controller
+system.mem_ctrl = SimpleMemory()
+system.mem_ctrl.range = system.mem_ranges[0]
+system.mem_ctrl.port = system.membus.mem_side_ports
+
+# Connect system port
+system.system_port = system.membus.cpu_side_ports
+
+# Create workload
+process = Process()
+process.executable = args.cmd
+process.cmd = [args.cmd]
+
+# Assign workload to CPU
+system.cpu.workload = process
+system.cpu.createThreads()
+
+# Create root and run simulation
+root = Root(full_system=False, system=system)
+m5.instantiate()
+
+print("[SmartEdgeAI] Starting simulation...")
+exit_event = m5.simulate()
+print(f"[SmartEdgeAI] Exiting @ tick {m5.curTick()} because {exit_event.getCause()}")