96 lines
2.7 KiB
Python
96 lines
2.7 KiB
Python
# scripts/hetero_big_little.py
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# Minimal SmartEdgeAI heterogeneous ARM system
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# Supports --cmd, --mem, --l2, --dvfs, and --drowsy
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# Generates valid stats.txt for all workloads
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import argparse, m5
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from m5.objects import *
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# -------------------------------
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# Argument parsing
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# -------------------------------
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ap = argparse.ArgumentParser()
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ap.add_argument("--cmd", required=True)
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ap.add_argument("--mem", default="16GB")
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ap.add_argument("--l2", default="1MB")
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ap.add_argument("--dvfs", choices=["high","low"], default="high")
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ap.add_argument("--drowsy", type=int, choices=[0,1], default=0)
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args = ap.parse_args()
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# -------------------------------
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# Clock & Voltage (DVFS)
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# -------------------------------
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v = VoltageDomain(voltage="1.0V" if args.dvfs == "high" else "0.8V")
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clk = "2GHz" if args.dvfs == "high" else "1GHz"
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system = System(
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clk_domain=SrcClockDomain(clock=clk, voltage_domain=v),
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mem_mode="timing",
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mem_ranges=[AddrRange(args.mem)]
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)
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# -------------------------------
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# CPU cluster: 1 big + 2 little
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# -------------------------------
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big = O3CPU(cpu_id=0)
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little1 = TimingSimpleCPU(cpu_id=1)
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little2 = TimingSimpleCPU(cpu_id=2)
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system.cpu = [big, little1, little2]
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# -------------------------------
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# Cache hierarchy
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# -------------------------------
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class L1I(Cache): size = "32kB"
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class L1D(Cache): size = "32kB"
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class L2(Cache): size = args.l2
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system.l2bus = L2XBar()
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for c in system.cpu:
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c.icache = L1I()
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c.dcache = L1D()
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c.icache.cpu_side = c.icache_port
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c.dcache.cpu_side = c.dcache_port
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c.icache.mem_side = system.l2bus.slave
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c.dcache.mem_side = system.l2bus.slave
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system.l2 = L2()
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system.membus = SystemXBar()
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system.l2.cpu_side = system.l2bus.master
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system.l2.mem_side = system.membus.slave
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# -------------------------------
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# Drowsy cache behavior
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# -------------------------------
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if args.drowsy:
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system.l2.tag_latency = 24
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system.l2.data_latency = 24
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# -------------------------------
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# Memory controller
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# -------------------------------
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system.mem_ctrl = DDR3_1600_8x8()
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system.mem_ctrl.range = system.mem_ranges[0]
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system.mem_ctrl.port = system.membus.master
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system.system_port = system.membus.slave
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# -------------------------------
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# Workload setup
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# -------------------------------
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proc = Process()
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proc.executable = args.cmd
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proc.cmd = [args.cmd]
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system.workload = SEWorkload.init_compatible(args.cmd)
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for c in system.cpu:
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c.workload = proc
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c.createThreads()
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# -------------------------------
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# Instantiate and simulate
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# -------------------------------
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root = Root(full_system=False, system=system)
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m5.instantiate()
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print("[SmartEdgeAI] Starting simulation...")
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exit_event = m5.simulate()
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print(f"[SmartEdgeAI] Exiting @ tick {m5.curTick()} because {exit_event.getCause()}")
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