10769 lines
579 KiB
JSON
10769 lines
579 KiB
JSON
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|
|
"routing_priority": 0
|
|
},
|
|
{
|
|
"type": "MessageBuffer",
|
|
"cxx_class": "gem5::ruby::MessageBuffer",
|
|
"name": "port_buffers22",
|
|
"path": "board.cache_hierarchy.ruby_system.network.routers7.port_buffers22",
|
|
"allow_zero_latency": true,
|
|
"buffer_size": 0,
|
|
"eventq_index": 0,
|
|
"max_dequeue_rate": 0,
|
|
"ordered": true,
|
|
"randomization": "ruby_system",
|
|
"routing_priority": 0
|
|
},
|
|
{
|
|
"type": "MessageBuffer",
|
|
"cxx_class": "gem5::ruby::MessageBuffer",
|
|
"name": "port_buffers23",
|
|
"path": "board.cache_hierarchy.ruby_system.network.routers7.port_buffers23",
|
|
"allow_zero_latency": true,
|
|
"buffer_size": 0,
|
|
"eventq_index": 0,
|
|
"max_dequeue_rate": 0,
|
|
"ordered": true,
|
|
"randomization": "ruby_system",
|
|
"routing_priority": 0
|
|
}
|
|
],
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.cache_hierarchy.ruby_system.network.routers7.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"router_id": 7,
|
|
"routing_unit": {
|
|
"type": "WeightBased",
|
|
"cxx_class": "gem5::ruby::WeightBased",
|
|
"name": "routing_unit",
|
|
"path": "board.cache_hierarchy.ruby_system.network.routers7.routing_unit",
|
|
"adaptive_routing": false,
|
|
"eventq_index": 0
|
|
},
|
|
"virt_nets": 3
|
|
}
|
|
],
|
|
"ruby_system": "board.cache_hierarchy.ruby_system",
|
|
"topology": "Not Specified",
|
|
"in_port": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": [
|
|
"board.cache_hierarchy.ruby_system.l1_controllers0.requestFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers0.responseFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers0.unblockFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers1.requestFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers1.responseFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers1.unblockFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers2.requestFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers2.responseFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers2.unblockFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers3.requestFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers3.responseFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers3.unblockFromL1Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l2_controllers.DirRequestFromL2Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l2_controllers.L1RequestFromL2Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.l2_controllers.responseFromL2Cache.out_port",
|
|
"board.cache_hierarchy.ruby_system.directory_controllers.responseFromDir.out_port",
|
|
"board.cache_hierarchy.ruby_system.dma_controllers0.requestToDir.out_port",
|
|
"board.cache_hierarchy.ruby_system.dma_controllers1.requestToDir.out_port"
|
|
],
|
|
"is_source": "False"
|
|
},
|
|
"out_port": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": [
|
|
"board.cache_hierarchy.ruby_system.l1_controllers0.requestToL1Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers0.responseToL1Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers1.requestToL1Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers1.responseToL1Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers2.requestToL1Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers2.responseToL1Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers3.requestToL1Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers3.responseToL1Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.l2_controllers.unblockToL2Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.l2_controllers.L1RequestToL2Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.l2_controllers.responseToL2Cache.in_port",
|
|
"board.cache_hierarchy.ruby_system.directory_controllers.requestToDir.in_port",
|
|
"board.cache_hierarchy.ruby_system.directory_controllers.responseToDir.in_port",
|
|
"board.cache_hierarchy.ruby_system.dma_controllers0.responseFromDir.in_port",
|
|
"board.cache_hierarchy.ruby_system.dma_controllers1.responseFromDir.in_port"
|
|
],
|
|
"is_source": "True"
|
|
}
|
|
},
|
|
"sys_port_proxy": {
|
|
"type": "RubyPortProxy",
|
|
"cxx_class": "gem5::ruby::RubyPortProxy",
|
|
"name": "sys_port_proxy",
|
|
"path": "board.cache_hierarchy.ruby_system.sys_port_proxy",
|
|
"clk_domain": "board.clk_domain",
|
|
"eventq_index": 0,
|
|
"is_cpu_sequencer": true,
|
|
"no_retry_on_stall": false,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.cache_hierarchy.ruby_system.sys_port_proxy.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
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|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"ruby_system": "board.cache_hierarchy.ruby_system",
|
|
"support_data_reqs": true,
|
|
"support_inst_reqs": true,
|
|
"system": "board",
|
|
"using_ruby_tester": false,
|
|
"version": 0,
|
|
"in_ports": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": [
|
|
"board.system_port"
|
|
],
|
|
"is_source": "False"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"clk_domain": {
|
|
"type": "SrcClockDomain",
|
|
"cxx_class": "gem5::SrcClockDomain",
|
|
"name": "clk_domain",
|
|
"path": "board.clk_domain",
|
|
"clock": [
|
|
333
|
|
],
|
|
"domain_id": -1,
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|
"eventq_index": 0,
|
|
"init_perf_level": 0,
|
|
"voltage_domain": {
|
|
"type": "VoltageDomain",
|
|
"cxx_class": "gem5::VoltageDomain",
|
|
"name": "voltage_domain",
|
|
"path": "board.clk_domain.voltage_domain",
|
|
"eventq_index": 0,
|
|
"voltage": [
|
|
1.0
|
|
]
|
|
}
|
|
},
|
|
"dvfs_handler": {
|
|
"type": "DVFSHandler",
|
|
"cxx_class": "gem5::DVFSHandler",
|
|
"name": "dvfs_handler",
|
|
"path": "board.dvfs_handler",
|
|
"domains": [],
|
|
"enable": false,
|
|
"eventq_index": 0,
|
|
"sys_clk_domain": "board.clk_domain",
|
|
"transition_latency": 100000000
|
|
},
|
|
"iobus": {
|
|
"type": "NoncoherentXBar",
|
|
"cxx_class": "gem5::NoncoherentXBar",
|
|
"name": "iobus",
|
|
"path": "board.iobus",
|
|
"clk_domain": "board.clk_domain",
|
|
"eventq_index": 0,
|
|
"forward_latency": 1,
|
|
"frontend_latency": 2,
|
|
"header_latency": 1,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.iobus.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
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|
|
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|
|
"leaders": [],
|
|
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|
|
},
|
|
"response_latency": 2,
|
|
"use_default_range": false,
|
|
"width": 16,
|
|
"cpu_side_ports": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": [
|
|
"board.pc.south_bridge.io_apic.int_requestor",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers0.sequencer.pio_request_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers0.sequencer.mem_request_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers1.sequencer.pio_request_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers1.sequencer.mem_request_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers2.sequencer.pio_request_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers2.sequencer.mem_request_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers3.sequencer.pio_request_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers3.sequencer.mem_request_port"
|
|
],
|
|
"is_source": "False"
|
|
},
|
|
"default": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": "board.pc.default_bus.cpu_side_ports[0]",
|
|
"is_source": "True"
|
|
},
|
|
"mem_side_ports": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": [
|
|
"board.pc.south_bridge.cmos.pio",
|
|
"board.pc.south_bridge.dma1.pio",
|
|
"board.pc.south_bridge.ide.pio",
|
|
"board.pc.south_bridge.keyboard.pio",
|
|
"board.pc.south_bridge.pic1.pio",
|
|
"board.pc.south_bridge.pic2.pio",
|
|
"board.pc.south_bridge.pit.pio",
|
|
"board.pc.south_bridge.speaker.pio",
|
|
"board.pc.south_bridge.io_apic.pio",
|
|
"board.pc.com_1.pio",
|
|
"board.pc.fake_com_2.pio",
|
|
"board.pc.fake_com_3.pio",
|
|
"board.pc.fake_com_4.pio",
|
|
"board.pc.fake_floppy.pio",
|
|
"board.pc.pci_host.pio",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers0.sequencer.pio_response_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers1.sequencer.pio_response_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers2.sequencer.pio_response_port",
|
|
"board.cache_hierarchy.ruby_system.l1_controllers3.sequencer.pio_response_port",
|
|
"board.cache_hierarchy.ruby_system.dma_controllers1.dma_sequencer.in_ports[0]"
|
|
],
|
|
"is_source": "True"
|
|
}
|
|
},
|
|
"memory": {
|
|
"type": "SubSystem",
|
|
"cxx_class": "gem5::SubSystem",
|
|
"name": "memory",
|
|
"path": "board.memory",
|
|
"eventq_index": 0,
|
|
"thermal_domain": null,
|
|
"mem_ctrl": [
|
|
{
|
|
"type": "MemCtrl",
|
|
"cxx_class": "gem5::memory::MemCtrl",
|
|
"name": "mem_ctrl",
|
|
"path": "board.memory.mem_ctrl",
|
|
"clk_domain": "board.clk_domain",
|
|
"command_window": 10000,
|
|
"disable_sanity_check": false,
|
|
"dram": {
|
|
"type": "DRAMInterface",
|
|
"cxx_class": "gem5::memory::DRAMInterface",
|
|
"name": "dram",
|
|
"path": "board.memory.mem_ctrl.dram",
|
|
"IDD0": 0.055,
|
|
"IDD02": 0.0,
|
|
"IDD2N": 0.032,
|
|
"IDD2N2": 0.0,
|
|
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|
|
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|
|
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|
|
"IDD2P12": 0.0,
|
|
"IDD3N": 0.038,
|
|
"IDD3N2": 0.0,
|
|
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|
|
"IDD3P02": 0.0,
|
|
"IDD3P1": 0.038,
|
|
"IDD3P12": 0.0,
|
|
"IDD4R": 0.157,
|
|
"IDD4R2": 0.0,
|
|
"IDD4W": 0.125,
|
|
"IDD4W2": 0.0,
|
|
"IDD5": 0.23500000000000001,
|
|
"IDD52": 0.0,
|
|
"IDD6": 0.02,
|
|
"IDD62": 0.0,
|
|
"VDD": 1.5,
|
|
"VDD2": 0.0,
|
|
"activation_limit": 4,
|
|
"addr_mapping": "RoRaBaCoCh",
|
|
"bank_groups_per_rank": 0,
|
|
"banks_per_rank": 8,
|
|
"beats_per_clock": 2,
|
|
"burst_length": 8,
|
|
"clk_domain": "board.clk_domain",
|
|
"conf_table_reported": true,
|
|
"data_clock_sync": false,
|
|
"device_bus_width": 8,
|
|
"device_rowbuffer_size": 1024,
|
|
"device_size": 536870912,
|
|
"devices_per_rank": 8,
|
|
"dll": true,
|
|
"enable_dram_powerdown": false,
|
|
"eventq_index": 0,
|
|
"image_file": "",
|
|
"in_addr_map": true,
|
|
"kvm_map": true,
|
|
"max_accesses_per_row": 16,
|
|
"null": false,
|
|
"page_policy": "open_adaptive",
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.memory.mem_ctrl.dram.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
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|
|
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|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"range": "0:2147483648",
|
|
"ranks_per_channel": 2,
|
|
"read_buffer_size": 32,
|
|
"tAAD": 1250,
|
|
"tBURST": 5000,
|
|
"tBURST_MAX": 5000,
|
|
"tBURST_MIN": 5000,
|
|
"tCCD_L": 0,
|
|
"tCCD_L_WR": 0,
|
|
"tCK": 1250,
|
|
"tCL": 13750,
|
|
"tCS": 2500,
|
|
"tCWL": 13750,
|
|
"tPPD": 0,
|
|
"tRAS": 35000,
|
|
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|
|
"tRCD_WR": 13750,
|
|
"tREFI": 7800000,
|
|
"tRFC": 260000,
|
|
"tRP": 13750,
|
|
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|
|
"tRRD_L": 0,
|
|
"tRTP": 7500,
|
|
"tRTW": 2500,
|
|
"tWR": 15000,
|
|
"tWTR": 7500,
|
|
"tWTR_L": 7500,
|
|
"tXAW": 30000,
|
|
"tXP": 6000,
|
|
"tXPDLL": 0,
|
|
"tXS": 270000,
|
|
"tXSDLL": 0,
|
|
"two_cycle_activate": false,
|
|
"write_buffer_size": 64,
|
|
"writeable": true
|
|
},
|
|
"eventq_index": 0,
|
|
"mem_sched_policy": "frfcfs",
|
|
"min_reads_per_switch": 16,
|
|
"min_writes_per_switch": 16,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.memory.mem_ctrl.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"qos_policy": null,
|
|
"qos_priorities": 1,
|
|
"qos_priority_escalation": false,
|
|
"qos_q_policy": "fifo",
|
|
"qos_requestors": [
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
""
|
|
],
|
|
"qos_syncro_scheduler": false,
|
|
"qos_turnaround_policy": null,
|
|
"static_backend_latency": 10000,
|
|
"static_frontend_latency": 10000,
|
|
"system": "board",
|
|
"write_high_thresh_perc": 85,
|
|
"write_low_thresh_perc": 50,
|
|
"port": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "board.cache_hierarchy.ruby_system.directory_controllers.memory_out_port",
|
|
"is_source": "False"
|
|
}
|
|
}
|
|
]
|
|
},
|
|
"pc": {
|
|
"type": "Pc",
|
|
"cxx_class": "gem5::Pc",
|
|
"name": "pc",
|
|
"path": "board.pc",
|
|
"eventq_index": 0,
|
|
"south_bridge": {
|
|
"type": "SouthBridge",
|
|
"cxx_class": "gem5::SouthBridge",
|
|
"name": "south_bridge",
|
|
"path": "board.pc.south_bridge",
|
|
"cmos": {
|
|
"type": "Cmos",
|
|
"cxx_class": "gem5::X86ISA::Cmos",
|
|
"name": "cmos",
|
|
"path": "board.pc.south_bridge.cmos",
|
|
"clk_domain": "board.clk_domain",
|
|
"eventq_index": 0,
|
|
"pio_addr": 9223372036854775920,
|
|
"pio_latency": 100000,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.pc.south_bridge.cmos.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"system": "board",
|
|
"time": "Sun Jan 1 00:00:00 2012",
|
|
"int_pin": {
|
|
"role": "Int Source Pin",
|
|
"peer": [
|
|
"board.pc.south_bridge.pic2.inputs[0]"
|
|
],
|
|
"is_source": "True"
|
|
},
|
|
"pio": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "board.iobus.mem_side_ports[0]",
|
|
"is_source": "False"
|
|
}
|
|
},
|
|
"dma1": {
|
|
"type": "I8237",
|
|
"cxx_class": "gem5::X86ISA::I8237",
|
|
"name": "dma1",
|
|
"path": "board.pc.south_bridge.dma1",
|
|
"clk_domain": "board.clk_domain",
|
|
"eventq_index": 0,
|
|
"pio_addr": 9223372036854775808,
|
|
"pio_latency": 100000,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.pc.south_bridge.dma1.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"system": "board",
|
|
"pio": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "board.iobus.mem_side_ports[1]",
|
|
"is_source": "False"
|
|
}
|
|
},
|
|
"eventq_index": 0,
|
|
"io_apic": {
|
|
"type": "I82094AA",
|
|
"cxx_class": "gem5::X86ISA::I82094AA",
|
|
"name": "io_apic",
|
|
"path": "board.pc.south_bridge.io_apic",
|
|
"apic_id": 4,
|
|
"clk_domain": "board.clk_domain",
|
|
"eventq_index": 0,
|
|
"int_latency": 1000,
|
|
"pio_addr": 4273995776,
|
|
"pio_latency": 100000,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.pc.south_bridge.io_apic.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"system": "board",
|
|
"inputs": {
|
|
"role": "Int Sink Pin",
|
|
"peer": [
|
|
"board.pc.south_bridge.pic1.output[0]",
|
|
"board.pc.south_bridge.keyboard.keyboard_int_pin[0]",
|
|
"board.pc.south_bridge.pit.int_pin[1]",
|
|
"None",
|
|
"None",
|
|
"None",
|
|
"None",
|
|
"None",
|
|
"None",
|
|
"None",
|
|
"None",
|
|
"None",
|
|
"board.pc.south_bridge.keyboard.mouse_int_pin[0]",
|
|
"None",
|
|
"board.pc.south_bridge.ide.int_primary[1]",
|
|
"board.pc.south_bridge.ide.int_secondary[1]"
|
|
],
|
|
"is_source": "False"
|
|
},
|
|
"int_requestor": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": "board.iobus.cpu_side_ports[0]",
|
|
"is_source": "True"
|
|
},
|
|
"pio": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "board.iobus.mem_side_ports[8]",
|
|
"is_source": "False"
|
|
}
|
|
},
|
|
"keyboard": {
|
|
"type": "I8042",
|
|
"cxx_class": "gem5::X86ISA::I8042",
|
|
"name": "keyboard",
|
|
"path": "board.pc.south_bridge.keyboard",
|
|
"clk_domain": "board.clk_domain",
|
|
"command_port": 9223372036854775908,
|
|
"data_port": 9223372036854775904,
|
|
"eventq_index": 0,
|
|
"keyboard": {
|
|
"type": "PS2Keyboard",
|
|
"cxx_class": "gem5::ps2::PS2Keyboard",
|
|
"name": "keyboard",
|
|
"path": "board.pc.south_bridge.keyboard.keyboard",
|
|
"eventq_index": 0,
|
|
"vnc": null
|
|
},
|
|
"mouse": {
|
|
"type": "PS2Mouse",
|
|
"cxx_class": "gem5::ps2::PS2Mouse",
|
|
"name": "mouse",
|
|
"path": "board.pc.south_bridge.keyboard.mouse",
|
|
"eventq_index": 0
|
|
},
|
|
"pio_latency": 100000,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.pc.south_bridge.keyboard.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"system": "board",
|
|
"keyboard_int_pin": {
|
|
"role": "Int Source Pin",
|
|
"peer": [
|
|
"board.pc.south_bridge.io_apic.inputs[1]"
|
|
],
|
|
"is_source": "True"
|
|
},
|
|
"mouse_int_pin": {
|
|
"role": "Int Source Pin",
|
|
"peer": [
|
|
"board.pc.south_bridge.io_apic.inputs[12]"
|
|
],
|
|
"is_source": "True"
|
|
},
|
|
"pio": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "board.iobus.mem_side_ports[3]",
|
|
"is_source": "False"
|
|
}
|
|
},
|
|
"pic1": {
|
|
"type": "I8259",
|
|
"cxx_class": "gem5::X86ISA::I8259",
|
|
"name": "pic1",
|
|
"path": "board.pc.south_bridge.pic1",
|
|
"clk_domain": "board.clk_domain",
|
|
"eventq_index": 0,
|
|
"mode": "I8259Master",
|
|
"pio_addr": 9223372036854775840,
|
|
"pio_latency": 100000,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.pc.south_bridge.pic1.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"slave": "board.pc.south_bridge.pic2",
|
|
"system": "board",
|
|
"inputs": {
|
|
"role": "Int Sink Pin",
|
|
"peer": [
|
|
"board.pc.south_bridge.pit.int_pin[0]",
|
|
"None",
|
|
"board.pc.south_bridge.pic2.output[0]"
|
|
],
|
|
"is_source": "False"
|
|
},
|
|
"output": {
|
|
"role": "Int Source Pin",
|
|
"peer": [
|
|
"board.pc.south_bridge.io_apic.inputs[0]"
|
|
],
|
|
"is_source": "True"
|
|
},
|
|
"pio": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "board.iobus.mem_side_ports[4]",
|
|
"is_source": "False"
|
|
}
|
|
},
|
|
"pic2": {
|
|
"type": "I8259",
|
|
"cxx_class": "gem5::X86ISA::I8259",
|
|
"name": "pic2",
|
|
"path": "board.pc.south_bridge.pic2",
|
|
"clk_domain": "board.clk_domain",
|
|
"eventq_index": 0,
|
|
"mode": "I8259Slave",
|
|
"pio_addr": 9223372036854775968,
|
|
"pio_latency": 100000,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.pc.south_bridge.pic2.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"slave": null,
|
|
"system": "board",
|
|
"inputs": {
|
|
"role": "Int Sink Pin",
|
|
"peer": [
|
|
"board.pc.south_bridge.cmos.int_pin[0]",
|
|
"None",
|
|
"None",
|
|
"None",
|
|
"None",
|
|
"None",
|
|
"board.pc.south_bridge.ide.int_primary[0]",
|
|
"board.pc.south_bridge.ide.int_secondary[0]"
|
|
],
|
|
"is_source": "False"
|
|
},
|
|
"output": {
|
|
"role": "Int Source Pin",
|
|
"peer": [
|
|
"board.pc.south_bridge.pic1.inputs[2]"
|
|
],
|
|
"is_source": "True"
|
|
},
|
|
"pio": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "board.iobus.mem_side_ports[5]",
|
|
"is_source": "False"
|
|
}
|
|
},
|
|
"pit": {
|
|
"type": "I8254",
|
|
"cxx_class": "gem5::X86ISA::I8254",
|
|
"name": "pit",
|
|
"path": "board.pc.south_bridge.pit",
|
|
"clk_domain": "board.clk_domain",
|
|
"eventq_index": 0,
|
|
"pio_addr": 9223372036854775872,
|
|
"pio_latency": 100000,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.pc.south_bridge.pit.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"system": "board",
|
|
"int_pin": {
|
|
"role": "Int Source Pin",
|
|
"peer": [
|
|
"board.pc.south_bridge.pic1.inputs[0]",
|
|
"board.pc.south_bridge.io_apic.inputs[2]"
|
|
],
|
|
"is_source": "True"
|
|
},
|
|
"pio": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "board.iobus.mem_side_ports[6]",
|
|
"is_source": "False"
|
|
}
|
|
},
|
|
"speaker": {
|
|
"type": "PcSpeaker",
|
|
"cxx_class": "gem5::X86ISA::Speaker",
|
|
"name": "speaker",
|
|
"path": "board.pc.south_bridge.speaker",
|
|
"clk_domain": "board.clk_domain",
|
|
"eventq_index": 0,
|
|
"i8254": "board.pc.south_bridge.pit",
|
|
"pio_addr": 9223372036854775905,
|
|
"pio_latency": 100000,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "board.pc.south_bridge.speaker.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"system": "board",
|
|
"pio": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "board.iobus.mem_side_ports[7]",
|
|
"is_source": "False"
|
|
}
|
|
},
|
|
"ide": {
|
|
"type": "X86IdeController",
|
|
"cxx_class": "gem5::X86IdeController",
|
|
"name": "ide",
|
|
"path": "board.pc.south_bridge.ide",
|
|
"BAR0": {
|
|
"type": "PciLegacyIoBar",
|
|
"cxx_class": "gem5::PciLegacyIoBar",
|
|
"name": "BAR0",
|
|
"path": "board.pc.south_bridge.ide.BAR0",
|
|
"addr": 496,
|
|
"eventq_index": 0,
|
|
"size": 8
|
|
},
|
|
"BAR1": {
|
|
"type": "PciLegacyIoBar",
|
|
"cxx_class": "gem5::PciLegacyIoBar",
|
|
"name": "BAR1",
|
|
"path": "board.pc.south_bridge.ide.BAR1",
|
|
"addr": 1012,
|
|
"eventq_index": 0,
|
|
"size": 3
|
|
},
|
|
"BAR2": {
|
|
"type": "PciLegacyIoBar",
|
|
"cxx_class": "gem5::PciLegacyIoBar",
|
|
"name": "BAR2",
|
|
"path": "board.pc.south_bridge.ide.BAR2",
|
|
"addr": 368,
|
|
"eventq_index": 0,
|
|
"size": 8
|
|
},
|
|
"BAR3": {
|
|
"type": "PciLegacyIoBar",
|
|
"cxx_class": "gem5::PciLegacyIoBar",
|
|
"name": "BAR3",
|
|
"path": "board.pc.south_bridge.ide.BAR3",
|
|
"addr": 884,
|
|
"eventq_index": 0,
|
|
"size": 3
|
|
},
|
|
"BAR4": {
|
|
"type": "PciIoBar",
|
|
"cxx_class": "gem5::PciIoBar",
|
|
"name": "BAR4",
|
|
"path": "board.pc.south_bridge.ide.BAR4",
|
|
"eventq_index": 0,
|
|
"size": 16
|
|
},
|
|
"BAR5": {
|
|
"type": "PciBarNone",
|
|
"cxx_class": "gem5::PciBarNone",
|
|
"name": "BAR5",
|
|
"path": "board.pc.south_bridge.ide.BAR5",
|
|
"eventq_index": 0
|
|
},
|
|
"BIST": 0,
|
|
"CacheLineSize": 0,
|
|
"CapabilityPtr": 0,
|
|
"CardbusCIS": 0,
|
|
"ClassCode": 1,
|
|
"Command": 0,
|
|
"DeviceID": 28945,
|
|
"ExpansionROM": 0,
|
|
"HeaderType": 0,
|
|
"InterruptLine": 255,
|
|
"InterruptPin": 1,
|
|
"LatencyTimer": 0,
|
|
"MSICAPBaseOffset": 0,
|
|
"MSICAPCapId": 0,
|
|
"MSICAPMaskBits": 0,
|
|
"MSICAPMsgAddr": 0,
|
|
"MSICAPMsgCtrl": 0,
|
|
"MSICAPMsgData": 0,
|
|
"MSICAPMsgUpperAddr": 0,
|
|
"MSICAPNextCapability": 0,
|
|
"MSICAPPendingBits": 0,
|
|
"MSIXCAPBaseOffset": 0,
|
|
"MSIXCAPCapId": 0,
|
|
"MSIXCAPNextCapability": 0,
|
|
"MSIXMsgCtrl": 0,
|
|
"MSIXPbaOffset": 0,
|
|
"MSIXTableOffset": 0,
|
|
"MaximumLatency": 0,
|
|
"MinimumGrant": 0,
|
|
"PMCAPBaseOffset": 0,
|
|
"PMCAPCapId": 0,
|
|
"PMCAPCapabilities": 0,
|
|
"PMCAPCtrlStatus": 0,
|
|
"PMCAPNextCapability": 0,
|
|
"PXCAPBaseOffset": 0,
|
|
"PXCAPCapId": 0,
|
|
"PXCAPCapabilities": 0,
|
|
"PXCAPDevCap2": 0,
|
|
"PXCAPDevCapabilities": 0,
|
|
"PXCAPDevCtrl": 0,
|
|
"PXCAPDevCtrl2": 0,
|
|
"PXCAPDevStatus": 0,
|
|
"PXCAPLinkCap": 0,
|
|
"PXCAPLinkCtrl": 0,
|
|
"PXCAPLinkStatus": 0,
|
|
"PXCAPNextCapability": 0,
|
|
"ProgIF": 128,
|
|
"Revision": 0,
|
|
"Status": 640,
|
|
"SubClassCode": 1,
|
|
"SubsystemID": 0,
|
|
"SubsystemVendorID": 0,
|
|
"VendorID": 32902,
|
|
"clk_domain": "board.clk_domain",
|
|
"config_latency": 20000,
|
|
"ctrl_offset": 0,
|
|
"disks": [
|
|
{
|
|
"type": "IdeDisk",
|
|
"cxx_class": "gem5::IdeDisk",
|
|
"name": "disks",
|
|
"path": "board.pc.south_bridge.ide.disks",
|
|
"delay": 1000000,
|
|
"driveID": "device0",
|
|
"eventq_index": 0,
|
|
"image": {
|
|
"type": "CowDiskImage",
|
|
"cxx_class": "gem5::CowDiskImage",
|
|
"name": "image",
|
|
"path": "board.pc.south_bridge.ide.disks.image",
|
|
"child": {
|
|
"type": "RawDiskImage",
|
|
"cxx_class": "gem5::RawDiskImage",
|
|
"name": "child",
|
|
"path": "board.pc.south_bridge.ide.disks.image.child",
|
|
"eventq_index": 0,
|
|
"image_file": "/home/carlos/.cache/gem5/x86-ubuntu-18.04-img",
|
|
"read_only": true
|
|
},
|
|
"eventq_index": 0,
|
|
"image_file": "",
|
|
"read_only": false,
|
|
"table_size": 65536
|
|
}
|
|
}
|
|
],
|
|
"eventq_index": 0,
|
|
"host": "board.pc.pci_host",
|
|
"io_shift": 0,
|
|
"pci_bus": 0,
|
|
"pci_dev": 4,
|
|
"pci_func": 0,
|
|
"pio_latency": 30000,
|
|
"power_model": [],
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"is_source": "True"
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"peer": [
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}
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}
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
},
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
}
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|
},
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
}
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|
}
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|
},
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|
"processor": {
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|
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|
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|
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|
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|
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|
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|
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|
{
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
{
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|
"type": "X86Decoder",
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|
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|
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|
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|
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|
"isa": "board.processor.cores0.core.isa"
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|
}
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|
],
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|
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|
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|
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|
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|
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|
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|
{
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|
"type": "X86LocalApic",
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|
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|
"name": "interrupts",
|
|
"path": "board.processor.cores0.core.interrupts",
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|
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|
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|
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|
"name": "clk_domain",
|
|
"path": "board.processor.cores0.core.interrupts.clk_domain",
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|
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|
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|
|
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|
},
|
|
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|
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|
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|
|
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|
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|
"role": "GEM5 REQUESTOR",
|
|
"peer": "board.cache_hierarchy.ruby_system.l1_controllers0.sequencer.in_ports[4]",
|
|
"is_source": "True"
|
|
},
|
|
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|
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|
|
"peer": "board.cache_hierarchy.ruby_system.l1_controllers0.sequencer.interrupt_out_port[1]",
|
|
"is_source": "False"
|
|
},
|
|
"pio": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "board.cache_hierarchy.ruby_system.l1_controllers0.sequencer.interrupt_out_port[0]",
|
|
"is_source": "False"
|
|
}
|
|
}
|
|
],
|
|
"isa": [
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|
{
|
|
"type": "X86ISA",
|
|
"cxx_class": "gem5::X86ISA::ISA",
|
|
"name": "isa",
|
|
"path": "board.processor.cores0.core.isa",
|
|
"eventq_index": 0,
|
|
"vendor_string": "HygonGenuine"
|
|
}
|
|
],
|
|
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|
|
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|
|
"mmu": {
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|
"type": "X86MMU",
|
|
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|
|
"name": "mmu",
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}
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}
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} |