CarGDev/bits-runner-builder
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Single parsing logic

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This commit is contained in:
Rafał Grodziński
2025-07-22 15:03:34 +09:00
parent 8a708d8936
commit 3041c4383b
6 changed files with 95 additions and 70 deletions
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11
samples/test.brc
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@@ -28,7 +28,12 @@ i u32 <- 0, rep text[i] != 0:
ret num1 + num2
;*/
rawAdd raw<"=r,r,r">: num1 sint32, num2 sint32 -> sint32
/*rawAdd raw<"=r,r,r">: num1 sint32, num2 sint32 -> sint32
add $1, $2
mov $0, $1
;*/
rawAdd raw: num1 sint32, num2 sint32 -> sint32
add $1, $2
mov $0, $1
;
@@ -46,8 +51,8 @@ rawAdd raw<"=r,r,r">: num1 sint32, num2 sint32 -> sint32
main fun -> sint32
//printChar()
res1 sint32 <- normAdd(4, 5)
res2 sint32 <- rawAdd(4, 5)
//res1 sint32 <- normAdd(4, 5)
//res2 sint32 <- rawAdd(4, 5)
ret 0
;