[root] type=Root children=system eventq_index=0 full_system=false sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 [system] type=System children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain cpu_voltage_domain dvfs_handler l2 mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 tol2bus voltage_domain workload auto_unlink_shared_backstore=false cache_line_size=64 eventq_index=0 exit_on_work_items=false init_param=0 m5ops_base=0 mem_mode=timing mem_ranges=0:536870912 memories=system.mem_ctrls.dram mmap_using_noreserve=false multi_thread=false num_work_ids=16 readfile= redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2 shadow_rom_ranges= shared_backstore= symbolfile= thermal_components= thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 workload=system.workload system_port=system.membus.cpu_side_ports[0] [system.clk_domain] type=SrcClockDomain clock=1000 domain_id=-1 eventq_index=0 init_perf_level=0 voltage_domain=system.voltage_domain [system.cpu0] type=BaseO3CPU children=branchPred dcache decoder dtb_walker_cache fuPool icache interrupts isa itb_walker_cache mmu power_state tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu0.branchPred cacheLoadPorts=200 cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 decoder=system.cpu0.decoder dispatchWidth=8 do_checkpoint_insts=true do_statistics_insts=true eventq_index=0 fetchBufferSize=64 fetchQueueSize=32 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 forwardComSize=5 fuPool=system.cpu0.fuPool function_trace=false function_trace_start=0 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 interrupts=system.cpu0.interrupts isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 max_insts_all_threads=0 max_insts_any_thread=20000000 mmu=system.cpu0.mmu needsTSO=true numIQEntries=64 numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numPhysMatRegs=2 numPhysVecPredRegs=32 numPhysVecRegs=256 numROBEntries=192 numRobs=1 numThreads=1 power_gating_on_idle=false power_model= power_state=system.cpu0.power_state progress_interval=0 pwr_gating_latency=300 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=RoundRobin smtIQPolicy=Partitioned smtIQThreshold=100 smtLSQPolicy=Partitioned smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false syscallRetryLatency=10000 system=system tracer=system.cpu0.tracer trapLatency=13 wbWidth=8 workload=system.cpu0.workload dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.branchPred] type=LTAGE children=indirectBranchPred loop_predictor tage BTBEntries=4096 BTBTagSize=16 RASSize=16 eventq_index=0 indirectBranchPred=system.cpu0.branchPred.indirectBranchPred instShiftAmt=2 loop_predictor=system.cpu0.branchPred.loop_predictor numThreads=1 tage=system.cpu0.branchPred.tage [system.cpu0.branchPred.indirectBranchPred] type=SimpleIndirectPredictor eventq_index=0 indirectGHRBits=13 indirectHashGHR=true indirectHashTargets=true indirectPathLength=3 indirectSets=256 indirectTagSize=16 indirectWays=2 instShiftAmt=2 numThreads=1 [system.cpu0.branchPred.loop_predictor] type=LoopPredictor eventq_index=0 initialLoopAge=255 initialLoopIter=1 logLoopTableAssoc=2 logSizeLoopPred=8 loopTableAgeBits=8 loopTableConfidenceBits=2 loopTableIterBits=14 loopTableTagBits=14 optionalAgeReset=true restrictAllocation=false useDirectionBit=false useHashing=false useSpeculation=false withLoopBits=7 [system.cpu0.branchPred.tage] type=TAGEBase eventq_index=0 histBufferSize=2097152 initialTCounterValue=131072 instShiftAmt=2 logRatioBiModalHystEntries=2 logTagTableSizes=14 10 10 11 11 11 11 10 10 10 10 9 9 logUResetPeriod=19 maxHist=640 maxNumAlloc=1 minHist=4 nHistoryTables=12 noSkip= numThreads=1 numUseAltOnNa=1 pathHistBits=16 speculativeHistUpdate=true tagTableCounterBits=3 tagTableTagWidths=0 7 7 8 8 9 10 11 12 12 13 14 15 tagTableUBits=2 useAltOnNaBits=4 [system.cpu0.dcache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=4 power_model= power_state=system.cpu0.dcache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu0.dcache.replacement_policy response_latency=2 sequential_access=false size=32768 system=system tag_latency=2 tags=system.cpu0.dcache.tags tgts_per_mshr=20 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu0.dcache_port mem_side=system.tol2bus.cpu_side_ports[1] [system.cpu0.dcache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu0.dcache.replacement_policy] type=LRURP eventq_index=0 [system.cpu0.dcache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu0.dcache.tags.indexing_policy power_model= power_state=system.cpu0.dcache.tags.power_state replacement_policy=system.cpu0.dcache.replacement_policy sequential_access=false size=32768 system=system tag_latency=2 warmup_percentage=0 [system.cpu0.dcache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=32768 [system.cpu0.dcache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu0.decoder] type=X86Decoder eventq_index=0 isa=system.cpu0.isa [system.cpu0.dtb_walker_cache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=10 power_model= power_state=system.cpu0.dtb_walker_cache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu0.dtb_walker_cache.replacement_policy response_latency=2 sequential_access=false size=1024 system=system tag_latency=2 tags=system.cpu0.dtb_walker_cache.tags tgts_per_mshr=12 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu0.mmu.dtb.walker.port mem_side=system.tol2bus.cpu_side_ports[3] [system.cpu0.dtb_walker_cache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu0.dtb_walker_cache.replacement_policy] type=LRURP eventq_index=0 [system.cpu0.dtb_walker_cache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu0.dtb_walker_cache.tags.indexing_policy power_model= power_state=system.cpu0.dtb_walker_cache.tags.power_state replacement_policy=system.cpu0.dtb_walker_cache.replacement_policy sequential_access=false size=1024 system=system tag_latency=2 warmup_percentage=0 [system.cpu0.dtb_walker_cache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=1024 [system.cpu0.dtb_walker_cache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu0.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 system.cpu0.fuPool.FUList9 eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc eventq_index=0 opClass=IntAlu opLat=1 pipelined=true [system.cpu0.fuPool.FUList1] type=FUDesc children=opList0 opList1 count=2 eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 opClass=IntMult opLat=3 pipelined=true [system.cpu0.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 opClass=IntDiv opLat=1 pipelined=false [system.cpu0.fuPool.FUList2] type=FUDesc children=opList0 opList1 opList2 count=4 eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=FloatAdd opLat=2 pipelined=true [system.cpu0.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 opClass=FloatCmp opLat=2 pipelined=true [system.cpu0.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 opClass=FloatCvt opLat=2 pipelined=true [system.cpu0.fuPool.FUList3] type=FUDesc children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=FloatMult opLat=4 pipelined=true [system.cpu0.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 opClass=FloatMultAcc opLat=5 pipelined=true [system.cpu0.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 opClass=FloatMisc opLat=3 pipelined=true [system.cpu0.fuPool.FUList3.opList3] type=OpDesc eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false [system.cpu0.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt opLat=24 pipelined=false [system.cpu0.fuPool.FUList4] type=FUDesc children=opList0 opList1 count=0 eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1 [system.cpu0.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true [system.cpu0.fuPool.FUList4.opList1] type=OpDesc eventq_index=0 opClass=FloatMemRead opLat=1 pipelined=true [system.cpu0.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=4 eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 system.cpu0.fuPool.FUList5.opList20 system.cpu0.fuPool.FUList5.opList21 system.cpu0.fuPool.FUList5.opList22 system.cpu0.fuPool.FUList5.opList23 system.cpu0.fuPool.FUList5.opList24 system.cpu0.fuPool.FUList5.opList25 system.cpu0.fuPool.FUList5.opList26 system.cpu0.fuPool.FUList5.opList27 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 opClass=SimdAdd opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 opClass=SimdAddAcc opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 opClass=SimdAlu opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 opClass=SimdCmp opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 opClass=SimdCvt opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 opClass=SimdMisc opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 opClass=SimdMult opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 opClass=SimdMultAcc opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 opClass=SimdMatMultAcc opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 opClass=SimdShift opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 opClass=SimdShiftAcc opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 opClass=SimdDiv opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 opClass=SimdSqrt opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 opClass=SimdFloatAdd opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 opClass=SimdFloatAlu opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 opClass=SimdFloatCmp opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 opClass=SimdFloatCvt opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 opClass=SimdFloatDiv opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 opClass=SimdFloatMisc opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 opClass=SimdFloatMult opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList20] type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList21] type=OpDesc eventq_index=0 opClass=SimdFloatMatMultAcc opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList22] type=OpDesc eventq_index=0 opClass=SimdFloatSqrt opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList23] type=OpDesc eventq_index=0 opClass=SimdReduceAdd opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList24] type=OpDesc eventq_index=0 opClass=SimdReduceAlu opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList25] type=OpDesc eventq_index=0 opClass=SimdReduceCmp opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList26] type=OpDesc eventq_index=0 opClass=SimdFloatReduceAdd opLat=1 pipelined=true [system.cpu0.fuPool.FUList5.opList27] type=OpDesc eventq_index=0 opClass=SimdFloatReduceCmp opLat=1 pipelined=true [system.cpu0.fuPool.FUList6] type=FUDesc children=opList count=1 eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc eventq_index=0 opClass=SimdPredAlu opLat=1 pipelined=true [system.cpu0.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=0 eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true [system.cpu0.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 opClass=FloatMemWrite opLat=1 pipelined=true [system.cpu0.fuPool.FUList8] type=FUDesc children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList0 system.cpu0.fuPool.FUList8.opList1 system.cpu0.fuPool.FUList8.opList2 system.cpu0.fuPool.FUList8.opList3 [system.cpu0.fuPool.FUList8.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true [system.cpu0.fuPool.FUList8.opList1] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true [system.cpu0.fuPool.FUList8.opList2] type=OpDesc eventq_index=0 opClass=FloatMemRead opLat=1 pipelined=true [system.cpu0.fuPool.FUList8.opList3] type=OpDesc eventq_index=0 opClass=FloatMemWrite opLat=1 pipelined=true [system.cpu0.fuPool.FUList9] type=FUDesc children=opList count=1 eventq_index=0 opList=system.cpu0.fuPool.FUList9.opList [system.cpu0.fuPool.FUList9.opList] type=OpDesc eventq_index=0 opClass=IprAccess opLat=3 pipelined=false [system.cpu0.icache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=true max_miss_count=0 move_contractions=true mshrs=4 power_model= power_state=system.cpu0.icache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu0.icache.replacement_policy response_latency=2 sequential_access=false size=32768 system=system tag_latency=2 tags=system.cpu0.icache.tags tgts_per_mshr=20 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=true cpu_side=system.cpu0.icache_port mem_side=system.tol2bus.cpu_side_ports[0] [system.cpu0.icache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu0.icache.replacement_policy] type=LRURP eventq_index=0 [system.cpu0.icache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu0.icache.tags.indexing_policy power_model= power_state=system.cpu0.icache.tags.power_state replacement_policy=system.cpu0.icache.replacement_policy sequential_access=false size=32768 system=system tag_latency=2 warmup_percentage=0 [system.cpu0.icache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=32768 [system.cpu0.icache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu0.interrupts] type=X86LocalApic children=clk_domain clk_domain=system.cpu0.interrupts.clk_domain eventq_index=0 int_latency=1000 pio_latency=100000 system=system int_requestor=system.membus.cpu_side_ports[2] int_responder=system.membus.mem_side_ports[1] pio=system.membus.mem_side_ports[0] [system.cpu0.interrupts.clk_domain] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu0.isa] type=X86ISA eventq_index=0 vendor_string=HygonGenuine [system.cpu0.itb_walker_cache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=10 power_model= power_state=system.cpu0.itb_walker_cache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu0.itb_walker_cache.replacement_policy response_latency=2 sequential_access=false size=1024 system=system tag_latency=2 tags=system.cpu0.itb_walker_cache.tags tgts_per_mshr=12 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu0.mmu.itb.walker.port mem_side=system.tol2bus.cpu_side_ports[2] [system.cpu0.itb_walker_cache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu0.itb_walker_cache.replacement_policy] type=LRURP eventq_index=0 [system.cpu0.itb_walker_cache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu0.itb_walker_cache.tags.indexing_policy power_model= power_state=system.cpu0.itb_walker_cache.tags.power_state replacement_policy=system.cpu0.itb_walker_cache.replacement_policy sequential_access=false size=1024 system=system tag_latency=2 warmup_percentage=0 [system.cpu0.itb_walker_cache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=1024 [system.cpu0.itb_walker_cache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu0.mmu] type=X86MMU children=dtb itb dtb=system.cpu0.mmu.dtb eventq_index=0 itb=system.cpu0.mmu.itb [system.cpu0.mmu.dtb] type=X86TLB children=walker entry_type=data eventq_index=0 next_level=Null size=64 system=system walker=system.cpu0.mmu.dtb.walker [system.cpu0.mmu.dtb.walker] type=X86PagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 power_model= power_state=system.cpu0.mmu.dtb.walker.power_state system=system port=system.cpu0.dtb_walker_cache.cpu_side [system.cpu0.mmu.dtb.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu0.mmu.itb] type=X86TLB children=walker entry_type=instruction eventq_index=0 next_level=Null size=64 system=system walker=system.cpu0.mmu.itb.walker [system.cpu0.mmu.itb.walker] type=X86PagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 power_model= power_state=system.cpu0.mmu.itb.walker.power_state system=system port=system.cpu0.itb_walker_cache.cpu_side [system.cpu0.mmu.itb.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu0.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states=ON CLK_GATED OFF [system.cpu0.tracer] type=ExeTracer eventq_index=0 [system.cpu0.workload] type=Process cmd=/home/carlos/projects/gem5/gem5-run/memtouch/memtouch cwd=/home/carlos/projects/gem5 drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 executable=/home/carlos/projects/gem5/gem5-run/memtouch/memtouch gid=1000 input=cin kvmInSE=false maxStackSize=67108864 output=cout pgid=100 pid=100 ppid=0 release=5.1.0 simpoint=0 system=system uid=100 useArchPT=false [system.cpu1] type=BaseO3CPU children=branchPred dcache decoder dtb_walker_cache fuPool icache interrupts isa itb_walker_cache mmu power_state tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu1.branchPred cacheLoadPorts=200 cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 cpu_id=1 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 decoder=system.cpu1.decoder dispatchWidth=8 do_checkpoint_insts=true do_statistics_insts=true eventq_index=0 fetchBufferSize=64 fetchQueueSize=32 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 forwardComSize=5 fuPool=system.cpu1.fuPool function_trace=false function_trace_start=0 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 interrupts=system.cpu1.interrupts isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 max_insts_all_threads=0 max_insts_any_thread=20000000 mmu=system.cpu1.mmu needsTSO=true numIQEntries=64 numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numPhysMatRegs=2 numPhysVecPredRegs=32 numPhysVecRegs=256 numROBEntries=192 numRobs=1 numThreads=1 power_gating_on_idle=false power_model= power_state=system.cpu1.power_state progress_interval=0 pwr_gating_latency=300 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=RoundRobin smtIQPolicy=Partitioned smtIQThreshold=100 smtLSQPolicy=Partitioned smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false syscallRetryLatency=10000 system=system tracer=system.cpu1.tracer trapLatency=13 wbWidth=8 workload=system.cpu1.workload dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side [system.cpu1.branchPred] type=LTAGE children=indirectBranchPred loop_predictor tage BTBEntries=4096 BTBTagSize=16 RASSize=16 eventq_index=0 indirectBranchPred=system.cpu1.branchPred.indirectBranchPred instShiftAmt=2 loop_predictor=system.cpu1.branchPred.loop_predictor numThreads=1 tage=system.cpu1.branchPred.tage [system.cpu1.branchPred.indirectBranchPred] type=SimpleIndirectPredictor eventq_index=0 indirectGHRBits=13 indirectHashGHR=true indirectHashTargets=true indirectPathLength=3 indirectSets=256 indirectTagSize=16 indirectWays=2 instShiftAmt=2 numThreads=1 [system.cpu1.branchPred.loop_predictor] type=LoopPredictor eventq_index=0 initialLoopAge=255 initialLoopIter=1 logLoopTableAssoc=2 logSizeLoopPred=8 loopTableAgeBits=8 loopTableConfidenceBits=2 loopTableIterBits=14 loopTableTagBits=14 optionalAgeReset=true restrictAllocation=false useDirectionBit=false useHashing=false useSpeculation=false withLoopBits=7 [system.cpu1.branchPred.tage] type=TAGEBase eventq_index=0 histBufferSize=2097152 initialTCounterValue=131072 instShiftAmt=2 logRatioBiModalHystEntries=2 logTagTableSizes=14 10 10 11 11 11 11 10 10 10 10 9 9 logUResetPeriod=19 maxHist=640 maxNumAlloc=1 minHist=4 nHistoryTables=12 noSkip= numThreads=1 numUseAltOnNa=1 pathHistBits=16 speculativeHistUpdate=true tagTableCounterBits=3 tagTableTagWidths=0 7 7 8 8 9 10 11 12 12 13 14 15 tagTableUBits=2 useAltOnNaBits=4 [system.cpu1.dcache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=4 power_model= power_state=system.cpu1.dcache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu1.dcache.replacement_policy response_latency=2 sequential_access=false size=32768 system=system tag_latency=2 tags=system.cpu1.dcache.tags tgts_per_mshr=20 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu1.dcache_port mem_side=system.tol2bus.cpu_side_ports[5] [system.cpu1.dcache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu1.dcache.replacement_policy] type=LRURP eventq_index=0 [system.cpu1.dcache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu1.dcache.tags.indexing_policy power_model= power_state=system.cpu1.dcache.tags.power_state replacement_policy=system.cpu1.dcache.replacement_policy sequential_access=false size=32768 system=system tag_latency=2 warmup_percentage=0 [system.cpu1.dcache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=32768 [system.cpu1.dcache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu1.decoder] type=X86Decoder eventq_index=0 isa=system.cpu1.isa [system.cpu1.dtb_walker_cache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=10 power_model= power_state=system.cpu1.dtb_walker_cache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu1.dtb_walker_cache.replacement_policy response_latency=2 sequential_access=false size=1024 system=system tag_latency=2 tags=system.cpu1.dtb_walker_cache.tags tgts_per_mshr=12 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu1.mmu.dtb.walker.port mem_side=system.tol2bus.cpu_side_ports[7] [system.cpu1.dtb_walker_cache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu1.dtb_walker_cache.replacement_policy] type=LRURP eventq_index=0 [system.cpu1.dtb_walker_cache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu1.dtb_walker_cache.tags.indexing_policy power_model= power_state=system.cpu1.dtb_walker_cache.tags.power_state replacement_policy=system.cpu1.dtb_walker_cache.replacement_policy sequential_access=false size=1024 system=system tag_latency=2 warmup_percentage=0 [system.cpu1.dtb_walker_cache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=1024 [system.cpu1.dtb_walker_cache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu1.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 system.cpu1.fuPool.FUList9 eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc eventq_index=0 opClass=IntAlu opLat=1 pipelined=true [system.cpu1.fuPool.FUList1] type=FUDesc children=opList0 opList1 count=2 eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 opClass=IntMult opLat=3 pipelined=true [system.cpu1.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 opClass=IntDiv opLat=1 pipelined=false [system.cpu1.fuPool.FUList2] type=FUDesc children=opList0 opList1 opList2 count=4 eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=FloatAdd opLat=2 pipelined=true [system.cpu1.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 opClass=FloatCmp opLat=2 pipelined=true [system.cpu1.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 opClass=FloatCvt opLat=2 pipelined=true [system.cpu1.fuPool.FUList3] type=FUDesc children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 system.cpu1.fuPool.FUList3.opList3 system.cpu1.fuPool.FUList3.opList4 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=FloatMult opLat=4 pipelined=true [system.cpu1.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 opClass=FloatMultAcc opLat=5 pipelined=true [system.cpu1.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 opClass=FloatMisc opLat=3 pipelined=true [system.cpu1.fuPool.FUList3.opList3] type=OpDesc eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false [system.cpu1.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt opLat=24 pipelined=false [system.cpu1.fuPool.FUList4] type=FUDesc children=opList0 opList1 count=0 eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList0 system.cpu1.fuPool.FUList4.opList1 [system.cpu1.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true [system.cpu1.fuPool.FUList4.opList1] type=OpDesc eventq_index=0 opClass=FloatMemRead opLat=1 pipelined=true [system.cpu1.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=4 eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 system.cpu1.fuPool.FUList5.opList20 system.cpu1.fuPool.FUList5.opList21 system.cpu1.fuPool.FUList5.opList22 system.cpu1.fuPool.FUList5.opList23 system.cpu1.fuPool.FUList5.opList24 system.cpu1.fuPool.FUList5.opList25 system.cpu1.fuPool.FUList5.opList26 system.cpu1.fuPool.FUList5.opList27 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 opClass=SimdAdd opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 opClass=SimdAddAcc opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 opClass=SimdAlu opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 opClass=SimdCmp opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 opClass=SimdCvt opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 opClass=SimdMisc opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 opClass=SimdMult opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 opClass=SimdMultAcc opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 opClass=SimdMatMultAcc opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 opClass=SimdShift opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 opClass=SimdShiftAcc opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 opClass=SimdDiv opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 opClass=SimdSqrt opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 opClass=SimdFloatAdd opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 opClass=SimdFloatAlu opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 opClass=SimdFloatCmp opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 opClass=SimdFloatCvt opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 opClass=SimdFloatDiv opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 opClass=SimdFloatMisc opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 opClass=SimdFloatMult opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList20] type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList21] type=OpDesc eventq_index=0 opClass=SimdFloatMatMultAcc opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList22] type=OpDesc eventq_index=0 opClass=SimdFloatSqrt opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList23] type=OpDesc eventq_index=0 opClass=SimdReduceAdd opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList24] type=OpDesc eventq_index=0 opClass=SimdReduceAlu opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList25] type=OpDesc eventq_index=0 opClass=SimdReduceCmp opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList26] type=OpDesc eventq_index=0 opClass=SimdFloatReduceAdd opLat=1 pipelined=true [system.cpu1.fuPool.FUList5.opList27] type=OpDesc eventq_index=0 opClass=SimdFloatReduceCmp opLat=1 pipelined=true [system.cpu1.fuPool.FUList6] type=FUDesc children=opList count=1 eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc eventq_index=0 opClass=SimdPredAlu opLat=1 pipelined=true [system.cpu1.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=0 eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true [system.cpu1.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 opClass=FloatMemWrite opLat=1 pipelined=true [system.cpu1.fuPool.FUList8] type=FUDesc children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList0 system.cpu1.fuPool.FUList8.opList1 system.cpu1.fuPool.FUList8.opList2 system.cpu1.fuPool.FUList8.opList3 [system.cpu1.fuPool.FUList8.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true [system.cpu1.fuPool.FUList8.opList1] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true [system.cpu1.fuPool.FUList8.opList2] type=OpDesc eventq_index=0 opClass=FloatMemRead opLat=1 pipelined=true [system.cpu1.fuPool.FUList8.opList3] type=OpDesc eventq_index=0 opClass=FloatMemWrite opLat=1 pipelined=true [system.cpu1.fuPool.FUList9] type=FUDesc children=opList count=1 eventq_index=0 opList=system.cpu1.fuPool.FUList9.opList [system.cpu1.fuPool.FUList9.opList] type=OpDesc eventq_index=0 opClass=IprAccess opLat=3 pipelined=false [system.cpu1.icache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=true max_miss_count=0 move_contractions=true mshrs=4 power_model= power_state=system.cpu1.icache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu1.icache.replacement_policy response_latency=2 sequential_access=false size=32768 system=system tag_latency=2 tags=system.cpu1.icache.tags tgts_per_mshr=20 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=true cpu_side=system.cpu1.icache_port mem_side=system.tol2bus.cpu_side_ports[4] [system.cpu1.icache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu1.icache.replacement_policy] type=LRURP eventq_index=0 [system.cpu1.icache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu1.icache.tags.indexing_policy power_model= power_state=system.cpu1.icache.tags.power_state replacement_policy=system.cpu1.icache.replacement_policy sequential_access=false size=32768 system=system tag_latency=2 warmup_percentage=0 [system.cpu1.icache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=32768 [system.cpu1.icache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu1.interrupts] type=X86LocalApic children=clk_domain clk_domain=system.cpu1.interrupts.clk_domain eventq_index=0 int_latency=1000 pio_latency=100000 system=system int_requestor=system.membus.cpu_side_ports[3] int_responder=system.membus.mem_side_ports[3] pio=system.membus.mem_side_ports[2] [system.cpu1.interrupts.clk_domain] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu1.isa] type=X86ISA eventq_index=0 vendor_string=HygonGenuine [system.cpu1.itb_walker_cache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=10 power_model= power_state=system.cpu1.itb_walker_cache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu1.itb_walker_cache.replacement_policy response_latency=2 sequential_access=false size=1024 system=system tag_latency=2 tags=system.cpu1.itb_walker_cache.tags tgts_per_mshr=12 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu1.mmu.itb.walker.port mem_side=system.tol2bus.cpu_side_ports[6] [system.cpu1.itb_walker_cache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu1.itb_walker_cache.replacement_policy] type=LRURP eventq_index=0 [system.cpu1.itb_walker_cache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu1.itb_walker_cache.tags.indexing_policy power_model= power_state=system.cpu1.itb_walker_cache.tags.power_state replacement_policy=system.cpu1.itb_walker_cache.replacement_policy sequential_access=false size=1024 system=system tag_latency=2 warmup_percentage=0 [system.cpu1.itb_walker_cache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=1024 [system.cpu1.itb_walker_cache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu1.mmu] type=X86MMU children=dtb itb dtb=system.cpu1.mmu.dtb eventq_index=0 itb=system.cpu1.mmu.itb [system.cpu1.mmu.dtb] type=X86TLB children=walker entry_type=data eventq_index=0 next_level=Null size=64 system=system walker=system.cpu1.mmu.dtb.walker [system.cpu1.mmu.dtb.walker] type=X86PagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 power_model= power_state=system.cpu1.mmu.dtb.walker.power_state system=system port=system.cpu1.dtb_walker_cache.cpu_side [system.cpu1.mmu.dtb.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu1.mmu.itb] type=X86TLB children=walker entry_type=instruction eventq_index=0 next_level=Null size=64 system=system walker=system.cpu1.mmu.itb.walker [system.cpu1.mmu.itb.walker] type=X86PagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 power_model= power_state=system.cpu1.mmu.itb.walker.power_state system=system port=system.cpu1.itb_walker_cache.cpu_side [system.cpu1.mmu.itb.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu1.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states=ON CLK_GATED OFF [system.cpu1.tracer] type=ExeTracer eventq_index=0 [system.cpu1.workload] type=Process cmd=/home/carlos/projects/gem5/gem5-run/memtouch/memtouch cwd=/home/carlos/projects/gem5 drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 executable=/home/carlos/projects/gem5/gem5-run/memtouch/memtouch gid=1000 input=cin kvmInSE=false maxStackSize=67108864 output=cout pgid=100 pid=101 ppid=0 release=5.1.0 simpoint=0 system=system uid=100 useArchPT=false [system.cpu2] type=BaseO3CPU children=branchPred dcache decoder dtb_walker_cache fuPool icache interrupts isa itb_walker_cache mmu power_state tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu2.branchPred cacheLoadPorts=200 cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 cpu_id=2 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 decoder=system.cpu2.decoder dispatchWidth=8 do_checkpoint_insts=true do_statistics_insts=true eventq_index=0 fetchBufferSize=64 fetchQueueSize=32 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 forwardComSize=5 fuPool=system.cpu2.fuPool function_trace=false function_trace_start=0 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 interrupts=system.cpu2.interrupts isa=system.cpu2.isa issueToExecuteDelay=1 issueWidth=8 max_insts_all_threads=0 max_insts_any_thread=20000000 mmu=system.cpu2.mmu needsTSO=true numIQEntries=64 numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numPhysMatRegs=2 numPhysVecPredRegs=32 numPhysVecRegs=256 numROBEntries=192 numRobs=1 numThreads=1 power_gating_on_idle=false power_model= power_state=system.cpu2.power_state progress_interval=0 pwr_gating_latency=300 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=RoundRobin smtIQPolicy=Partitioned smtIQThreshold=100 smtLSQPolicy=Partitioned smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false syscallRetryLatency=10000 system=system tracer=system.cpu2.tracer trapLatency=13 wbWidth=8 workload=system.cpu2.workload dcache_port=system.cpu2.dcache.cpu_side icache_port=system.cpu2.icache.cpu_side [system.cpu2.branchPred] type=LTAGE children=indirectBranchPred loop_predictor tage BTBEntries=4096 BTBTagSize=16 RASSize=16 eventq_index=0 indirectBranchPred=system.cpu2.branchPred.indirectBranchPred instShiftAmt=2 loop_predictor=system.cpu2.branchPred.loop_predictor numThreads=1 tage=system.cpu2.branchPred.tage [system.cpu2.branchPred.indirectBranchPred] type=SimpleIndirectPredictor eventq_index=0 indirectGHRBits=13 indirectHashGHR=true indirectHashTargets=true indirectPathLength=3 indirectSets=256 indirectTagSize=16 indirectWays=2 instShiftAmt=2 numThreads=1 [system.cpu2.branchPred.loop_predictor] type=LoopPredictor eventq_index=0 initialLoopAge=255 initialLoopIter=1 logLoopTableAssoc=2 logSizeLoopPred=8 loopTableAgeBits=8 loopTableConfidenceBits=2 loopTableIterBits=14 loopTableTagBits=14 optionalAgeReset=true restrictAllocation=false useDirectionBit=false useHashing=false useSpeculation=false withLoopBits=7 [system.cpu2.branchPred.tage] type=TAGEBase eventq_index=0 histBufferSize=2097152 initialTCounterValue=131072 instShiftAmt=2 logRatioBiModalHystEntries=2 logTagTableSizes=14 10 10 11 11 11 11 10 10 10 10 9 9 logUResetPeriod=19 maxHist=640 maxNumAlloc=1 minHist=4 nHistoryTables=12 noSkip= numThreads=1 numUseAltOnNa=1 pathHistBits=16 speculativeHistUpdate=true tagTableCounterBits=3 tagTableTagWidths=0 7 7 8 8 9 10 11 12 12 13 14 15 tagTableUBits=2 useAltOnNaBits=4 [system.cpu2.dcache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=4 power_model= power_state=system.cpu2.dcache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu2.dcache.replacement_policy response_latency=2 sequential_access=false size=32768 system=system tag_latency=2 tags=system.cpu2.dcache.tags tgts_per_mshr=20 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu2.dcache_port mem_side=system.tol2bus.cpu_side_ports[9] [system.cpu2.dcache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu2.dcache.replacement_policy] type=LRURP eventq_index=0 [system.cpu2.dcache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu2.dcache.tags.indexing_policy power_model= power_state=system.cpu2.dcache.tags.power_state replacement_policy=system.cpu2.dcache.replacement_policy sequential_access=false size=32768 system=system tag_latency=2 warmup_percentage=0 [system.cpu2.dcache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=32768 [system.cpu2.dcache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu2.decoder] type=X86Decoder eventq_index=0 isa=system.cpu2.isa [system.cpu2.dtb_walker_cache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=10 power_model= power_state=system.cpu2.dtb_walker_cache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu2.dtb_walker_cache.replacement_policy response_latency=2 sequential_access=false size=1024 system=system tag_latency=2 tags=system.cpu2.dtb_walker_cache.tags tgts_per_mshr=12 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu2.mmu.dtb.walker.port mem_side=system.tol2bus.cpu_side_ports[11] [system.cpu2.dtb_walker_cache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu2.dtb_walker_cache.replacement_policy] type=LRURP eventq_index=0 [system.cpu2.dtb_walker_cache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu2.dtb_walker_cache.tags.indexing_policy power_model= power_state=system.cpu2.dtb_walker_cache.tags.power_state replacement_policy=system.cpu2.dtb_walker_cache.replacement_policy sequential_access=false size=1024 system=system tag_latency=2 warmup_percentage=0 [system.cpu2.dtb_walker_cache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=1024 [system.cpu2.dtb_walker_cache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu2.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 system.cpu2.fuPool.FUList9 eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc eventq_index=0 opClass=IntAlu opLat=1 pipelined=true [system.cpu2.fuPool.FUList1] type=FUDesc children=opList0 opList1 count=2 eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 opClass=IntMult opLat=3 pipelined=true [system.cpu2.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 opClass=IntDiv opLat=1 pipelined=false [system.cpu2.fuPool.FUList2] type=FUDesc children=opList0 opList1 opList2 count=4 eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=FloatAdd opLat=2 pipelined=true [system.cpu2.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 opClass=FloatCmp opLat=2 pipelined=true [system.cpu2.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 opClass=FloatCvt opLat=2 pipelined=true [system.cpu2.fuPool.FUList3] type=FUDesc children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=FloatMult opLat=4 pipelined=true [system.cpu2.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 opClass=FloatMultAcc opLat=5 pipelined=true [system.cpu2.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 opClass=FloatMisc opLat=3 pipelined=true [system.cpu2.fuPool.FUList3.opList3] type=OpDesc eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false [system.cpu2.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt opLat=24 pipelined=false [system.cpu2.fuPool.FUList4] type=FUDesc children=opList0 opList1 count=0 eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1 [system.cpu2.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true [system.cpu2.fuPool.FUList4.opList1] type=OpDesc eventq_index=0 opClass=FloatMemRead opLat=1 pipelined=true [system.cpu2.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=4 eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 system.cpu2.fuPool.FUList5.opList20 system.cpu2.fuPool.FUList5.opList21 system.cpu2.fuPool.FUList5.opList22 system.cpu2.fuPool.FUList5.opList23 system.cpu2.fuPool.FUList5.opList24 system.cpu2.fuPool.FUList5.opList25 system.cpu2.fuPool.FUList5.opList26 system.cpu2.fuPool.FUList5.opList27 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 opClass=SimdAdd opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 opClass=SimdAddAcc opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 opClass=SimdAlu opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 opClass=SimdCmp opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 opClass=SimdCvt opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 opClass=SimdMisc opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 opClass=SimdMult opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 opClass=SimdMultAcc opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 opClass=SimdMatMultAcc opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 opClass=SimdShift opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 opClass=SimdShiftAcc opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 opClass=SimdDiv opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 opClass=SimdSqrt opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 opClass=SimdFloatAdd opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 opClass=SimdFloatAlu opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 opClass=SimdFloatCmp opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 opClass=SimdFloatCvt opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 opClass=SimdFloatDiv opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 opClass=SimdFloatMisc opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 opClass=SimdFloatMult opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList20] type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList21] type=OpDesc eventq_index=0 opClass=SimdFloatMatMultAcc opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList22] type=OpDesc eventq_index=0 opClass=SimdFloatSqrt opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList23] type=OpDesc eventq_index=0 opClass=SimdReduceAdd opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList24] type=OpDesc eventq_index=0 opClass=SimdReduceAlu opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList25] type=OpDesc eventq_index=0 opClass=SimdReduceCmp opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList26] type=OpDesc eventq_index=0 opClass=SimdFloatReduceAdd opLat=1 pipelined=true [system.cpu2.fuPool.FUList5.opList27] type=OpDesc eventq_index=0 opClass=SimdFloatReduceCmp opLat=1 pipelined=true [system.cpu2.fuPool.FUList6] type=FUDesc children=opList count=1 eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc eventq_index=0 opClass=SimdPredAlu opLat=1 pipelined=true [system.cpu2.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=0 eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true [system.cpu2.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 opClass=FloatMemWrite opLat=1 pipelined=true [system.cpu2.fuPool.FUList8] type=FUDesc children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList0 system.cpu2.fuPool.FUList8.opList1 system.cpu2.fuPool.FUList8.opList2 system.cpu2.fuPool.FUList8.opList3 [system.cpu2.fuPool.FUList8.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true [system.cpu2.fuPool.FUList8.opList1] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true [system.cpu2.fuPool.FUList8.opList2] type=OpDesc eventq_index=0 opClass=FloatMemRead opLat=1 pipelined=true [system.cpu2.fuPool.FUList8.opList3] type=OpDesc eventq_index=0 opClass=FloatMemWrite opLat=1 pipelined=true [system.cpu2.fuPool.FUList9] type=FUDesc children=opList count=1 eventq_index=0 opList=system.cpu2.fuPool.FUList9.opList [system.cpu2.fuPool.FUList9.opList] type=OpDesc eventq_index=0 opClass=IprAccess opLat=3 pipelined=false [system.cpu2.icache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=true max_miss_count=0 move_contractions=true mshrs=4 power_model= power_state=system.cpu2.icache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu2.icache.replacement_policy response_latency=2 sequential_access=false size=32768 system=system tag_latency=2 tags=system.cpu2.icache.tags tgts_per_mshr=20 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=true cpu_side=system.cpu2.icache_port mem_side=system.tol2bus.cpu_side_ports[8] [system.cpu2.icache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu2.icache.replacement_policy] type=LRURP eventq_index=0 [system.cpu2.icache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu2.icache.tags.indexing_policy power_model= power_state=system.cpu2.icache.tags.power_state replacement_policy=system.cpu2.icache.replacement_policy sequential_access=false size=32768 system=system tag_latency=2 warmup_percentage=0 [system.cpu2.icache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=32768 [system.cpu2.icache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu2.interrupts] type=X86LocalApic children=clk_domain clk_domain=system.cpu2.interrupts.clk_domain eventq_index=0 int_latency=1000 pio_latency=100000 system=system int_requestor=system.membus.cpu_side_ports[4] int_responder=system.membus.mem_side_ports[5] pio=system.membus.mem_side_ports[4] [system.cpu2.interrupts.clk_domain] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu2.isa] type=X86ISA eventq_index=0 vendor_string=HygonGenuine [system.cpu2.itb_walker_cache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=10 power_model= power_state=system.cpu2.itb_walker_cache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu2.itb_walker_cache.replacement_policy response_latency=2 sequential_access=false size=1024 system=system tag_latency=2 tags=system.cpu2.itb_walker_cache.tags tgts_per_mshr=12 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu2.mmu.itb.walker.port mem_side=system.tol2bus.cpu_side_ports[10] [system.cpu2.itb_walker_cache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu2.itb_walker_cache.replacement_policy] type=LRURP eventq_index=0 [system.cpu2.itb_walker_cache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu2.itb_walker_cache.tags.indexing_policy power_model= power_state=system.cpu2.itb_walker_cache.tags.power_state replacement_policy=system.cpu2.itb_walker_cache.replacement_policy sequential_access=false size=1024 system=system tag_latency=2 warmup_percentage=0 [system.cpu2.itb_walker_cache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=1024 [system.cpu2.itb_walker_cache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu2.mmu] type=X86MMU children=dtb itb dtb=system.cpu2.mmu.dtb eventq_index=0 itb=system.cpu2.mmu.itb [system.cpu2.mmu.dtb] type=X86TLB children=walker entry_type=data eventq_index=0 next_level=Null size=64 system=system walker=system.cpu2.mmu.dtb.walker [system.cpu2.mmu.dtb.walker] type=X86PagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 power_model= power_state=system.cpu2.mmu.dtb.walker.power_state system=system port=system.cpu2.dtb_walker_cache.cpu_side [system.cpu2.mmu.dtb.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu2.mmu.itb] type=X86TLB children=walker entry_type=instruction eventq_index=0 next_level=Null size=64 system=system walker=system.cpu2.mmu.itb.walker [system.cpu2.mmu.itb.walker] type=X86PagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 power_model= power_state=system.cpu2.mmu.itb.walker.power_state system=system port=system.cpu2.itb_walker_cache.cpu_side [system.cpu2.mmu.itb.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu2.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states=ON CLK_GATED OFF [system.cpu2.tracer] type=ExeTracer eventq_index=0 [system.cpu2.workload] type=Process cmd=/bin/ls cwd=/home/carlos/projects/gem5 drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 executable=/bin/ls gid=1000 input=cin kvmInSE=false maxStackSize=67108864 output=cout pgid=100 pid=102 ppid=0 release=5.1.0 simpoint=0 system=system uid=100 useArchPT=false [system.cpu3] type=BaseO3CPU children=branchPred dcache decoder dtb_walker_cache fuPool icache interrupts isa itb_walker_cache mmu power_state tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu3.branchPred cacheLoadPorts=200 cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 cpu_id=3 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 decoder=system.cpu3.decoder dispatchWidth=8 do_checkpoint_insts=true do_statistics_insts=true eventq_index=0 fetchBufferSize=64 fetchQueueSize=32 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 forwardComSize=5 fuPool=system.cpu3.fuPool function_trace=false function_trace_start=0 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 interrupts=system.cpu3.interrupts isa=system.cpu3.isa issueToExecuteDelay=1 issueWidth=8 max_insts_all_threads=0 max_insts_any_thread=20000000 mmu=system.cpu3.mmu needsTSO=true numIQEntries=64 numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numPhysMatRegs=2 numPhysVecPredRegs=32 numPhysVecRegs=256 numROBEntries=192 numRobs=1 numThreads=1 power_gating_on_idle=false power_model= power_state=system.cpu3.power_state progress_interval=0 pwr_gating_latency=300 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=RoundRobin smtIQPolicy=Partitioned smtIQThreshold=100 smtLSQPolicy=Partitioned smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false syscallRetryLatency=10000 system=system tracer=system.cpu3.tracer trapLatency=13 wbWidth=8 workload=system.cpu3.workload dcache_port=system.cpu3.dcache.cpu_side icache_port=system.cpu3.icache.cpu_side [system.cpu3.branchPred] type=LTAGE children=indirectBranchPred loop_predictor tage BTBEntries=4096 BTBTagSize=16 RASSize=16 eventq_index=0 indirectBranchPred=system.cpu3.branchPred.indirectBranchPred instShiftAmt=2 loop_predictor=system.cpu3.branchPred.loop_predictor numThreads=1 tage=system.cpu3.branchPred.tage [system.cpu3.branchPred.indirectBranchPred] type=SimpleIndirectPredictor eventq_index=0 indirectGHRBits=13 indirectHashGHR=true indirectHashTargets=true indirectPathLength=3 indirectSets=256 indirectTagSize=16 indirectWays=2 instShiftAmt=2 numThreads=1 [system.cpu3.branchPred.loop_predictor] type=LoopPredictor eventq_index=0 initialLoopAge=255 initialLoopIter=1 logLoopTableAssoc=2 logSizeLoopPred=8 loopTableAgeBits=8 loopTableConfidenceBits=2 loopTableIterBits=14 loopTableTagBits=14 optionalAgeReset=true restrictAllocation=false useDirectionBit=false useHashing=false useSpeculation=false withLoopBits=7 [system.cpu3.branchPred.tage] type=TAGEBase eventq_index=0 histBufferSize=2097152 initialTCounterValue=131072 instShiftAmt=2 logRatioBiModalHystEntries=2 logTagTableSizes=14 10 10 11 11 11 11 10 10 10 10 9 9 logUResetPeriod=19 maxHist=640 maxNumAlloc=1 minHist=4 nHistoryTables=12 noSkip= numThreads=1 numUseAltOnNa=1 pathHistBits=16 speculativeHistUpdate=true tagTableCounterBits=3 tagTableTagWidths=0 7 7 8 8 9 10 11 12 12 13 14 15 tagTableUBits=2 useAltOnNaBits=4 [system.cpu3.dcache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=4 power_model= power_state=system.cpu3.dcache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu3.dcache.replacement_policy response_latency=2 sequential_access=false size=32768 system=system tag_latency=2 tags=system.cpu3.dcache.tags tgts_per_mshr=20 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu3.dcache_port mem_side=system.tol2bus.cpu_side_ports[13] [system.cpu3.dcache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu3.dcache.replacement_policy] type=LRURP eventq_index=0 [system.cpu3.dcache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu3.dcache.tags.indexing_policy power_model= power_state=system.cpu3.dcache.tags.power_state replacement_policy=system.cpu3.dcache.replacement_policy sequential_access=false size=32768 system=system tag_latency=2 warmup_percentage=0 [system.cpu3.dcache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=32768 [system.cpu3.dcache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu3.decoder] type=X86Decoder eventq_index=0 isa=system.cpu3.isa [system.cpu3.dtb_walker_cache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=10 power_model= power_state=system.cpu3.dtb_walker_cache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu3.dtb_walker_cache.replacement_policy response_latency=2 sequential_access=false size=1024 system=system tag_latency=2 tags=system.cpu3.dtb_walker_cache.tags tgts_per_mshr=12 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu3.mmu.dtb.walker.port mem_side=system.tol2bus.cpu_side_ports[15] [system.cpu3.dtb_walker_cache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu3.dtb_walker_cache.replacement_policy] type=LRURP eventq_index=0 [system.cpu3.dtb_walker_cache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu3.dtb_walker_cache.tags.indexing_policy power_model= power_state=system.cpu3.dtb_walker_cache.tags.power_state replacement_policy=system.cpu3.dtb_walker_cache.replacement_policy sequential_access=false size=1024 system=system tag_latency=2 warmup_percentage=0 [system.cpu3.dtb_walker_cache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=1024 [system.cpu3.dtb_walker_cache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu3.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9 FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 system.cpu3.fuPool.FUList9 eventq_index=0 [system.cpu3.fuPool.FUList0] type=FUDesc children=opList count=6 eventq_index=0 opList=system.cpu3.fuPool.FUList0.opList [system.cpu3.fuPool.FUList0.opList] type=OpDesc eventq_index=0 opClass=IntAlu opLat=1 pipelined=true [system.cpu3.fuPool.FUList1] type=FUDesc children=opList0 opList1 count=2 eventq_index=0 opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 [system.cpu3.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 opClass=IntMult opLat=3 pipelined=true [system.cpu3.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 opClass=IntDiv opLat=1 pipelined=false [system.cpu3.fuPool.FUList2] type=FUDesc children=opList0 opList1 opList2 count=4 eventq_index=0 opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 [system.cpu3.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=FloatAdd opLat=2 pipelined=true [system.cpu3.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 opClass=FloatCmp opLat=2 pipelined=true [system.cpu3.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 opClass=FloatCvt opLat=2 pipelined=true [system.cpu3.fuPool.FUList3] type=FUDesc children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4 [system.cpu3.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=FloatMult opLat=4 pipelined=true [system.cpu3.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 opClass=FloatMultAcc opLat=5 pipelined=true [system.cpu3.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 opClass=FloatMisc opLat=3 pipelined=true [system.cpu3.fuPool.FUList3.opList3] type=OpDesc eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false [system.cpu3.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt opLat=24 pipelined=false [system.cpu3.fuPool.FUList4] type=FUDesc children=opList0 opList1 count=0 eventq_index=0 opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1 [system.cpu3.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true [system.cpu3.fuPool.FUList4.opList1] type=OpDesc eventq_index=0 opClass=FloatMemRead opLat=1 pipelined=true [system.cpu3.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=4 eventq_index=0 opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 system.cpu3.fuPool.FUList5.opList20 system.cpu3.fuPool.FUList5.opList21 system.cpu3.fuPool.FUList5.opList22 system.cpu3.fuPool.FUList5.opList23 system.cpu3.fuPool.FUList5.opList24 system.cpu3.fuPool.FUList5.opList25 system.cpu3.fuPool.FUList5.opList26 system.cpu3.fuPool.FUList5.opList27 [system.cpu3.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 opClass=SimdAdd opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 opClass=SimdAddAcc opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 opClass=SimdAlu opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 opClass=SimdCmp opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 opClass=SimdCvt opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 opClass=SimdMisc opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 opClass=SimdMult opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 opClass=SimdMultAcc opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 opClass=SimdMatMultAcc opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 opClass=SimdShift opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 opClass=SimdShiftAcc opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 opClass=SimdDiv opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 opClass=SimdSqrt opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 opClass=SimdFloatAdd opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 opClass=SimdFloatAlu opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 opClass=SimdFloatCmp opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 opClass=SimdFloatCvt opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 opClass=SimdFloatDiv opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 opClass=SimdFloatMisc opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 opClass=SimdFloatMult opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList20] type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList21] type=OpDesc eventq_index=0 opClass=SimdFloatMatMultAcc opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList22] type=OpDesc eventq_index=0 opClass=SimdFloatSqrt opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList23] type=OpDesc eventq_index=0 opClass=SimdReduceAdd opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList24] type=OpDesc eventq_index=0 opClass=SimdReduceAlu opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList25] type=OpDesc eventq_index=0 opClass=SimdReduceCmp opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList26] type=OpDesc eventq_index=0 opClass=SimdFloatReduceAdd opLat=1 pipelined=true [system.cpu3.fuPool.FUList5.opList27] type=OpDesc eventq_index=0 opClass=SimdFloatReduceCmp opLat=1 pipelined=true [system.cpu3.fuPool.FUList6] type=FUDesc children=opList count=1 eventq_index=0 opList=system.cpu3.fuPool.FUList6.opList [system.cpu3.fuPool.FUList6.opList] type=OpDesc eventq_index=0 opClass=SimdPredAlu opLat=1 pipelined=true [system.cpu3.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=0 eventq_index=0 opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 [system.cpu3.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true [system.cpu3.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 opClass=FloatMemWrite opLat=1 pipelined=true [system.cpu3.fuPool.FUList8] type=FUDesc children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 opList=system.cpu3.fuPool.FUList8.opList0 system.cpu3.fuPool.FUList8.opList1 system.cpu3.fuPool.FUList8.opList2 system.cpu3.fuPool.FUList8.opList3 [system.cpu3.fuPool.FUList8.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true [system.cpu3.fuPool.FUList8.opList1] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true [system.cpu3.fuPool.FUList8.opList2] type=OpDesc eventq_index=0 opClass=FloatMemRead opLat=1 pipelined=true [system.cpu3.fuPool.FUList8.opList3] type=OpDesc eventq_index=0 opClass=FloatMemWrite opLat=1 pipelined=true [system.cpu3.fuPool.FUList9] type=FUDesc children=opList count=1 eventq_index=0 opList=system.cpu3.fuPool.FUList9.opList [system.cpu3.fuPool.FUList9.opList] type=OpDesc eventq_index=0 opClass=IprAccess opLat=3 pipelined=false [system.cpu3.icache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=true max_miss_count=0 move_contractions=true mshrs=4 power_model= power_state=system.cpu3.icache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu3.icache.replacement_policy response_latency=2 sequential_access=false size=32768 system=system tag_latency=2 tags=system.cpu3.icache.tags tgts_per_mshr=20 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=true cpu_side=system.cpu3.icache_port mem_side=system.tol2bus.cpu_side_ports[12] [system.cpu3.icache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu3.icache.replacement_policy] type=LRURP eventq_index=0 [system.cpu3.icache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu3.icache.tags.indexing_policy power_model= power_state=system.cpu3.icache.tags.power_state replacement_policy=system.cpu3.icache.replacement_policy sequential_access=false size=32768 system=system tag_latency=2 warmup_percentage=0 [system.cpu3.icache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=32768 [system.cpu3.icache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu3.interrupts] type=X86LocalApic children=clk_domain clk_domain=system.cpu3.interrupts.clk_domain eventq_index=0 int_latency=1000 pio_latency=100000 system=system int_requestor=system.membus.cpu_side_ports[5] int_responder=system.membus.mem_side_ports[7] pio=system.membus.mem_side_ports[6] [system.cpu3.interrupts.clk_domain] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu3.isa] type=X86ISA eventq_index=0 vendor_string=HygonGenuine [system.cpu3.itb_walker_cache] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=2 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=10 power_model= power_state=system.cpu3.itb_walker_cache.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.cpu3.itb_walker_cache.replacement_policy response_latency=2 sequential_access=false size=1024 system=system tag_latency=2 tags=system.cpu3.itb_walker_cache.tags tgts_per_mshr=12 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.cpu3.mmu.itb.walker.port mem_side=system.tol2bus.cpu_side_ports[14] [system.cpu3.itb_walker_cache.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu3.itb_walker_cache.replacement_policy] type=LRURP eventq_index=0 [system.cpu3.itb_walker_cache.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=2 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.cpu3.itb_walker_cache.tags.indexing_policy power_model= power_state=system.cpu3.itb_walker_cache.tags.power_state replacement_policy=system.cpu3.itb_walker_cache.replacement_policy sequential_access=false size=1024 system=system tag_latency=2 warmup_percentage=0 [system.cpu3.itb_walker_cache.tags.indexing_policy] type=SetAssociative assoc=2 entry_size=64 eventq_index=0 size=1024 [system.cpu3.itb_walker_cache.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu3.mmu] type=X86MMU children=dtb itb dtb=system.cpu3.mmu.dtb eventq_index=0 itb=system.cpu3.mmu.itb [system.cpu3.mmu.dtb] type=X86TLB children=walker entry_type=data eventq_index=0 next_level=Null size=64 system=system walker=system.cpu3.mmu.dtb.walker [system.cpu3.mmu.dtb.walker] type=X86PagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 power_model= power_state=system.cpu3.mmu.dtb.walker.power_state system=system port=system.cpu3.dtb_walker_cache.cpu_side [system.cpu3.mmu.dtb.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu3.mmu.itb] type=X86TLB children=walker entry_type=instruction eventq_index=0 next_level=Null size=64 system=system walker=system.cpu3.mmu.itb.walker [system.cpu3.mmu.itb.walker] type=X86PagetableWalker children=power_state clk_domain=system.cpu_clk_domain eventq_index=0 num_squash_per_cycle=4 power_model= power_state=system.cpu3.mmu.itb.walker.power_state system=system port=system.cpu3.itb_walker_cache.cpu_side [system.cpu3.mmu.itb.walker.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.cpu3.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states=ON CLK_GATED OFF [system.cpu3.tracer] type=ExeTracer eventq_index=0 [system.cpu3.workload] type=Process cmd=/bin/echo cwd=/home/carlos/projects/gem5 drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 executable=/bin/echo gid=1000 input=cin kvmInSE=false maxStackSize=67108864 output=cout pgid=100 pid=103 ppid=0 release=5.1.0 simpoint=0 system=system uid=100 useArchPT=false [system.cpu_clk_domain] type=SrcClockDomain clock=500 domain_id=-1 eventq_index=0 init_perf_level=0 voltage_domain=system.cpu_voltage_domain [system.cpu_voltage_domain] type=VoltageDomain eventq_index=0 voltage=1.0 [system.dvfs_handler] type=DVFSHandler domains= enable=false eventq_index=0 sys_clk_domain=system.clk_domain transition_latency=100000000 [system.l2] type=Cache children=power_state replacement_policy tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl compressor=Null data_latency=20 demand_mshr_reserve=1 eventq_index=0 is_read_only=false max_miss_count=0 move_contractions=true mshrs=20 power_model= power_state=system.l2.power_state prefetch_on_access=false prefetch_on_pf_hit=false prefetcher=Null replace_expansions=true replacement_policy=system.l2.replacement_policy response_latency=20 sequential_access=false size=1048576 system=system tag_latency=20 tags=system.l2.tags tgts_per_mshr=12 warmup_percentage=0 write_allocator=Null write_buffers=8 writeback_clean=false cpu_side=system.tol2bus.mem_side_ports[0] mem_side=system.membus.cpu_side_ports[1] [system.l2.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.l2.replacement_policy] type=LRURP eventq_index=0 [system.l2.tags] type=BaseSetAssoc children=indexing_policy power_state assoc=8 block_size=64 clk_domain=system.cpu_clk_domain entry_size=64 eventq_index=0 indexing_policy=system.l2.tags.indexing_policy power_model= power_state=system.l2.tags.power_state replacement_policy=system.l2.replacement_policy sequential_access=false size=1048576 system=system tag_latency=20 warmup_percentage=0 [system.l2.tags.indexing_policy] type=SetAssociative assoc=8 entry_size=64 eventq_index=0 size=1048576 [system.l2.tags.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.mem_ctrls] type=MemCtrl children=dram power_state clk_domain=system.clk_domain command_window=10000 disable_sanity_check=false dram=system.mem_ctrls.dram eventq_index=0 mem_sched_policy=frfcfs min_reads_per_switch=16 min_writes_per_switch=16 power_model= power_state=system.mem_ctrls.power_state qos_policy=Null qos_priorities=1 qos_priority_escalation=false qos_q_policy=fifo qos_requestors= qos_syncro_scheduler=false qos_turnaround_policy=Null static_backend_latency=10000 static_frontend_latency=10000 system=system write_high_thresh_perc=85 write_low_thresh_perc=50 port=system.membus.mem_side_ports[8] [system.mem_ctrls.dram] type=DRAMInterface children=power_state IDD0=0.055 IDD02=0.0 IDD2N=0.032 IDD2N2=0.0 IDD2P0=0.0 IDD2P02=0.0 IDD2P1=0.032 IDD2P12=0.0 IDD3N=0.038 IDD3N2=0.0 IDD3P0=0.0 IDD3P02=0.0 IDD3P1=0.038 IDD3P12=0.0 IDD4R=0.157 IDD4R2=0.0 IDD4W=0.125 IDD4W2=0.0 IDD5=0.23500000000000001 IDD52=0.0 IDD6=0.02 IDD62=0.0 VDD=1.5 VDD2=0.0 activation_limit=4 addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 beats_per_clock=2 burst_length=8 clk_domain=system.clk_domain conf_table_reported=true data_clock_sync=false device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 devices_per_rank=8 dll=true enable_dram_powerdown=false eventq_index=0 image_file= in_addr_map=true kvm_map=true max_accesses_per_row=16 null=false page_policy=open_adaptive power_model= power_state=system.mem_ctrls.dram.power_state range=0:536870912 ranks_per_channel=2 read_buffer_size=32 tAAD=1250 tBURST=5000 tBURST_MAX=5000 tBURST_MIN=5000 tCCD_L=0 tCCD_L_WR=0 tCK=1250 tCL=13750 tCS=2500 tCWL=13750 tPPD=0 tRAS=35000 tRCD=13750 tRCD_WR=13750 tREFI=7800000 tRFC=260000 tRP=13750 tRRD=6000 tRRD_L=0 tRTP=7500 tRTW=2500 tWR=15000 tWTR=7500 tWTR_L=7500 tXAW=30000 tXP=6000 tXPDLL=0 tXS=270000 tXSDLL=0 two_cycle_activate=false write_buffer_size=64 writeable=true [system.mem_ctrls.dram.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.mem_ctrls.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.membus] type=CoherentXBar children=power_state snoop_filter clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 header_latency=1 max_outstanding_snoops=512 max_routing_table_size=512 point_of_coherency=true point_of_unification=true power_model= power_state=system.membus.power_state response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false width=16 cpu_side_ports=system.system_port system.l2.mem_side system.cpu0.interrupts.int_requestor system.cpu1.interrupts.int_requestor system.cpu2.interrupts.int_requestor system.cpu3.interrupts.int_requestor mem_side_ports=system.cpu0.interrupts.pio system.cpu0.interrupts.int_responder system.cpu1.interrupts.pio system.cpu1.interrupts.int_responder system.cpu2.interrupts.pio system.cpu2.interrupts.int_responder system.cpu3.interrupts.pio system.cpu3.interrupts.int_responder system.mem_ctrls.port [system.membus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.membus.snoop_filter] type=SnoopFilter eventq_index=0 lookup_latency=1 max_capacity=8388608 system=system [system.redirect_paths0] type=RedirectPath app_path=/proc eventq_index=0 host_paths=/home/carlos/projects/gem5/gem5-data/results/smt/CMP4/fs/proc [system.redirect_paths1] type=RedirectPath app_path=/sys eventq_index=0 host_paths=/home/carlos/projects/gem5/gem5-data/results/smt/CMP4/fs/sys [system.redirect_paths2] type=RedirectPath app_path=/tmp eventq_index=0 host_paths=/home/carlos/projects/gem5/gem5-data/results/smt/CMP4/fs/tmp [system.tol2bus] type=CoherentXBar children=power_state snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 header_latency=1 max_outstanding_snoops=512 max_routing_table_size=512 point_of_coherency=false point_of_unification=true power_model= power_state=system.tol2bus.power_state response_latency=1 snoop_filter=system.tol2bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false width=32 cpu_side_ports=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb_walker_cache.mem_side system.cpu0.dtb_walker_cache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb_walker_cache.mem_side system.cpu1.dtb_walker_cache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu2.itb_walker_cache.mem_side system.cpu2.dtb_walker_cache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side system.cpu3.itb_walker_cache.mem_side system.cpu3.dtb_walker_cache.mem_side mem_side_ports=system.l2.cpu_side [system.tol2bus.power_state] type=PowerState clk_gate_bins=20 clk_gate_max=1000000000000 clk_gate_min=1000 default_state=UNDEFINED eventq_index=0 leaders= possible_states= [system.tol2bus.snoop_filter] type=SnoopFilter eventq_index=0 lookup_latency=0 max_capacity=8388608 system=system [system.voltage_domain] type=VoltageDomain eventq_index=0 voltage=1.0 [system.workload] type=X86EmuLinux eventq_index=0 remote_gdb_port=#7000 wait_for_remote_gdb=false