---------- Begin Simulation Statistics ----------
simSeconds                                   0.249692                       # Number of seconds simulated (Second)
simTicks                                 249692033000                       # Number of ticks simulated (Tick)
finalTick                                249692033000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq                                  1000000000000                       # The number of ticks per simulated second ((Tick/Second))
hostSeconds                                    333.22                       # Real time elapsed on the host (Second)
hostTickRate                                749321111                       # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory                                     672392                       # Number of bytes of host memory used (Byte)
simInsts                                     25297289                       # Number of instructions simulated (Count)
simOps                                       34841936                       # Number of ops (including micro ops) simulated (Count)
hostInstRate                                    75917                       # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate                                     104560                       # Simulator op (including micro ops) rate (op/s) ((Count/Second))
system.clk_domain.clock                           500                       # Clock period in ticks (Tick)
system.cpu.numCycles                        499384067                       # Number of cpu cycles simulated (Cycle)
system.cpu.cpi                              19.740616                       # CPI: cycles per instruction (core level) ((Cycle/Count))
system.cpu.ipc                               0.050657                       # IPC: instructions per cycle (core level) ((Count/Cycle))
system.cpu.numWorkItemsStarted                      0                       # Number of work items this cpu started (Count)
system.cpu.numWorkItemsCompleted                    0                       # Number of work items this cpu completed (Count)
system.cpu.instsAdded                        37752518                       # Number of instructions added to the IQ (excludes non-spec) (Count)
system.cpu.nonSpecInstsAdded                      234                       # Number of non-speculative instructions added to the IQ (Count)
system.cpu.instsIssued                       37744482                       # Number of instructions issued (Count)
system.cpu.squashedInstsIssued                    111                       # Number of squashed instructions issued (Count)
system.cpu.squashedInstsExamined              2910810                       # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
system.cpu.squashedOperandsExamined           1094925                       # Number of squashed operands that are examined and possibly removed from graph (Count)
system.cpu.squashedNonSpecRemoved                 144                       # Number of squashed non-spec instructions that were removed (Count)
system.cpu.numIssuedDist::samples           499325844                       # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::mean               0.075591                       # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::stdev              0.484716                       # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::underflows                0      0.00%      0.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::0                 484939217     97.12%     97.12% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::1                   3992045      0.80%     97.92% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::2                   1290531      0.26%     98.18% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::3                   5873799      1.18%     99.35% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::4                   2860307      0.57%     99.93% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::5                    236359      0.05%     99.97% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::6                     26802      0.01%     99.98% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::7                     88129      0.02%    100.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::8                     18655      0.00%    100.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::overflows                 0      0.00%    100.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::min_value                 0                       # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::max_value                 8                       # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::total             499325844                       # Number of insts issued each cycle (Count)
system.cpu.statFuBusy::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IntAlu                   24642     99.31%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IntMult                      0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IntDiv                       0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatAdd                     0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatCmp                     0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatCvt                     0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMult                    0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMultAcc                 0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatDiv                     0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMisc                    0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatSqrt                    0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAdd                      0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAddAcc                   0      0.00%     99.31% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAlu                     26      0.10%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdCmp                      0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdCvt                      1      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMisc                     0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMult                     0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMultAcc                  0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMatMultAcc               0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShift                    0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShiftAcc                 0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdDiv                      0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSqrt                     0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatAdd                 0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatAlu                 0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatCmp                 0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatCvt                 0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatDiv                 0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMisc                0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMult                0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMultAcc             0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMatMultAcc            0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatSqrt                0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdReduceAdd                0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdReduceAlu                0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdReduceCmp                0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatReduceAdd            0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatReduceCmp            0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAes                      0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAesMix                   0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha1Hash                 0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha1Hash2                0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha256Hash               0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha256Hash2              0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShaSigma2                0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShaSigma3                0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdPredAlu                  0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::Matrix                       0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MatrixMov                    0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MatrixOP                     0      0.00%     99.42% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MemRead                     82      0.33%     99.75% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MemWrite                    41      0.17%     99.92% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMemRead                 3      0.01%     99.93% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMemWrite               17      0.07%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideMaskLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideMaskStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorStridedLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorStridedStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIndexedLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIndexedStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorWholeRegisterLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorWholeRegisterStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIntegerArith            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorFloatArith             0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorFloatConvert            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIntegerReduce            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorFloatReduce            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorMisc                   0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIntegerExtension            0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorConfig                 0      0.00%    100.00% # attempts to use FU when none available (Count)
system.cpu.statIssuedInstType_0::No_OpClass          699      0.00%      0.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IntAlu      27485186     72.82%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IntMult           57      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IntDiv            81      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatAdd          185      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatCmp            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatCvt            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMult            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMultAcc            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatDiv            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMisc            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatSqrt            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAdd           10      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAddAcc            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAlu          309      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdCmp            4      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdCvt           92      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMisc          277      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMult            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMultAcc            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMatMultAcc            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShift            7      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShiftAcc            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdDiv            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSqrt            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatAdd            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatAlu            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatCmp            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatCvt            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatDiv            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMisc            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMult            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMultAcc            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMatMultAcc            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatSqrt            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdReduceAdd            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdReduceAlu            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdReduceCmp            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatReduceAdd            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatReduceCmp            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAes            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAesMix            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha1Hash            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha1Hash2            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha256Hash            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha256Hash2            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShaSigma2            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShaSigma3            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdPredAlu            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::Matrix             0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MatrixMov            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MatrixOP            0      0.00%     72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MemRead      3429566      9.09%     81.91% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MemWrite      6827197     18.09%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMemRead          192      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMemWrite          620      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IprAccess            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::InstPrefetch            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorStridedLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorStridedStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIndexedLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIndexedStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorWholeRegisterLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorWholeRegisterStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIntegerArith            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorFloatArith            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorFloatConvert            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIntegerReduce            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorFloatReduce            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorMisc            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIntegerExtension            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorConfig            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::total       37744482                       # Number of instructions issued per FU type, per thread (Count)
system.cpu.issueRate                         0.075582                       # Inst issue rate ((Count/Cycle))
system.cpu.fuBusy                               24812                       # FU busy when requested (Count)
system.cpu.fuBusyRate                        0.000657                       # FU busy rate (busy events/executed inst) ((Count/Count))
system.cpu.intInstQueueReads                574835909                       # Number of integer instruction queue reads (Count)
system.cpu.intInstQueueWrites                40661287                       # Number of integer instruction queue writes (Count)
system.cpu.intInstQueueWakeupAccesses        37478380                       # Number of integer instruction queue wakeup accesses (Count)
system.cpu.fpInstQueueReads                      3822                       # Number of floating instruction queue reads (Count)
system.cpu.fpInstQueueWrites                     2337                       # Number of floating instruction queue writes (Count)
system.cpu.fpInstQueueWakeupAccesses             1838                       # Number of floating instruction queue wakeup accesses (Count)
system.cpu.vecInstQueueReads                        0                       # Number of vector instruction queue reads (Count)
system.cpu.vecInstQueueWrites                       0                       # Number of vector instruction queue writes (Count)
system.cpu.vecInstQueueWakeupAccesses               0                       # Number of vector instruction queue wakeup accesses (Count)
system.cpu.intAluAccesses                    37766662                       # Number of integer alu accesses (Count)
system.cpu.fpAluAccesses                         1933                       # Number of floating point alu accesses (Count)
system.cpu.vecAluAccesses                           0                       # Number of vector alu accesses (Count)
system.cpu.numSquashedInsts                      1265                       # Number of squashed instructions skipped in execute (Count)
system.cpu.numSwp                                   0                       # Number of swp insts executed (Count)
system.cpu.timesIdled                             515                       # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
system.cpu.idleCycles                           58223                       # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
system.cpu.MemDepUnit__0.insertedLoads        3430582                       # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__0.insertedStores       6828519                       # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__0.conflictingLoads      2201707                       # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__0.conflictingStores       230307                       # Number of conflicting stores. (Count)
system.cpu.MemDepUnit__1.insertedLoads              0                       # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__1.insertedStores             0                       # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__1.conflictingLoads            0                       # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__1.conflictingStores            0                       # Number of conflicting stores. (Count)
system.cpu.MemDepUnit__2.insertedLoads              0                       # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__2.insertedStores             0                       # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__2.conflictingLoads            0                       # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__2.conflictingStores            0                       # Number of conflicting stores. (Count)
system.cpu.MemDepUnit__3.insertedLoads              0                       # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__3.insertedStores             0                       # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__3.conflictingLoads            0                       # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__3.conflictingStores            0                       # Number of conflicting stores. (Count)
system.cpu.branchPred.lookups                 3528004                       # Number of BP lookups (Count)
system.cpu.branchPred.condPredicted           3516195                       # Number of conditional branches predicted (Count)
system.cpu.branchPred.condIncorrect              1057                       # Number of conditional branches incorrect (Count)
system.cpu.branchPred.BTBLookups              3501437                       # Number of BTB lookups (Count)
system.cpu.branchPred.BTBUpdates                  917                       # Number of BTB updates (Count)
system.cpu.branchPred.BTBHits                 3500272                       # Number of BTB hits (Count)
system.cpu.branchPred.BTBHitRatio            0.999667                       # BTB Hit Ratio (Ratio)
system.cpu.branchPred.RASUsed                    2725                       # Number of times the RAS was used to get a target. (Count)
system.cpu.branchPred.RASIncorrect                  9                       # Number of incorrect RAS predictions. (Count)
system.cpu.branchPred.indirectLookups            2502                       # Number of indirect predictor lookups. (Count)
system.cpu.branchPred.indirectHits               2190                       # Number of indirect target hits. (Count)
system.cpu.branchPred.indirectMisses              312                       # Number of indirect misses. (Count)
system.cpu.branchPred.indirectMispredicted           87                       # Number of mispredicted indirect branches. (Count)
system.cpu.commit.commitSquashedInsts         2779396                       # The number of squashed insts skipped by commit (Count)
system.cpu.commit.commitNonSpecStalls              90                       # The number of times commit has been forced to stall to communicate backwards (Count)
system.cpu.commit.branchMispredicts               733                       # The number of times a branch was mispredicted (Count)
system.cpu.commit.numCommittedDist::samples    498977852                       # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::mean     0.069827                       # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::stdev     0.468608                       # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::underflows            0      0.00%      0.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::0       485870838     97.37%     97.37% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::1         3859564      0.77%     98.15% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::2          401486      0.08%     98.23% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::3         5788764      1.16%     99.39% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::4         2540490      0.51%     99.90% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::5          493480      0.10%    100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::6             387      0.00%    100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::7            1318      0.00%    100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::8           21525      0.00%    100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::overflows            0      0.00%    100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::min_value            0                       # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::max_value            8                       # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::total    498977852                       # Number of insts commited each cycle (Count)
system.cpu.commit.amos                              0                       # Number of atomic instructions committed (Count)
system.cpu.commit.membars                          60                       # Number of memory barriers committed (Count)
system.cpu.commit.functionCalls                  2380                       # Number of function calls committed. (Count)
system.cpu.commit.committedInstType_0::No_OpClass          327      0.00%      0.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntAlu     25373027     72.82%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntMult           50      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntDiv           63      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatAdd          154      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatCmp            0      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatCvt            0      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMult            0      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMultAcc            0      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatDiv            0      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMisc            0      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatSqrt            0      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAdd           10      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAddAcc            0      0.00%     72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAlu          247      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdCmp            4      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdCvt           84      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMisc          256      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMult            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMultAcc            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMatMultAcc            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShift            3      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShiftAcc            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdDiv            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSqrt            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatAdd            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatAlu            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatCmp            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatCvt            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatDiv            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMisc            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMult            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMultAcc            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMatMultAcc            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatSqrt            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdReduceAdd            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdReduceAlu            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdReduceCmp            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatReduceAdd            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatReduceCmp            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAes            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAesMix            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha1Hash            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha1Hash2            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha256Hash            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha256Hash2            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShaSigma2            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShaSigma3            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdPredAlu            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::Matrix            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MatrixMov            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MatrixOP            0      0.00%     72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MemRead      3165230      9.08%     81.91% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MemWrite      6301804     18.09%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMemRead          135      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMemWrite          542      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IprAccess            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideLoad            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideStore            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskLoad            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskStore            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorStridedLoad            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorStridedStore            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIndexedLoad            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIndexedStore            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorWholeRegisterLoad            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorWholeRegisterStore            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIntegerArith            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorFloatArith            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorFloatConvert            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIntegerReduce            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorFloatReduce            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorMisc            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIntegerExtension            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorConfig            0      0.00%    100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::total     34841936                       # Class of committed instruction (Count)
system.cpu.commit.commitEligibleSamples         21525                       # number cycles where commit BW limit reached (Cycle)
system.cpu.commitStats0.numInsts             25297289                       # Number of instructions committed (thread level) (Count)
system.cpu.commitStats0.numOps               34841936                       # Number of ops (including micro ops) committed (thread level) (Count)
system.cpu.commitStats0.numInstsNotNOP       25297289                       # Number of instructions committed excluding NOPs or prefetches (Count)
system.cpu.commitStats0.numOpsNotNOP         34841936                       # Number of Ops (including micro ops) Simulated (Count)
system.cpu.commitStats0.cpi                 19.740616                       # CPI: cycles per instruction (thread level) ((Cycle/Count))
system.cpu.commitStats0.ipc                  0.050657                       # IPC: instructions per cycle (thread level) ((Count/Cycle))
system.cpu.commitStats0.numMemRefs            9467711                       # Number of memory references committed (Count)
system.cpu.commitStats0.numFpInsts               1611                       # Number of float instructions (Count)
system.cpu.commitStats0.numIntInsts          34840630                       # Number of integer instructions (Count)
system.cpu.commitStats0.numLoadInsts          3165365                       # Number of load instructions (Count)
system.cpu.commitStats0.numStoreInsts         6302346                       # Number of store instructions (Count)
system.cpu.commitStats0.numVecInsts                 0                       # Number of vector instructions (Count)
system.cpu.commitStats0.committedInstType::No_OpClass          327      0.00%      0.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IntAlu     25373027     72.82%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IntMult           50      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IntDiv           63      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatAdd          154      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatCmp            0      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatCvt            0      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMult            0      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMultAcc            0      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatDiv            0      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMisc            0      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatSqrt            0      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAdd           10      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAddAcc            0      0.00%     72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAlu          247      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdCmp            4      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdCvt           84      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMisc          256      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMult            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMultAcc            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMatMultAcc            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShift            3      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShiftAcc            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdDiv            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSqrt            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatAdd            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatAlu            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatCmp            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatCvt            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatDiv            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMisc            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMult            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMultAcc            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMatMultAcc            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatSqrt            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdReduceAdd            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdReduceAlu            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdReduceCmp            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatReduceAdd            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatReduceCmp            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAes            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAesMix            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha1Hash            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha1Hash2            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha256Hash            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha256Hash2            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShaSigma2            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShaSigma3            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdPredAlu            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::Matrix            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MatrixMov            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MatrixOP            0      0.00%     72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MemRead      3165230      9.08%     81.91% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MemWrite      6301804     18.09%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMemRead          135      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMemWrite          542      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IprAccess            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::InstPrefetch            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideStore            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskStore            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorStridedLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorStridedStore            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIndexedLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIndexedStore            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorWholeRegisterLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorWholeRegisterStore            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIntegerArith            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorFloatArith            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorFloatConvert            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIntegerReduce            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorFloatReduce            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorMisc            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIntegerExtension            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorConfig            0      0.00%    100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::total     34841936                       # Class of committed instruction. (Count)
system.cpu.commitStats0.committedControl::IsControl      3179115                       # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsDirectControl      3174553                       # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsIndirectControl         4562                       # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsCondControl      3168897                       # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsUncondControl        10218                       # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsCall         2380                       # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsReturn         2375                       # Class of control type instructions committed (Count)
system.cpu.dcache.demandHits::cpu.data        3171567                       # number of demand (read+write) hits (Count)
system.cpu.dcache.demandHits::total           3171567                       # number of demand (read+write) hits (Count)
system.cpu.dcache.overallHits::cpu.data       3171567                       # number of overall hits (Count)
system.cpu.dcache.overallHits::total          3171567                       # number of overall hits (Count)
system.cpu.dcache.demandMisses::cpu.data      3147778                       # number of demand (read+write) misses (Count)
system.cpu.dcache.demandMisses::total         3147778                       # number of demand (read+write) misses (Count)
system.cpu.dcache.overallMisses::cpu.data      3147778                       # number of overall misses (Count)
system.cpu.dcache.overallMisses::total        3147778                       # number of overall misses (Count)
system.cpu.dcache.demandMissLatency::cpu.data 246213434998                       # number of demand (read+write) miss ticks (Tick)
system.cpu.dcache.demandMissLatency::total 246213434998                       # number of demand (read+write) miss ticks (Tick)
system.cpu.dcache.overallMissLatency::cpu.data 246213434998                       # number of overall miss ticks (Tick)
system.cpu.dcache.overallMissLatency::total 246213434998                       # number of overall miss ticks (Tick)
system.cpu.dcache.demandAccesses::cpu.data      6319345                       # number of demand (read+write) accesses (Count)
system.cpu.dcache.demandAccesses::total       6319345                       # number of demand (read+write) accesses (Count)
system.cpu.dcache.overallAccesses::cpu.data      6319345                       # number of overall (read+write) accesses (Count)
system.cpu.dcache.overallAccesses::total      6319345                       # number of overall (read+write) accesses (Count)
system.cpu.dcache.demandMissRate::cpu.data     0.498118                       # miss rate for demand accesses (Ratio)
system.cpu.dcache.demandMissRate::total      0.498118                       # miss rate for demand accesses (Ratio)
system.cpu.dcache.overallMissRate::cpu.data     0.498118                       # miss rate for overall accesses (Ratio)
system.cpu.dcache.overallMissRate::total     0.498118                       # miss rate for overall accesses (Ratio)
system.cpu.dcache.demandAvgMissLatency::cpu.data 78218.170086                       # average overall miss latency in ticks ((Tick/Count))
system.cpu.dcache.demandAvgMissLatency::total 78218.170086                       # average overall miss latency in ticks ((Tick/Count))
system.cpu.dcache.overallAvgMissLatency::cpu.data 78218.170086                       # average overall miss latency ((Tick/Count))
system.cpu.dcache.overallAvgMissLatency::total 78218.170086                       # average overall miss latency ((Tick/Count))
system.cpu.dcache.blockedCycles::no_mshrs         1273                       # number of cycles access was blocked (Cycle)
system.cpu.dcache.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
system.cpu.dcache.blockedCauses::no_mshrs           22                       # number of times access was blocked (Count)
system.cpu.dcache.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
system.cpu.dcache.avgBlocked::no_mshrs      57.863636                       # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dcache.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dcache.writebacks::writebacks      3145487                       # number of writebacks (Count)
system.cpu.dcache.writebacks::total           3145487                       # number of writebacks (Count)
system.cpu.dcache.demandMshrHits::cpu.data         1073                       # number of demand (read+write) MSHR hits (Count)
system.cpu.dcache.demandMshrHits::total          1073                       # number of demand (read+write) MSHR hits (Count)
system.cpu.dcache.overallMshrHits::cpu.data         1073                       # number of overall MSHR hits (Count)
system.cpu.dcache.overallMshrHits::total         1073                       # number of overall MSHR hits (Count)
system.cpu.dcache.demandMshrMisses::cpu.data      3146705                       # number of demand (read+write) MSHR misses (Count)
system.cpu.dcache.demandMshrMisses::total      3146705                       # number of demand (read+write) MSHR misses (Count)
system.cpu.dcache.overallMshrMisses::cpu.data      3146705                       # number of overall MSHR misses (Count)
system.cpu.dcache.overallMshrMisses::total      3146705                       # number of overall MSHR misses (Count)
system.cpu.dcache.demandMshrMissLatency::cpu.data 242993954498                       # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.dcache.demandMshrMissLatency::total 242993954498                       # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.dcache.overallMshrMissLatency::cpu.data 242993954498                       # number of overall MSHR miss ticks (Tick)
system.cpu.dcache.overallMshrMissLatency::total 242993954498                       # number of overall MSHR miss ticks (Tick)
system.cpu.dcache.demandMshrMissRate::cpu.data     0.497948                       # mshr miss ratio for demand accesses (Ratio)
system.cpu.dcache.demandMshrMissRate::total     0.497948                       # mshr miss ratio for demand accesses (Ratio)
system.cpu.dcache.overallMshrMissRate::cpu.data     0.497948                       # mshr miss ratio for overall accesses (Ratio)
system.cpu.dcache.overallMshrMissRate::total     0.497948                       # mshr miss ratio for overall accesses (Ratio)
system.cpu.dcache.demandAvgMshrMissLatency::cpu.data 77221.714301                       # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.demandAvgMshrMissLatency::total 77221.714301                       # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.overallAvgMshrMissLatency::cpu.data 77221.714301                       # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.overallAvgMshrMissLatency::total 77221.714301                       # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.replacements                3146195                       # number of replacements (Count)
system.cpu.dcache.LockedRMWReadReq.hits::cpu.data           26                       # number of LockedRMWReadReq hits (Count)
system.cpu.dcache.LockedRMWReadReq.hits::total           26                       # number of LockedRMWReadReq hits (Count)
system.cpu.dcache.LockedRMWReadReq.misses::cpu.data            4                       # number of LockedRMWReadReq misses (Count)
system.cpu.dcache.LockedRMWReadReq.misses::total            4                       # number of LockedRMWReadReq misses (Count)
system.cpu.dcache.LockedRMWReadReq.missLatency::cpu.data       347000                       # number of LockedRMWReadReq miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.missLatency::total       347000                       # number of LockedRMWReadReq miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.accesses::cpu.data           30                       # number of LockedRMWReadReq accesses(hits+misses) (Count)
system.cpu.dcache.LockedRMWReadReq.accesses::total           30                       # number of LockedRMWReadReq accesses(hits+misses) (Count)
system.cpu.dcache.LockedRMWReadReq.missRate::cpu.data     0.133333                       # miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.missRate::total     0.133333                       # miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::cpu.data        86750                       # average LockedRMWReadReq miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::total        86750                       # average LockedRMWReadReq miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWReadReq.mshrMisses::cpu.data            4                       # number of LockedRMWReadReq MSHR misses (Count)
system.cpu.dcache.LockedRMWReadReq.mshrMisses::total            4                       # number of LockedRMWReadReq MSHR misses (Count)
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::cpu.data       803500                       # number of LockedRMWReadReq MSHR miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::total       803500                       # number of LockedRMWReadReq MSHR miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::cpu.data     0.133333                       # mshr miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::total     0.133333                       # mshr miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu.data       200875                       # average LockedRMWReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::total       200875                       # average LockedRMWReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWWriteReq.hits::cpu.data           30                       # number of LockedRMWWriteReq hits (Count)
system.cpu.dcache.LockedRMWWriteReq.hits::total           30                       # number of LockedRMWWriteReq hits (Count)
system.cpu.dcache.LockedRMWWriteReq.accesses::cpu.data           30                       # number of LockedRMWWriteReq accesses(hits+misses) (Count)
system.cpu.dcache.LockedRMWWriteReq.accesses::total           30                       # number of LockedRMWWriteReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.hits::cpu.data        15147                       # number of ReadReq hits (Count)
system.cpu.dcache.ReadReq.hits::total           15147                       # number of ReadReq hits (Count)
system.cpu.dcache.ReadReq.misses::cpu.data         1882                       # number of ReadReq misses (Count)
system.cpu.dcache.ReadReq.misses::total          1882                       # number of ReadReq misses (Count)
system.cpu.dcache.ReadReq.missLatency::cpu.data    131497000                       # number of ReadReq miss ticks (Tick)
system.cpu.dcache.ReadReq.missLatency::total    131497000                       # number of ReadReq miss ticks (Tick)
system.cpu.dcache.ReadReq.accesses::cpu.data        17029                       # number of ReadReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.accesses::total        17029                       # number of ReadReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.missRate::cpu.data     0.110517                       # miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.missRate::total     0.110517                       # miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.avgMissLatency::cpu.data 69870.882040                       # average ReadReq miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.avgMissLatency::total 69870.882040                       # average ReadReq miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.mshrHits::cpu.data         1072                       # number of ReadReq MSHR hits (Count)
system.cpu.dcache.ReadReq.mshrHits::total         1072                       # number of ReadReq MSHR hits (Count)
system.cpu.dcache.ReadReq.mshrMisses::cpu.data          810                       # number of ReadReq MSHR misses (Count)
system.cpu.dcache.ReadReq.mshrMisses::total          810                       # number of ReadReq MSHR misses (Count)
system.cpu.dcache.ReadReq.mshrMissLatency::cpu.data     57918000                       # number of ReadReq MSHR miss ticks (Tick)
system.cpu.dcache.ReadReq.mshrMissLatency::total     57918000                       # number of ReadReq MSHR miss ticks (Tick)
system.cpu.dcache.ReadReq.mshrMissRate::cpu.data     0.047566                       # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.mshrMissRate::total     0.047566                       # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.avgMshrMissLatency::cpu.data 71503.703704                       # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.avgMshrMissLatency::total 71503.703704                       # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.hits::cpu.data      3156420                       # number of WriteReq hits (Count)
system.cpu.dcache.WriteReq.hits::total        3156420                       # number of WriteReq hits (Count)
system.cpu.dcache.WriteReq.misses::cpu.data      3145896                       # number of WriteReq misses (Count)
system.cpu.dcache.WriteReq.misses::total      3145896                       # number of WriteReq misses (Count)
system.cpu.dcache.WriteReq.missLatency::cpu.data 246081937998                       # number of WriteReq miss ticks (Tick)
system.cpu.dcache.WriteReq.missLatency::total 246081937998                       # number of WriteReq miss ticks (Tick)
system.cpu.dcache.WriteReq.accesses::cpu.data      6302316                       # number of WriteReq accesses(hits+misses) (Count)
system.cpu.dcache.WriteReq.accesses::total      6302316                       # number of WriteReq accesses(hits+misses) (Count)
system.cpu.dcache.WriteReq.missRate::cpu.data     0.499165                       # miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.missRate::total     0.499165                       # miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.avgMissLatency::cpu.data 78223.163766                       # average WriteReq miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.avgMissLatency::total 78223.163766                       # average WriteReq miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.mshrHits::cpu.data            1                       # number of WriteReq MSHR hits (Count)
system.cpu.dcache.WriteReq.mshrHits::total            1                       # number of WriteReq MSHR hits (Count)
system.cpu.dcache.WriteReq.mshrMisses::cpu.data      3145895                       # number of WriteReq MSHR misses (Count)
system.cpu.dcache.WriteReq.mshrMisses::total      3145895                       # number of WriteReq MSHR misses (Count)
system.cpu.dcache.WriteReq.mshrMissLatency::cpu.data 242936036498                       # number of WriteReq MSHR miss ticks (Tick)
system.cpu.dcache.WriteReq.mshrMissLatency::total 242936036498                       # number of WriteReq MSHR miss ticks (Tick)
system.cpu.dcache.WriteReq.mshrMissRate::cpu.data     0.499165                       # mshr miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.mshrMissRate::total     0.499165                       # mshr miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.avgMshrMissLatency::cpu.data 77223.186565                       # average WriteReq mshr miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.avgMshrMissLatency::total 77223.186565                       # average WriteReq mshr miss latency ((Tick/Count))
system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.dcache.tags.tagsInUse           511.925925                       # Average ticks per tags in use ((Tick/Count))
system.cpu.dcache.tags.totalRefs              6318332                       # Total number of references to valid blocks. (Count)
system.cpu.dcache.tags.sampledRefs            3146707                       # Sample count of references to valid blocks. (Count)
system.cpu.dcache.tags.avgRefs               2.007919                       # Average number of references to valid blocks. ((Count/Count))
system.cpu.dcache.tags.warmupTick              165500                       # The tick when the warmup percentage was hit. (Tick)
system.cpu.dcache.tags.occupancies::cpu.data   511.925925                       # Average occupied blocks per tick, per requestor ((Count/Tick))
system.cpu.dcache.tags.avgOccs::cpu.data     0.999855                       # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.dcache.tags.avgOccs::total        0.999855                       # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.dcache.tags.occupanciesTaskId::1024          512                       # Occupied blocks per task id (Count)
system.cpu.dcache.tags.ageTaskId_1024::0           51                       # Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ageTaskId_1024::1          460                       # Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ageTaskId_1024::4            1                       # Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ratioOccsTaskId::1024            1                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
system.cpu.dcache.tags.tagAccesses           15785517                       # Number of tag accesses (Count)
system.cpu.dcache.tags.dataAccesses          15785517                       # Number of data accesses (Count)
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.decode.idleCycles                  1630013                       # Number of cycles decode is idle (Cycle)
system.cpu.decode.blockedCycles             492822344                       # Number of cycles decode is blocked (Cycle)
system.cpu.decode.runCycles                    508124                       # Number of cycles decode is running (Cycle)
system.cpu.decode.unblockCycles               4348164                       # Number of cycles decode is unblocking (Cycle)
system.cpu.decode.squashCycles                  17199                       # Number of cycles decode is squashing (Cycle)
system.cpu.decode.branchResolved              3434798                       # Number of times decode resolved a branch (Count)
system.cpu.decode.branchMispred                   376                       # Number of times decode detected a branch misprediction (Count)
system.cpu.decode.decodedInsts               37938642                       # Number of instructions handled by decode (Count)
system.cpu.decode.squashedInsts                  1747                       # Number of squashed instructions handled by decode (Count)
system.cpu.dtb_walker_cache.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
system.cpu.dtb_walker_cache.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
system.cpu.dtb_walker_cache.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
system.cpu.dtb_walker_cache.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
system.cpu.dtb_walker_cache.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dtb_walker_cache.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dtb_walker_cache.replacements            0                       # number of replacements (Count)
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.dtb_walker_cache.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
system.cpu.dtb_walker_cache.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
system.cpu.dtb_walker_cache.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
system.cpu.dtb_walker_cache.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
system.cpu.dtb_walker_cache.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
system.cpu.dtb_walker_cache.tags.tagAccesses            0                       # Number of tag accesses (Count)
system.cpu.dtb_walker_cache.tags.dataAccesses            0                       # Number of data accesses (Count)
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.executeStats0.numInsts            37743217                       # Number of executed instructions (Count)
system.cpu.executeStats0.numNop                     0                       # Number of nop insts executed (Count)
system.cpu.executeStats0.numBranches          3442570                       # Number of branches executed (Count)
system.cpu.executeStats0.numLoadInsts         3429486                       # Number of load instructions executed (Count)
system.cpu.executeStats0.numStoreInsts        6827693                       # Number of stores executed (Count)
system.cpu.executeStats0.instRate            0.075580                       # Inst execution rate ((Count/Cycle))
system.cpu.executeStats0.numCCRegReads       17201075                       # Number of times the CC registers were read (Count)
system.cpu.executeStats0.numCCRegWrites      20532311                       # Number of times the CC registers were written (Count)
system.cpu.executeStats0.numFpRegReads           2256                       # Number of times the floating registers were read (Count)
system.cpu.executeStats0.numFpRegWrites          1155                       # Number of times the floating registers were written (Count)
system.cpu.executeStats0.numIntRegReads      61673765                       # Number of times the integer registers were read (Count)
system.cpu.executeStats0.numIntRegWrites     24037994                       # Number of times the integer registers were written (Count)
system.cpu.executeStats0.numMemRefs          10257179                       # Number of memory refs (Count)
system.cpu.executeStats0.numMiscRegReads     17142215                       # Number of times the Misc registers were read (Count)
system.cpu.executeStats0.numVecAluAccesses            0                       # Number of vector alu accesses (Count)
system.cpu.executeStats0.numDiscardedOps            0                       # Number of ops (including micro ops) which were discarded before commit (Count)
system.cpu.fetch.predictedBranches            3505187                       # Number of branches that fetch has predicted taken (Count)
system.cpu.fetch.cycles                     499259765                       # Number of cycles fetch has run and was not squashing or blocked (Cycle)
system.cpu.fetch.squashCycles                   35138                       # Number of cycles fetch has spent squashing (Cycle)
system.cpu.fetch.miscStallCycles                   52                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
system.cpu.fetch.pendingTrapStallCycles           295                       # Number of stall cycles due to pending traps (Cycle)
system.cpu.fetch.cacheLines                     20710                       # Number of cache lines fetched (Count)
system.cpu.fetch.icacheSquashes                   558                       # Number of outstanding Icache misses that were squashed (Count)
system.cpu.fetch.nisnDist::samples          499325844                       # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::mean              0.077573                       # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::stdev             0.697976                       # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::0                491482759     98.43%     98.43% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::1                   821393      0.16%     98.59% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::2                   820685      0.16%     98.76% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::3                  1869138      0.37%     99.13% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::4                   399640      0.08%     99.21% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::5                   394705      0.08%     99.29% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::6                   396774      0.08%     99.37% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::7                   414562      0.08%     99.45% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::8                  2726188      0.55%    100.00% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::min_value                0                       # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::max_value                8                       # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::total            499325844                       # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetchStats0.numInsts              28138169                       # Number of instructions fetched (thread level) (Count)
system.cpu.fetchStats0.numOps                       0                       # Number of ops (including micro ops) fetched (thread level) (Count)
system.cpu.fetchStats0.fetchRate             0.056346                       # Number of inst fetches per cycle ((Count/Cycle))
system.cpu.fetchStats0.numBranches            3528004                       # Number of branches fetched (Count)
system.cpu.fetchStats0.branchRate            0.007065                       # Number of branch fetches per cycle (Ratio)
system.cpu.fetchStats0.icacheStallCycles        48163                       # ICache total stall cycles (Cycle)
system.cpu.fetchStats0.numFetchSuspends             0                       # Number of times Execute suspended instruction fetching (Count)
system.cpu.icache.demandHits::cpu.inst          19681                       # number of demand (read+write) hits (Count)
system.cpu.icache.demandHits::total             19681                       # number of demand (read+write) hits (Count)
system.cpu.icache.overallHits::cpu.inst         19681                       # number of overall hits (Count)
system.cpu.icache.overallHits::total            19681                       # number of overall hits (Count)
system.cpu.icache.demandMisses::cpu.inst         1029                       # number of demand (read+write) misses (Count)
system.cpu.icache.demandMisses::total            1029                       # number of demand (read+write) misses (Count)
system.cpu.icache.overallMisses::cpu.inst         1029                       # number of overall misses (Count)
system.cpu.icache.overallMisses::total           1029                       # number of overall misses (Count)
system.cpu.icache.demandMissLatency::cpu.inst     72754500                       # number of demand (read+write) miss ticks (Tick)
system.cpu.icache.demandMissLatency::total     72754500                       # number of demand (read+write) miss ticks (Tick)
system.cpu.icache.overallMissLatency::cpu.inst     72754500                       # number of overall miss ticks (Tick)
system.cpu.icache.overallMissLatency::total     72754500                       # number of overall miss ticks (Tick)
system.cpu.icache.demandAccesses::cpu.inst        20710                       # number of demand (read+write) accesses (Count)
system.cpu.icache.demandAccesses::total         20710                       # number of demand (read+write) accesses (Count)
system.cpu.icache.overallAccesses::cpu.inst        20710                       # number of overall (read+write) accesses (Count)
system.cpu.icache.overallAccesses::total        20710                       # number of overall (read+write) accesses (Count)
system.cpu.icache.demandMissRate::cpu.inst     0.049686                       # miss rate for demand accesses (Ratio)
system.cpu.icache.demandMissRate::total      0.049686                       # miss rate for demand accesses (Ratio)
system.cpu.icache.overallMissRate::cpu.inst     0.049686                       # miss rate for overall accesses (Ratio)
system.cpu.icache.overallMissRate::total     0.049686                       # miss rate for overall accesses (Ratio)
system.cpu.icache.demandAvgMissLatency::cpu.inst 70704.081633                       # average overall miss latency in ticks ((Tick/Count))
system.cpu.icache.demandAvgMissLatency::total 70704.081633                       # average overall miss latency in ticks ((Tick/Count))
system.cpu.icache.overallAvgMissLatency::cpu.inst 70704.081633                       # average overall miss latency ((Tick/Count))
system.cpu.icache.overallAvgMissLatency::total 70704.081633                       # average overall miss latency ((Tick/Count))
system.cpu.icache.blockedCycles::no_mshrs          276                       # number of cycles access was blocked (Cycle)
system.cpu.icache.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
system.cpu.icache.blockedCauses::no_mshrs            6                       # number of times access was blocked (Count)
system.cpu.icache.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
system.cpu.icache.avgBlocked::no_mshrs             46                       # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.icache.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.icache.writebacks::writebacks          344                       # number of writebacks (Count)
system.cpu.icache.writebacks::total               344                       # number of writebacks (Count)
system.cpu.icache.demandMshrHits::cpu.inst          220                       # number of demand (read+write) MSHR hits (Count)
system.cpu.icache.demandMshrHits::total           220                       # number of demand (read+write) MSHR hits (Count)
system.cpu.icache.overallMshrHits::cpu.inst          220                       # number of overall MSHR hits (Count)
system.cpu.icache.overallMshrHits::total          220                       # number of overall MSHR hits (Count)
system.cpu.icache.demandMshrMisses::cpu.inst          809                       # number of demand (read+write) MSHR misses (Count)
system.cpu.icache.demandMshrMisses::total          809                       # number of demand (read+write) MSHR misses (Count)
system.cpu.icache.overallMshrMisses::cpu.inst          809                       # number of overall MSHR misses (Count)
system.cpu.icache.overallMshrMisses::total          809                       # number of overall MSHR misses (Count)
system.cpu.icache.demandMshrMissLatency::cpu.inst     60173000                       # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.icache.demandMshrMissLatency::total     60173000                       # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.icache.overallMshrMissLatency::cpu.inst     60173000                       # number of overall MSHR miss ticks (Tick)
system.cpu.icache.overallMshrMissLatency::total     60173000                       # number of overall MSHR miss ticks (Tick)
system.cpu.icache.demandMshrMissRate::cpu.inst     0.039063                       # mshr miss ratio for demand accesses (Ratio)
system.cpu.icache.demandMshrMissRate::total     0.039063                       # mshr miss ratio for demand accesses (Ratio)
system.cpu.icache.overallMshrMissRate::cpu.inst     0.039063                       # mshr miss ratio for overall accesses (Ratio)
system.cpu.icache.overallMshrMissRate::total     0.039063                       # mshr miss ratio for overall accesses (Ratio)
system.cpu.icache.demandAvgMshrMissLatency::cpu.inst 74379.480841                       # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.demandAvgMshrMissLatency::total 74379.480841                       # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.overallAvgMshrMissLatency::cpu.inst 74379.480841                       # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.overallAvgMshrMissLatency::total 74379.480841                       # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.replacements                    344                       # number of replacements (Count)
system.cpu.icache.ReadReq.hits::cpu.inst        19681                       # number of ReadReq hits (Count)
system.cpu.icache.ReadReq.hits::total           19681                       # number of ReadReq hits (Count)
system.cpu.icache.ReadReq.misses::cpu.inst         1029                       # number of ReadReq misses (Count)
system.cpu.icache.ReadReq.misses::total          1029                       # number of ReadReq misses (Count)
system.cpu.icache.ReadReq.missLatency::cpu.inst     72754500                       # number of ReadReq miss ticks (Tick)
system.cpu.icache.ReadReq.missLatency::total     72754500                       # number of ReadReq miss ticks (Tick)
system.cpu.icache.ReadReq.accesses::cpu.inst        20710                       # number of ReadReq accesses(hits+misses) (Count)
system.cpu.icache.ReadReq.accesses::total        20710                       # number of ReadReq accesses(hits+misses) (Count)
system.cpu.icache.ReadReq.missRate::cpu.inst     0.049686                       # miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.missRate::total     0.049686                       # miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.avgMissLatency::cpu.inst 70704.081633                       # average ReadReq miss latency ((Tick/Count))
system.cpu.icache.ReadReq.avgMissLatency::total 70704.081633                       # average ReadReq miss latency ((Tick/Count))
system.cpu.icache.ReadReq.mshrHits::cpu.inst          220                       # number of ReadReq MSHR hits (Count)
system.cpu.icache.ReadReq.mshrHits::total          220                       # number of ReadReq MSHR hits (Count)
system.cpu.icache.ReadReq.mshrMisses::cpu.inst          809                       # number of ReadReq MSHR misses (Count)
system.cpu.icache.ReadReq.mshrMisses::total          809                       # number of ReadReq MSHR misses (Count)
system.cpu.icache.ReadReq.mshrMissLatency::cpu.inst     60173000                       # number of ReadReq MSHR miss ticks (Tick)
system.cpu.icache.ReadReq.mshrMissLatency::total     60173000                       # number of ReadReq MSHR miss ticks (Tick)
system.cpu.icache.ReadReq.mshrMissRate::cpu.inst     0.039063                       # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.mshrMissRate::total     0.039063                       # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.avgMshrMissLatency::cpu.inst 74379.480841                       # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.icache.ReadReq.avgMshrMissLatency::total 74379.480841                       # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.icache.tags.tagsInUse           407.969381                       # Average ticks per tags in use ((Tick/Count))
system.cpu.icache.tags.totalRefs                20489                       # Total number of references to valid blocks. (Count)
system.cpu.icache.tags.sampledRefs                808                       # Sample count of references to valid blocks. (Count)
system.cpu.icache.tags.avgRefs              25.357673                       # Average number of references to valid blocks. ((Count/Count))
system.cpu.icache.tags.warmupTick               82000                       # The tick when the warmup percentage was hit. (Tick)
system.cpu.icache.tags.occupancies::cpu.inst   407.969381                       # Average occupied blocks per tick, per requestor ((Count/Tick))
system.cpu.icache.tags.avgOccs::cpu.inst     0.796815                       # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.icache.tags.avgOccs::total        0.796815                       # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.icache.tags.occupanciesTaskId::1024          462                       # Occupied blocks per task id (Count)
system.cpu.icache.tags.ageTaskId_1024::0          124                       # Occupied blocks per task id, per block age (Count)
system.cpu.icache.tags.ageTaskId_1024::1           66                       # Occupied blocks per task id, per block age (Count)
system.cpu.icache.tags.ageTaskId_1024::4          272                       # Occupied blocks per task id, per block age (Count)
system.cpu.icache.tags.ratioOccsTaskId::1024     0.902344                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
system.cpu.icache.tags.tagAccesses              42228                       # Number of tag accesses (Count)
system.cpu.icache.tags.dataAccesses             42228                       # Number of data accesses (Count)
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.iew.idleCycles                           0                       # Number of cycles IEW is idle (Cycle)
system.cpu.iew.squashCycles                     17199                       # Number of cycles IEW is squashing (Cycle)
system.cpu.iew.blockCycles                     394613                       # Number of cycles IEW is blocking (Cycle)
system.cpu.iew.unblockCycles                251481030                       # Number of cycles IEW is unblocking (Cycle)
system.cpu.iew.dispatchedInsts               37752752                       # Number of instructions dispatched to IQ (Count)
system.cpu.iew.dispSquashedInsts                   97                       # Number of squashed instructions skipped by dispatch (Count)
system.cpu.iew.dispLoadInsts                  3430582                       # Number of dispatched load instructions (Count)
system.cpu.iew.dispStoreInsts                 6828519                       # Number of dispatched store instructions (Count)
system.cpu.iew.dispNonSpecInsts                    79                       # Number of dispatched non-speculative instructions (Count)
system.cpu.iew.iqFullEvents                      1643                       # Number of times the IQ has become full, causing a stall (Count)
system.cpu.iew.lsqFullEvents                251495773                       # Number of times the LSQ has become full, causing a stall (Count)
system.cpu.iew.memOrderViolationEvents             65                       # Number of memory order violations (Count)
system.cpu.iew.predictedTakenIncorrect             72                       # Number of branches that were predicted taken incorrectly (Count)
system.cpu.iew.predictedNotTakenIncorrect          770                       # Number of branches that were predicted not taken incorrectly (Count)
system.cpu.iew.branchMispredicts                  842                       # Number of branch mispredicts detected at execute (Count)
system.cpu.iew.instsToCommit                 37742764                       # Cumulative count of insts sent to commit (Count)
system.cpu.iew.writebackCount                37480218                       # Cumulative count of insts written-back (Count)
system.cpu.iew.producerInst                  14701434                       # Number of instructions producing a value (Count)
system.cpu.iew.consumerInst                  23556803                       # Number of instructions consuming a value (Count)
system.cpu.iew.wbRate                        0.075053                       # Insts written-back per cycle ((Count/Cycle))
system.cpu.iew.wbFanout                      0.624084                       # Average fanout of values written-back ((Count/Count))
system.cpu.interrupts.clk_domain.clock           8000                       # Clock period in ticks (Tick)
system.cpu.itb_walker_cache.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
system.cpu.itb_walker_cache.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
system.cpu.itb_walker_cache.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
system.cpu.itb_walker_cache.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
system.cpu.itb_walker_cache.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.itb_walker_cache.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.itb_walker_cache.replacements            0                       # number of replacements (Count)
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.itb_walker_cache.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
system.cpu.itb_walker_cache.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
system.cpu.itb_walker_cache.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
system.cpu.itb_walker_cache.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
system.cpu.itb_walker_cache.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
system.cpu.itb_walker_cache.tags.tagAccesses            0                       # Number of tag accesses (Count)
system.cpu.itb_walker_cache.tags.dataAccesses            0                       # Number of data accesses (Count)
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.lsq0.forwLoads                     3412276                       # Number of loads that had data forwarded from stores (Count)
system.cpu.lsq0.squashedLoads                  265217                       # Number of loads squashed (Count)
system.cpu.lsq0.ignoredResponses                    5                       # Number of memory responses ignored because the instruction is squashed (Count)
system.cpu.lsq0.memOrderViolation                  65                       # Number of memory ordering violations (Count)
system.cpu.lsq0.squashedStores                 526173                       # Number of stores squashed (Count)
system.cpu.lsq0.rescheduledLoads                    2                       # Number of loads that were rescheduled (Count)
system.cpu.lsq0.blockedByCache                     16                       # Number of times an access to memory failed due to the cache being blocked (Count)
system.cpu.lsq0.loadToUse::samples            3165365                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::mean              2.080214                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::stdev             3.458004                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::0-9                3163671     99.95%     99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::10-19                    2      0.00%     99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::20-29                   13      0.00%     99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::30-39                    6      0.00%     99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::90-99                    2      0.00%     99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::100-109                 12      0.00%     99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::110-119                 34      0.00%     99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::120-129                195      0.01%     99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::130-139               1193      0.04%     99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::140-149                 37      0.00%     99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::150-159                 32      0.00%     99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::160-169                 75      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::170-179                  2      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::180-189                  3      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::190-199                 49      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::200-209                 10      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::240-249                  2      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::250-259                  1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::280-289                  1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::290-299                  1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::overflows               24      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::min_value                2                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::max_value              681                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::total              3165365                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.mmu.dtb.rdAccesses                 3429435                       # TLB accesses on read requests (Count)
system.cpu.mmu.dtb.wrAccesses                 6827693                       # TLB accesses on write requests (Count)
system.cpu.mmu.dtb.rdMisses                       137                       # TLB misses on read requests (Count)
system.cpu.mmu.dtb.wrMisses                    311321                       # TLB misses on write requests (Count)
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.mmu.itb.rdAccesses                       0                       # TLB accesses on read requests (Count)
system.cpu.mmu.itb.wrAccesses                   20763                       # TLB accesses on write requests (Count)
system.cpu.mmu.itb.rdMisses                         0                       # TLB misses on read requests (Count)
system.cpu.mmu.itb.wrMisses                       124                       # TLB misses on write requests (Count)
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.power_state.pwrStateResidencyTicks::ON 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.cpu.rename.squashCycles                  17199                       # Number of cycles rename is squashing (Cycle)
system.cpu.rename.idleCycles                  2861397                       # Number of cycles rename is idle (Cycle)
system.cpu.rename.blockCycles               251879752                       # Number of cycles rename is blocking (Cycle)
system.cpu.rename.serializeStallCycles           1288                       # count of cycles rename stalled for serializing inst (Cycle)
system.cpu.rename.runCycles                   3608137                       # Number of cycles rename is running (Cycle)
system.cpu.rename.unblockCycles             240958071                       # Number of cycles rename is unblocking (Cycle)
system.cpu.rename.renamedInsts               37805484                       # Number of instructions processed by rename (Count)
system.cpu.rename.ROBFullEvents                    26                       # Number of times rename has blocked due to ROB full (Count)
system.cpu.rename.IQFullEvents                  10754                       # Number of times rename has blocked due to IQ full (Count)
system.cpu.rename.SQFullEvents              240092670                       # Number of times rename has blocked due to SQ full (Count)
system.cpu.rename.renamedOperands            79026304                       # Number of destination operands rename has renamed (Count)
system.cpu.rename.lookups                   154553181                       # Number of register rename lookups that rename has made (Count)
system.cpu.rename.intLookups                 61810091                       # Number of integer rename lookups (Count)
system.cpu.rename.fpLookups                      2456                       # Number of floating rename lookups (Count)
system.cpu.rename.committedMaps              72751303                       # Number of HB maps that are committed (Count)
system.cpu.rename.undoneMaps                  6274992                       # Number of HB maps that are undone due to squashing (Count)
system.cpu.rename.serializing                      45                       # count of serializing insts renamed (Count)
system.cpu.rename.tempSerializing                  45                       # count of temporary serializing insts renamed (Count)
system.cpu.rename.skidInsts                  23399852                       # count of insts added to the skid buffer (Count)
system.cpu.rob.reads                        536364381                       # The number of ROB reads (Count)
system.cpu.rob.writes                        75590701                       # The number of ROB writes (Count)
system.cpu.thread_0.numInsts                 25297289                       # Number of Instructions committed (Count)
system.cpu.thread_0.numOps                   34841936                       # Number of Ops committed (Count)
system.cpu.thread_0.numMemRefs                      0                       # Number of Memory References (Count)
system.cpu.workload.numSyscalls                    18                       # Number of system calls (Count)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks (Tick)
system.cpu_voltage_domain.voltage                   1                       # Voltage in Volts (Volt)
system.l2.demandHits::cpu.inst                     29                       # number of demand (read+write) hits (Count)
system.l2.demandHits::cpu.data                     28                       # number of demand (read+write) hits (Count)
system.l2.demandHits::total                        57                       # number of demand (read+write) hits (Count)
system.l2.overallHits::cpu.inst                    29                       # number of overall hits (Count)
system.l2.overallHits::cpu.data                    28                       # number of overall hits (Count)
system.l2.overallHits::total                       57                       # number of overall hits (Count)
system.l2.demandMisses::cpu.inst                  778                       # number of demand (read+write) misses (Count)
system.l2.demandMisses::cpu.data              3146679                       # number of demand (read+write) misses (Count)
system.l2.demandMisses::total                 3147457                       # number of demand (read+write) misses (Count)
system.l2.overallMisses::cpu.inst                 778                       # number of overall misses (Count)
system.l2.overallMisses::cpu.data             3146679                       # number of overall misses (Count)
system.l2.overallMisses::total                3147457                       # number of overall misses (Count)
system.l2.demandMissLatency::cpu.inst        58642000                       # number of demand (read+write) miss ticks (Tick)
system.l2.demandMissLatency::cpu.data    238273886000                       # number of demand (read+write) miss ticks (Tick)
system.l2.demandMissLatency::total       238332528000                       # number of demand (read+write) miss ticks (Tick)
system.l2.overallMissLatency::cpu.inst       58642000                       # number of overall miss ticks (Tick)
system.l2.overallMissLatency::cpu.data   238273886000                       # number of overall miss ticks (Tick)
system.l2.overallMissLatency::total      238332528000                       # number of overall miss ticks (Tick)
system.l2.demandAccesses::cpu.inst                807                       # number of demand (read+write) accesses (Count)
system.l2.demandAccesses::cpu.data            3146707                       # number of demand (read+write) accesses (Count)
system.l2.demandAccesses::total               3147514                       # number of demand (read+write) accesses (Count)
system.l2.overallAccesses::cpu.inst               807                       # number of overall (read+write) accesses (Count)
system.l2.overallAccesses::cpu.data           3146707                       # number of overall (read+write) accesses (Count)
system.l2.overallAccesses::total              3147514                       # number of overall (read+write) accesses (Count)
system.l2.demandMissRate::cpu.inst           0.964064                       # miss rate for demand accesses (Ratio)
system.l2.demandMissRate::cpu.data           0.999991                       # miss rate for demand accesses (Ratio)
system.l2.demandMissRate::total              0.999982                       # miss rate for demand accesses (Ratio)
system.l2.overallMissRate::cpu.inst          0.964064                       # miss rate for overall accesses (Ratio)
system.l2.overallMissRate::cpu.data          0.999991                       # miss rate for overall accesses (Ratio)
system.l2.overallMissRate::total             0.999982                       # miss rate for overall accesses (Ratio)
system.l2.demandAvgMissLatency::cpu.inst 75375.321337                       # average overall miss latency in ticks ((Tick/Count))
system.l2.demandAvgMissLatency::cpu.data 75722.336470                       # average overall miss latency in ticks ((Tick/Count))
system.l2.demandAvgMissLatency::total    75722.250693                       # average overall miss latency in ticks ((Tick/Count))
system.l2.overallAvgMissLatency::cpu.inst 75375.321337                       # average overall miss latency ((Tick/Count))
system.l2.overallAvgMissLatency::cpu.data 75722.336470                       # average overall miss latency ((Tick/Count))
system.l2.overallAvgMissLatency::total   75722.250693                       # average overall miss latency ((Tick/Count))
system.l2.blockedCycles::no_mshrs                   0                       # number of cycles access was blocked (Cycle)
system.l2.blockedCycles::no_targets                 0                       # number of cycles access was blocked (Cycle)
system.l2.blockedCauses::no_mshrs                   0                       # number of times access was blocked (Count)
system.l2.blockedCauses::no_targets                 0                       # number of times access was blocked (Count)
system.l2.avgBlocked::no_mshrs                    nan                       # average number of cycles each access was blocked ((Cycle/Count))
system.l2.avgBlocked::no_targets                  nan                       # average number of cycles each access was blocked ((Cycle/Count))
system.l2.writebacks::writebacks              3129931                       # number of writebacks (Count)
system.l2.writebacks::total                   3129931                       # number of writebacks (Count)
system.l2.demandMshrMisses::cpu.inst              778                       # number of demand (read+write) MSHR misses (Count)
system.l2.demandMshrMisses::cpu.data          3146679                       # number of demand (read+write) MSHR misses (Count)
system.l2.demandMshrMisses::total             3147457                       # number of demand (read+write) MSHR misses (Count)
system.l2.overallMshrMisses::cpu.inst             778                       # number of overall MSHR misses (Count)
system.l2.overallMshrMisses::cpu.data         3146679                       # number of overall MSHR misses (Count)
system.l2.overallMshrMisses::total            3147457                       # number of overall MSHR misses (Count)
system.l2.demandMshrMissLatency::cpu.inst     50872000                       # number of demand (read+write) MSHR miss ticks (Tick)
system.l2.demandMshrMissLatency::cpu.data 206807096000                       # number of demand (read+write) MSHR miss ticks (Tick)
system.l2.demandMshrMissLatency::total   206857968000                       # number of demand (read+write) MSHR miss ticks (Tick)
system.l2.overallMshrMissLatency::cpu.inst     50872000                       # number of overall MSHR miss ticks (Tick)
system.l2.overallMshrMissLatency::cpu.data 206807096000                       # number of overall MSHR miss ticks (Tick)
system.l2.overallMshrMissLatency::total  206857968000                       # number of overall MSHR miss ticks (Tick)
system.l2.demandMshrMissRate::cpu.inst       0.964064                       # mshr miss ratio for demand accesses (Ratio)
system.l2.demandMshrMissRate::cpu.data       0.999991                       # mshr miss ratio for demand accesses (Ratio)
system.l2.demandMshrMissRate::total          0.999982                       # mshr miss ratio for demand accesses (Ratio)
system.l2.overallMshrMissRate::cpu.inst      0.964064                       # mshr miss ratio for overall accesses (Ratio)
system.l2.overallMshrMissRate::cpu.data      0.999991                       # mshr miss ratio for overall accesses (Ratio)
system.l2.overallMshrMissRate::total         0.999982                       # mshr miss ratio for overall accesses (Ratio)
system.l2.demandAvgMshrMissLatency::cpu.inst 65388.174807                       # average overall mshr miss latency ((Tick/Count))
system.l2.demandAvgMshrMissLatency::cpu.data 65722.336470                       # average overall mshr miss latency ((Tick/Count))
system.l2.demandAvgMshrMissLatency::total 65722.253870                       # average overall mshr miss latency ((Tick/Count))
system.l2.overallAvgMshrMissLatency::cpu.inst 65388.174807                       # average overall mshr miss latency ((Tick/Count))
system.l2.overallAvgMshrMissLatency::cpu.data 65722.336470                       # average overall mshr miss latency ((Tick/Count))
system.l2.overallAvgMshrMissLatency::total 65722.253870                       # average overall mshr miss latency ((Tick/Count))
system.l2.replacements                        3131210                       # number of replacements (Count)
system.l2.ReadCleanReq.hits::cpu.inst              29                       # number of ReadCleanReq hits (Count)
system.l2.ReadCleanReq.hits::total                 29                       # number of ReadCleanReq hits (Count)
system.l2.ReadCleanReq.misses::cpu.inst           778                       # number of ReadCleanReq misses (Count)
system.l2.ReadCleanReq.misses::total              778                       # number of ReadCleanReq misses (Count)
system.l2.ReadCleanReq.missLatency::cpu.inst     58642000                       # number of ReadCleanReq miss ticks (Tick)
system.l2.ReadCleanReq.missLatency::total     58642000                       # number of ReadCleanReq miss ticks (Tick)
system.l2.ReadCleanReq.accesses::cpu.inst          807                       # number of ReadCleanReq accesses(hits+misses) (Count)
system.l2.ReadCleanReq.accesses::total            807                       # number of ReadCleanReq accesses(hits+misses) (Count)
system.l2.ReadCleanReq.missRate::cpu.inst     0.964064                       # miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.missRate::total       0.964064                       # miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.avgMissLatency::cpu.inst 75375.321337                       # average ReadCleanReq miss latency ((Tick/Count))
system.l2.ReadCleanReq.avgMissLatency::total 75375.321337                       # average ReadCleanReq miss latency ((Tick/Count))
system.l2.ReadCleanReq.mshrMisses::cpu.inst          778                       # number of ReadCleanReq MSHR misses (Count)
system.l2.ReadCleanReq.mshrMisses::total          778                       # number of ReadCleanReq MSHR misses (Count)
system.l2.ReadCleanReq.mshrMissLatency::cpu.inst     50872000                       # number of ReadCleanReq MSHR miss ticks (Tick)
system.l2.ReadCleanReq.mshrMissLatency::total     50872000                       # number of ReadCleanReq MSHR miss ticks (Tick)
system.l2.ReadCleanReq.mshrMissRate::cpu.inst     0.964064                       # mshr miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.mshrMissRate::total     0.964064                       # mshr miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.avgMshrMissLatency::cpu.inst 65388.174807                       # average ReadCleanReq mshr miss latency ((Tick/Count))
system.l2.ReadCleanReq.avgMshrMissLatency::total 65388.174807                       # average ReadCleanReq mshr miss latency ((Tick/Count))
system.l2.ReadExReq.hits::cpu.data                  7                       # number of ReadExReq hits (Count)
system.l2.ReadExReq.hits::total                     7                       # number of ReadExReq hits (Count)
system.l2.ReadExReq.misses::cpu.data          3145890                       # number of ReadExReq misses (Count)
system.l2.ReadExReq.misses::total             3145890                       # number of ReadExReq misses (Count)
system.l2.ReadExReq.missLatency::cpu.data 238217428500                       # number of ReadExReq miss ticks (Tick)
system.l2.ReadExReq.missLatency::total   238217428500                       # number of ReadExReq miss ticks (Tick)
system.l2.ReadExReq.accesses::cpu.data        3145897                       # number of ReadExReq accesses(hits+misses) (Count)
system.l2.ReadExReq.accesses::total           3145897                       # number of ReadExReq accesses(hits+misses) (Count)
system.l2.ReadExReq.missRate::cpu.data       0.999998                       # miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.missRate::total          0.999998                       # miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.avgMissLatency::cpu.data 75723.381460                       # average ReadExReq miss latency ((Tick/Count))
system.l2.ReadExReq.avgMissLatency::total 75723.381460                       # average ReadExReq miss latency ((Tick/Count))
system.l2.ReadExReq.mshrMisses::cpu.data      3145890                       # number of ReadExReq MSHR misses (Count)
system.l2.ReadExReq.mshrMisses::total         3145890                       # number of ReadExReq MSHR misses (Count)
system.l2.ReadExReq.mshrMissLatency::cpu.data 206758528500                       # number of ReadExReq MSHR miss ticks (Tick)
system.l2.ReadExReq.mshrMissLatency::total 206758528500                       # number of ReadExReq MSHR miss ticks (Tick)
system.l2.ReadExReq.mshrMissRate::cpu.data     0.999998                       # mshr miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.mshrMissRate::total      0.999998                       # mshr miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.avgMshrMissLatency::cpu.data 65723.381460                       # average ReadExReq mshr miss latency ((Tick/Count))
system.l2.ReadExReq.avgMshrMissLatency::total 65723.381460                       # average ReadExReq mshr miss latency ((Tick/Count))
system.l2.ReadSharedReq.hits::cpu.data             21                       # number of ReadSharedReq hits (Count)
system.l2.ReadSharedReq.hits::total                21                       # number of ReadSharedReq hits (Count)
system.l2.ReadSharedReq.misses::cpu.data          789                       # number of ReadSharedReq misses (Count)
system.l2.ReadSharedReq.misses::total             789                       # number of ReadSharedReq misses (Count)
system.l2.ReadSharedReq.missLatency::cpu.data     56457500                       # number of ReadSharedReq miss ticks (Tick)
system.l2.ReadSharedReq.missLatency::total     56457500                       # number of ReadSharedReq miss ticks (Tick)
system.l2.ReadSharedReq.accesses::cpu.data          810                       # number of ReadSharedReq accesses(hits+misses) (Count)
system.l2.ReadSharedReq.accesses::total           810                       # number of ReadSharedReq accesses(hits+misses) (Count)
system.l2.ReadSharedReq.missRate::cpu.data     0.974074                       # miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.missRate::total      0.974074                       # miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.avgMissLatency::cpu.data 71555.766793                       # average ReadSharedReq miss latency ((Tick/Count))
system.l2.ReadSharedReq.avgMissLatency::total 71555.766793                       # average ReadSharedReq miss latency ((Tick/Count))
system.l2.ReadSharedReq.mshrMisses::cpu.data          789                       # number of ReadSharedReq MSHR misses (Count)
system.l2.ReadSharedReq.mshrMisses::total          789                       # number of ReadSharedReq MSHR misses (Count)
system.l2.ReadSharedReq.mshrMissLatency::cpu.data     48567500                       # number of ReadSharedReq MSHR miss ticks (Tick)
system.l2.ReadSharedReq.mshrMissLatency::total     48567500                       # number of ReadSharedReq MSHR miss ticks (Tick)
system.l2.ReadSharedReq.mshrMissRate::cpu.data     0.974074                       # mshr miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.mshrMissRate::total     0.974074                       # mshr miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.avgMshrMissLatency::cpu.data 61555.766793                       # average ReadSharedReq mshr miss latency ((Tick/Count))
system.l2.ReadSharedReq.avgMshrMissLatency::total 61555.766793                       # average ReadSharedReq mshr miss latency ((Tick/Count))
system.l2.UpgradeReq.hits::cpu.data                 2                       # number of UpgradeReq hits (Count)
system.l2.UpgradeReq.hits::total                    2                       # number of UpgradeReq hits (Count)
system.l2.UpgradeReq.accesses::cpu.data             2                       # number of UpgradeReq accesses(hits+misses) (Count)
system.l2.UpgradeReq.accesses::total                2                       # number of UpgradeReq accesses(hits+misses) (Count)
system.l2.WritebackClean.hits::writebacks          344                       # number of WritebackClean hits (Count)
system.l2.WritebackClean.hits::total              344                       # number of WritebackClean hits (Count)
system.l2.WritebackClean.accesses::writebacks          344                       # number of WritebackClean accesses(hits+misses) (Count)
system.l2.WritebackClean.accesses::total          344                       # number of WritebackClean accesses(hits+misses) (Count)
system.l2.WritebackDirty.hits::writebacks      3145487                       # number of WritebackDirty hits (Count)
system.l2.WritebackDirty.hits::total          3145487                       # number of WritebackDirty hits (Count)
system.l2.WritebackDirty.accesses::writebacks      3145487                       # number of WritebackDirty accesses(hits+misses) (Count)
system.l2.WritebackDirty.accesses::total      3145487                       # number of WritebackDirty accesses(hits+misses) (Count)
system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.l2.tags.tagsInUse                 16345.270386                       # Average ticks per tags in use ((Tick/Count))
system.l2.tags.totalRefs                      6294054                       # Total number of references to valid blocks. (Count)
system.l2.tags.sampledRefs                    3147594                       # Sample count of references to valid blocks. (Count)
system.l2.tags.avgRefs                       1.999640                       # Average number of references to valid blocks. ((Count/Count))
system.l2.tags.warmupTick                       71500                       # The tick when the warmup percentage was hit. (Tick)
system.l2.tags.occupancies::writebacks       0.014291                       # Average occupied blocks per tick, per requestor ((Count/Tick))
system.l2.tags.occupancies::cpu.inst         2.446019                       # Average occupied blocks per tick, per requestor ((Count/Tick))
system.l2.tags.occupancies::cpu.data     16342.810075                       # Average occupied blocks per tick, per requestor ((Count/Tick))
system.l2.tags.avgOccs::writebacks           0.000001                       # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.avgOccs::cpu.inst             0.000149                       # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.avgOccs::cpu.data             0.997486                       # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.avgOccs::total                0.997636                       # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.occupanciesTaskId::1024          16384                       # Occupied blocks per task id (Count)
system.l2.tags.ageTaskId_1024::0                  247                       # Occupied blocks per task id, per block age (Count)
system.l2.tags.ageTaskId_1024::1                 1243                       # Occupied blocks per task id, per block age (Count)
system.l2.tags.ageTaskId_1024::2                11345                       # Occupied blocks per task id, per block age (Count)
system.l2.tags.ageTaskId_1024::3                 3549                       # Occupied blocks per task id, per block age (Count)
system.l2.tags.ratioOccsTaskId::1024                1                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
system.l2.tags.tagAccesses                   53500034                       # Number of tag accesses (Count)
system.l2.tags.dataAccesses                  53500034                       # Number of data accesses (Count)
system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.mem_ctrls.avgPriority_writebacks::samples   3129931.00                       # Average QoS priority value for accepted requests (Count)
system.mem_ctrls.avgPriority_cpu.inst::samples       778.00                       # Average QoS priority value for accepted requests (Count)
system.mem_ctrls.avgPriority_cpu.data::samples   3146679.00                       # Average QoS priority value for accepted requests (Count)
system.mem_ctrls.priorityMinLatency      0.000000018750                       # per QoS priority minimum request to response latency (Second)
system.mem_ctrls.priorityMaxLatency      0.000580619750                       # per QoS priority maximum request to response latency (Second)
system.mem_ctrls.numReadWriteTurnArounds       195618                       # Number of turnarounds from READ to WRITE (Count)
system.mem_ctrls.numWriteReadTurnArounds       195618                       # Number of turnarounds from WRITE to READ (Count)
system.mem_ctrls.numStayReadState             9288070                       # Number of times bus staying in READ state (Count)
system.mem_ctrls.numStayWriteState            2939475                       # Number of times bus staying in WRITE state (Count)
system.mem_ctrls.readReqs                     3147457                       # Number of read requests accepted (Count)
system.mem_ctrls.writeReqs                    3129931                       # Number of write requests accepted (Count)
system.mem_ctrls.readBursts                   3147457                       # Number of controller read bursts, including those serviced by the write queue (Count)
system.mem_ctrls.writeBursts                  3129931                       # Number of controller write bursts, including those merged in the write queue (Count)
system.mem_ctrls.servicedByWrQ                      0                       # Number of controller read bursts serviced by the write queue (Count)
system.mem_ctrls.mergedWrBursts                     0                       # Number of controller write bursts merged with an existing one (Count)
system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write (Count)
system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing ((Count/Tick))
system.mem_ctrls.avgWrQLen                      26.17                       # Average write queue length when enqueuing ((Count/Tick))
system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry (Count)
system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry (Count)
system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::6               3147457                       # Read request sizes (log2) (Count)
system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::6              3129931                       # Write request sizes (log2) (Count)
system.mem_ctrls.rdQLenPdf::0                 3147011                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::1                     332                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::2                      91                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::3                      19                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::4                       4                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::15                      8                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::16                      9                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::17                 194679                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::18                 195612                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::19                 195618                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::20                 195616                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::21                 195623                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::22                 195622                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::23                 195624                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::24                 195622                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::25                 195622                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::26                 196541                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::27                 195626                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::28                 195621                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::29                 195619                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::30                 195618                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::31                 195618                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::32                 195618                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see (Count)
system.mem_ctrls.rdPerTurnAround::samples       195618                       # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::mean      16.089808                       # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::gmean     16.000492                       # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::stdev     38.394535                       # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::0-1023       195617    100.00%    100.00% # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::total        195618                       # Reads before turning the bus around for writes (Count)
system.mem_ctrls.wrPerTurnAround::samples       195618                       # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::mean      16.000128                       # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::gmean     16.000118                       # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::stdev      0.019051                       # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::16           195609    100.00%    100.00% # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::18                2      0.00%    100.00% # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::19                7      0.00%    100.00% # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::total        195618                       # Writes before turning the bus around for reads (Count)
system.mem_ctrls.bytesReadWrQ                       0                       # Total number of bytes read from write queue (Byte)
system.mem_ctrls.bytesReadSys               201437248                       # Total read bytes from the system interface side (Byte)
system.mem_ctrls.bytesWrittenSys            200315584                       # Total written bytes from the system interface side (Byte)
system.mem_ctrls.avgRdBWSys              806742792.63047206                       # Average system read bandwidth in Byte/s ((Byte/Second))
system.mem_ctrls.avgWrBWSys              802250602.84562624                       # Average system write bandwidth in Byte/s ((Byte/Second))
system.mem_ctrls.totGap                  249691966500                       # Total gap between requests (Tick)
system.mem_ctrls.avgGap                      39776.41                       # Average gap between requests ((Tick/Count))
system.mem_ctrls.requestorReadBytes::cpu.inst        49792                       # Per-requestor bytes read from memory (Byte)
system.mem_ctrls.requestorReadBytes::cpu.data    201387456                       # Per-requestor bytes read from memory (Byte)
system.mem_ctrls.requestorWriteBytes::writebacks    200314432                       # Per-requestor bytes write to memory (Byte)
system.mem_ctrls.requestorReadRate::cpu.inst 199413.651295794436                       # Per-requestor bytes read from memory rate ((Byte/Second))
system.mem_ctrls.requestorReadRate::cpu.data 806543378.979176282883                       # Per-requestor bytes read from memory rate ((Byte/Second))
system.mem_ctrls.requestorWriteRate::writebacks 802245989.162177205086                       # Per-requestor bytes write to memory rate ((Byte/Second))
system.mem_ctrls.requestorReadAccesses::cpu.inst          778                       # Per-requestor read serviced memory accesses (Count)
system.mem_ctrls.requestorReadAccesses::cpu.data      3146679                       # Per-requestor read serviced memory accesses (Count)
system.mem_ctrls.requestorWriteAccesses::writebacks      3129931                       # Per-requestor write serviced memory accesses (Count)
system.mem_ctrls.requestorReadTotalLat::cpu.inst     23230750                       # Per-requestor read total memory access latency (Tick)
system.mem_ctrls.requestorReadTotalLat::cpu.data  94343945000                       # Per-requestor read total memory access latency (Tick)
system.mem_ctrls.requestorWriteTotalLat::writebacks 6125476560750                       # Per-requestor write total memory access latency (Tick)
system.mem_ctrls.requestorReadAvgLat::cpu.inst     29859.58                       # Per-requestor read average memory access latency ((Tick/Count))
system.mem_ctrls.requestorReadAvgLat::cpu.data     29982.07                       # Per-requestor read average memory access latency ((Tick/Count))
system.mem_ctrls.requestorWriteAvgLat::writebacks   1957064.41                       # Per-requestor write average memory access latency ((Tick/Count))
system.mem_ctrls.dram.bytesRead::cpu.inst        49728                       # Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesRead::cpu.data    201387456                       # Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesRead::total      201437184                       # Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesInstRead::cpu.inst        49728                       # Number of instructions bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesInstRead::total        49728                       # Number of instructions bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesWritten::writebacks    200315584                       # Number of bytes written to this memory (Byte)
system.mem_ctrls.dram.bytesWritten::total    200315584                       # Number of bytes written to this memory (Byte)
system.mem_ctrls.dram.numReads::cpu.inst          777                       # Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numReads::cpu.data      3146679                       # Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numReads::total         3147456                       # Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numWrites::writebacks      3129931                       # Number of write requests responded to by this memory (Count)
system.mem_ctrls.dram.numWrites::total        3129931                       # Number of write requests responded to by this memory (Count)
system.mem_ctrls.dram.bwRead::cpu.inst         199157                       # Total read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwRead::cpu.data      806543379                       # Total read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwRead::total         806742536                       # Total read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwInstRead::cpu.inst       199157                       # Instruction read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwInstRead::total        199157                       # Instruction read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwWrite::writebacks    802250603                       # Write bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwWrite::total        802250603                       # Write bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::writebacks    802250603                       # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::cpu.inst        199157                       # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::cpu.data     806543379                       # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::total       1608993139                       # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.readBursts              3147457                       # Number of DRAM read bursts (Count)
system.mem_ctrls.dram.writeBursts             3129913                       # Number of DRAM write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::0       196843                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::1       196819                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::2       196711                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::3       196671                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::4       196762                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::5       196771                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::6       196634                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::7       196608                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::8       196667                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::9       196684                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::10       196666                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::11       196654                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::12       196646                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::13       196746                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::14       196826                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::15       196749                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::0       195641                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::1       195604                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::2       195627                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::3       195618                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::4       195641                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::5       195679                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::6       195592                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::7       195584                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::8       195628                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::9       195629                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::10       195629                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::11       195624                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::12       195610                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::13       195600                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::14       195620                       # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::15       195587                       # Per bank write bursts (Count)
system.mem_ctrls.dram.totQLat             35352357000                       # Total ticks spent queuing (Tick)
system.mem_ctrls.dram.totBusLat           15737285000                       # Total ticks spent in databus transfers (Tick)
system.mem_ctrls.dram.totMemAccLat        94367175750                       # Total ticks spent from burst creation until serviced by the DRAM (Tick)
system.mem_ctrls.dram.avgQLat                11232.04                       # Average queueing delay per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.avgBusLat               5000.00                       # Average bus latency per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.avgMemAccLat           29982.04                       # Average memory access latency per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.readRowHits             2897704                       # Number of row buffer hits during reads (Count)
system.mem_ctrls.dram.writeRowHits            2907869                       # Number of row buffer hits during writes (Count)
system.mem_ctrls.dram.readRowHitRate            92.06                       # Row buffer hit rate for reads (Ratio)
system.mem_ctrls.dram.writeRowHitRate           92.91                       # Row buffer hit rate for writes (Ratio)
system.mem_ctrls.dram.bytesPerActivate::samples       471785                       # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::mean   851.551550                       # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::gmean   718.640539                       # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::stdev   311.603128                       # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::0-127        24292      5.15%      5.15% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::128-255        23165      4.91%     10.06% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::256-383        16875      3.58%     13.64% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::384-511        14063      2.98%     16.62% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::512-639         8277      1.75%     18.37% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::640-767        22977      4.87%     23.24% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::768-895         5951      1.26%     24.50% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::896-1023        37657      7.98%     32.48% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::1024-1151       318528     67.52%    100.00% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::total       471785                       # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesRead             201437248                       # Total bytes read (Byte)
system.mem_ctrls.dram.bytesWritten          200314432                       # Total bytes written (Byte)
system.mem_ctrls.dram.avgRdBW              806.742793                       # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
system.mem_ctrls.dram.avgWrBW              802.245989                       # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
system.mem_ctrls.dram.peakBW                 12800.00                       # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
system.mem_ctrls.dram.busUtil                   12.57                       # Data bus utilization in percentage (Ratio)
system.mem_ctrls.dram.busUtilRead                6.30                       # Data bus utilization in percentage for reads (Ratio)
system.mem_ctrls.dram.busUtilWrite               6.27                       # Data bus utilization in percentage for writes (Ratio)
system.mem_ctrls.dram.pageHitRate               92.48                       # Row buffer hit rate, read and write combined (Ratio)
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.mem_ctrls.dram.rank0.actEnergy      1685418420                       # Energy for activate commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.preEnergy       895798365                       # Energy for precharge commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.readEnergy    11237060520                       # Energy for read commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.writeEnergy    8169206040                       # Energy for write commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.refreshEnergy 19710275520.000004                       # Energy for refresh commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.actBackEnergy  60061519020                       # Energy for active background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.preBackEnergy  45303619680                       # Energy for precharge background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.totalEnergy  147062897565                       # Total energy per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.averagePower   588.977132                       # Core power per rank (mW) (Watt)
system.mem_ctrls.dram.rank0.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE 115732190750                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::REF   8337680000                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::SREF            0                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::ACT 125622162250                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.actEnergy      1683212160                       # Energy for activate commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.preEnergy       894625710                       # Energy for precharge commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.readEnergy    11235775320                       # Energy for read commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.writeEnergy    8168918940                       # Energy for write commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.refreshEnergy 19710275520.000004                       # Energy for refresh commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.actBackEnergy  60489683640                       # Energy for active background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.preBackEnergy  44943060000                       # Energy for precharge background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.totalEnergy  147125551290                       # Total energy per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.averagePower   589.228056                       # Core power per rank (mW) (Watt)
system.mem_ctrls.dram.rank1.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE 114821841250                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::REF   8337680000                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::SREF            0                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::ACT 126532511750                       # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.membus.transDist::ReadResp                1566                       # Transaction distribution (Count)
system.membus.transDist::WritebackDirty       3129931                       # Transaction distribution (Count)
system.membus.transDist::CleanEvict               868                       # Transaction distribution (Count)
system.membus.transDist::ReadExReq            3145890                       # Transaction distribution (Count)
system.membus.transDist::ReadExResp           3145890                       # Transaction distribution (Count)
system.membus.transDist::ReadSharedReq           1567                       # Transaction distribution (Count)
system.membus.pktCount_system.l2.mem_side_port::system.mem_ctrls.port      9425712                       # Packet count per connected requestor and responder (Count)
system.membus.pktCount_system.l2.mem_side_port::total      9425712                       # Packet count per connected requestor and responder (Count)
system.membus.pktCount::total                 9425712                       # Packet count per connected requestor and responder (Count)
system.membus.pktSize_system.l2.mem_side_port::system.mem_ctrls.port    401752768                       # Cumulative packet size per connected requestor and responder (Byte)
system.membus.pktSize_system.l2.mem_side_port::total    401752768                       # Cumulative packet size per connected requestor and responder (Byte)
system.membus.pktSize::total                401752768                       # Cumulative packet size per connected requestor and responder (Byte)
system.membus.snoops                                0                       # Total snoops (Count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (Byte)
system.membus.snoopFanout::samples            3147457                       # Request fanout histogram (Count)
system.membus.snoopFanout::mean                     0                       # Request fanout histogram (Count)
system.membus.snoopFanout::stdev                    0                       # Request fanout histogram (Count)
system.membus.snoopFanout::underflows               0      0.00%      0.00% # Request fanout histogram (Count)
system.membus.snoopFanout::0                  3147457    100.00%    100.00% # Request fanout histogram (Count)
system.membus.snoopFanout::1                        0      0.00%    100.00% # Request fanout histogram (Count)
system.membus.snoopFanout::overflows                0      0.00%    100.00% # Request fanout histogram (Count)
system.membus.snoopFanout::min_value                0                       # Request fanout histogram (Count)
system.membus.snoopFanout::max_value                0                       # Request fanout histogram (Count)
system.membus.snoopFanout::total              3147457                       # Request fanout histogram (Count)
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.membus.reqLayer2.occupancy          9398990000                       # Layer occupancy (ticks) (Tick)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (Ratio)
system.membus.respLayer1.occupancy         8624849750                       # Layer occupancy (ticks) (Tick)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (Ratio)
system.membus.snoop_filter.totRequests        6278256                       # Total number of requests made to the snoop filter. (Count)
system.membus.snoop_filter.hitSingleRequests      3130799                       # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
system.membus.snoop_filter.hitMultiRequests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.membus.snoop_filter.totSnoops                0                       # Total number of snoops made to the snoop filter. (Count)
system.membus.snoop_filter.hitSingleSnoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
system.membus.snoop_filter.hitMultiSnoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.tol2bus.transDist::ReadResp               1618                       # Transaction distribution (Count)
system.tol2bus.transDist::WritebackDirty      6275418                       # Transaction distribution (Count)
system.tol2bus.transDist::WritebackClean          344                       # Transaction distribution (Count)
system.tol2bus.transDist::CleanEvict             1987                       # Transaction distribution (Count)
system.tol2bus.transDist::UpgradeReq                2                       # Transaction distribution (Count)
system.tol2bus.transDist::UpgradeResp               2                       # Transaction distribution (Count)
system.tol2bus.transDist::ReadExReq           3145897                       # Transaction distribution (Count)
system.tol2bus.transDist::ReadExResp          3145897                       # Transaction distribution (Count)
system.tol2bus.transDist::ReadCleanReq            809                       # Transaction distribution (Count)
system.tol2bus.transDist::ReadSharedReq           810                       # Transaction distribution (Count)
system.tol2bus.pktCount_system.cpu.icache.mem_side_port::system.l2.cpu_side_port         1959                       # Packet count per connected requestor and responder (Count)
system.tol2bus.pktCount_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port      9439613                       # Packet count per connected requestor and responder (Count)
system.tol2bus.pktCount::total                9441572                       # Packet count per connected requestor and responder (Count)
system.tol2bus.pktSize_system.cpu.icache.mem_side_port::system.l2.cpu_side_port        73600                       # Cumulative packet size per connected requestor and responder (Byte)
system.tol2bus.pktSize_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port    402700416                       # Cumulative packet size per connected requestor and responder (Byte)
system.tol2bus.pktSize::total               402774016                       # Cumulative packet size per connected requestor and responder (Byte)
system.tol2bus.snoops                         3131212                       # Total snoops (Count)
system.tol2bus.snoopTraffic                 200315712                       # Total snoop traffic (Byte)
system.tol2bus.snoopFanout::samples           6278728                       # Request fanout histogram (Count)
system.tol2bus.snoopFanout::mean             0.000067                       # Request fanout histogram (Count)
system.tol2bus.snoopFanout::stdev            0.008159                       # Request fanout histogram (Count)
system.tol2bus.snoopFanout::underflows              0      0.00%      0.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::0                 6278310     99.99%     99.99% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::1                     418      0.01%    100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::2                       0      0.00%    100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::3                       0      0.00%    100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::4                       0      0.00%    100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::overflows               0      0.00%    100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::min_value               0                       # Request fanout histogram (Count)
system.tol2bus.snoopFanout::max_value               1                       # Request fanout histogram (Count)
system.tol2bus.snoopFanout::total             6278728                       # Request fanout histogram (Count)
system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 249692033000                       # Cumulative time (in ticks) in various power states (Tick)
system.tol2bus.reqLayer0.occupancy         6292859500                       # Layer occupancy (ticks) (Tick)
system.tol2bus.reqLayer0.utilization              0.0                       # Layer utilization (Ratio)
system.tol2bus.respLayer0.occupancy           1212000                       # Layer occupancy (ticks) (Tick)
system.tol2bus.respLayer0.utilization             0.0                       # Layer utilization (Ratio)
system.tol2bus.respLayer1.occupancy        4720061500                       # Layer occupancy (ticks) (Tick)
system.tol2bus.respLayer1.utilization             0.0                       # Layer utilization (Ratio)
system.tol2bus.snoop_filter.totRequests       6294057                       # Total number of requests made to the snoop filter. (Count)
system.tol2bus.snoop_filter.hitSingleRequests      3146539                       # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
system.tol2bus.snoop_filter.hitMultiRequests            5                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.tol2bus.snoop_filter.totSnoops             413                       # Total number of snoops made to the snoop filter. (Count)
system.tol2bus.snoop_filter.hitSingleSnoops          413                       # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
system.tol2bus.snoop_filter.hitMultiSnoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.voltage_domain.voltage                       1                       # Voltage in Volts (Volt)
system.workload.inst.arm                            0                       # number of arm instructions executed (Count)
system.workload.inst.quiesce                        0                       # number of quiesce instructions executed (Count)

---------- End Simulation Statistics   ----------