CarGDev/gem5-ilp-experiments
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
master
gem5-ilp-experiments/branchPrediction/LocalBP/stats.txt
Carlos Gutierrez cd69096346 initial commit
2025-09-21 01:17:26 -04:00

1403 lines
178 KiB
Plaintext
Raw Permalink Blame History

---------- Begin Simulation Statistics ----------
simSeconds 0.265340 # Number of seconds simulated (Second)
simTicks 265339781000 # Number of ticks simulated (Tick)
finalTick 265339781000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 351.88 # Real time elapsed on the host (Second)
hostTickRate 754067403 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 677372 # Number of bytes of host memory used (Byte)
simInsts 25297289 # Number of instructions simulated (Count)
simOps 34841936 # Number of ops (including micro ops) simulated (Count)
hostInstRate 71892 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 99017 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
system.clk_domain.clock 1000 # Clock period in ticks (Tick)
system.cpu.numCycles 530679563 # Number of cpu cycles simulated (Cycle)
system.cpu.cpi 20.977725 # CPI: cycles per instruction (core level) ((Cycle/Count))
system.cpu.ipc 0.047670 # IPC: instructions per cycle (core level) ((Count/Cycle))
system.cpu.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
system.cpu.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
system.cpu.instsAdded 37751584 # Number of instructions added to the IQ (excludes non-spec) (Count)
system.cpu.nonSpecInstsAdded 248 # Number of non-speculative instructions added to the IQ (Count)
system.cpu.instsIssued 37743684 # Number of instructions issued (Count)
system.cpu.squashedInstsIssued 124 # Number of squashed instructions issued (Count)
system.cpu.squashedInstsExamined 2909890 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
system.cpu.squashedOperandsExamined 1093638 # Number of squashed operands that are examined and possibly removed from graph (Count)
system.cpu.squashedNonSpecRemoved 158 # Number of squashed non-spec instructions that were removed (Count)
system.cpu.numIssuedDist::samples 530616716 # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::mean 0.071132 # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::stdev 0.470540 # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::0 516230286 97.29% 97.29% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::1 3993217 0.75% 98.04% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::2 1288068 0.24% 98.28% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::3 5875023 1.11% 99.39% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::4 2860262 0.54% 99.93% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::5 236344 0.04% 99.97% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::6 26754 0.01% 99.98% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::7 88126 0.02% 100.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::8 18636 0.00% 100.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::total 530616716 # Number of insts issued each cycle (Count)
system.cpu.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IntAlu 24713 99.44% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IntMult 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IntDiv 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatAdd 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatCmp 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatCvt 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMult 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMultAcc 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatDiv 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMisc 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatSqrt 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAdd 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAddAcc 0 0.00% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAlu 24 0.10% 99.53% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdCmp 0 0.00% 99.53% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdCvt 1 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMisc 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMult 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMultAcc 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMatMultAcc 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShift 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShiftAcc 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdDiv 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSqrt 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatAdd 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatAlu 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatCmp 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatCvt 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatDiv 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMisc 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMult 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMultAcc 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMatMultAcc 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatSqrt 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdReduceAdd 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdReduceAlu 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdReduceCmp 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatReduceAdd 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatReduceCmp 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAes 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAesMix 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha1Hash 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha1Hash2 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha256Hash 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha256Hash2 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShaSigma2 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShaSigma3 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdPredAlu 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::Matrix 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MatrixMov 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MatrixOP 0 0.00% 99.54% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MemRead 64 0.26% 99.79% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MemWrite 39 0.16% 99.95% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMemRead 1 0.00% 99.96% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMemWrite 11 0.04% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIntegerArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorFloatArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorFloatConvert 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIntegerReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorFloatReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorMisc 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIntegerExtension 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statIssuedInstType_0::No_OpClass 670 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IntAlu 27484803 72.82% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IntMult 56 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IntDiv 91 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatAdd 182 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatCmp 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatCvt 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMult 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMultAcc 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatDiv 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMisc 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatSqrt 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAdd 10 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAddAcc 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAlu 267 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdCmp 4 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdCvt 92 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMisc 277 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMult 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMultAcc 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShift 7 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShiftAcc 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdDiv 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSqrt 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatAdd 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatAlu 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatCmp 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatCvt 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatDiv 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMisc 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMult 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdReduceAdd 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdReduceAlu 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdReduceCmp 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAes 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAesMix 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha1Hash 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha256Hash 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShaSigma2 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShaSigma3 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdPredAlu 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::Matrix 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MatrixMov 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MatrixOP 0 0.00% 72.82% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MemRead 3429375 9.09% 81.91% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MemWrite 6827064 18.09% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMemRead 183 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMemWrite 603 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::total 37743684 # Number of instructions issued per FU type, per thread (Count)
system.cpu.issueRate 0.071123 # Inst issue rate ((Count/Cycle))
system.cpu.fuBusy 24853 # FU busy when requested (Count)
system.cpu.fuBusyRate 0.000658 # FU busy rate (busy events/executed inst) ((Count/Count))
system.cpu.intInstQueueReads 606125398 # Number of integer instruction queue reads (Count)
system.cpu.intInstQueueWrites 40659682 # Number of integer instruction queue writes (Count)
system.cpu.intInstQueueWakeupAccesses 37477792 # Number of integer instruction queue wakeup accesses (Count)
system.cpu.fpInstQueueReads 3663 # Number of floating instruction queue reads (Count)
system.cpu.fpInstQueueWrites 2097 # Number of floating instruction queue writes (Count)
system.cpu.fpInstQueueWakeupAccesses 1774 # Number of floating instruction queue wakeup accesses (Count)
system.cpu.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
system.cpu.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
system.cpu.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
system.cpu.intAluAccesses 37766017 # Number of integer alu accesses (Count)
system.cpu.fpAluAccesses 1850 # Number of floating point alu accesses (Count)
system.cpu.vecAluAccesses 0 # Number of vector alu accesses (Count)
system.cpu.numSquashedInsts 1188 # Number of squashed instructions skipped in execute (Count)
system.cpu.numSwp 0 # Number of swp insts executed (Count)
system.cpu.timesIdled 514 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
system.cpu.idleCycles 62847 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
system.cpu.MemDepUnit__0.insertedLoads 3430388 # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__0.insertedStores 6828306 # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__0.conflictingLoads 2200479 # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__0.conflictingStores 230282 # Number of conflicting stores. (Count)
system.cpu.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
system.cpu.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
system.cpu.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
system.cpu.branchPred.lookups 3527917 # Number of BP lookups (Count)
system.cpu.branchPred.condPredicted 3516114 # Number of conditional branches predicted (Count)
system.cpu.branchPred.condIncorrect 1019 # Number of conditional branches incorrect (Count)
system.cpu.branchPred.BTBLookups 3501044 # Number of BTB lookups (Count)
system.cpu.branchPred.BTBUpdates 883 # Number of BTB updates (Count)
system.cpu.branchPred.BTBHits 3500284 # Number of BTB hits (Count)
system.cpu.branchPred.BTBHitRatio 0.999783 # BTB Hit Ratio (Ratio)
system.cpu.branchPred.RASUsed 2741 # Number of times the RAS was used to get a target. (Count)
system.cpu.branchPred.RASIncorrect 9 # Number of incorrect RAS predictions. (Count)
system.cpu.branchPred.indirectLookups 2505 # Number of indirect predictor lookups. (Count)
system.cpu.branchPred.indirectHits 2197 # Number of indirect target hits. (Count)
system.cpu.branchPred.indirectMisses 308 # Number of indirect misses. (Count)
system.cpu.branchPred.indirectMispredicted 88 # Number of mispredicted indirect branches. (Count)
system.cpu.commit.commitSquashedInsts 2778417 # The number of squashed insts skipped by commit (Count)
system.cpu.commit.commitNonSpecStalls 90 # The number of times commit has been forced to stall to communicate backwards (Count)
system.cpu.commit.branchMispredicts 697 # The number of times a branch was mispredicted (Count)
system.cpu.commit.numCommittedDist::samples 530268889 # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::mean 0.065706 # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::stdev 0.454865 # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::0 517161917 97.53% 97.53% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::1 3860752 0.73% 98.26% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::2 397787 0.08% 98.33% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::3 5791239 1.09% 99.42% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::4 2541686 0.48% 99.90% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::5 492271 0.09% 100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::6 385 0.00% 100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::7 1332 0.00% 100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::8 21520 0.00% 100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::total 530268889 # Number of insts commited each cycle (Count)
system.cpu.commit.amos 0 # Number of atomic instructions committed (Count)
system.cpu.commit.membars 60 # Number of memory barriers committed (Count)
system.cpu.commit.functionCalls 2380 # Number of function calls committed. (Count)
system.cpu.commit.committedInstType_0::No_OpClass 327 0.00% 0.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntAlu 25373027 72.82% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntMult 50 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntDiv 63 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatAdd 154 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatCmp 0 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatCvt 0 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMult 0 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMultAcc 0 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatDiv 0 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMisc 0 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatSqrt 0 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAdd 10 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAddAcc 0 0.00% 72.82% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAlu 247 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdCmp 4 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdCvt 84 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMisc 256 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMult 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMultAcc 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShift 3 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShiftAcc 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdDiv 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSqrt 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatAdd 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatAlu 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatCmp 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatCvt 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatDiv 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMisc 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMult 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdReduceAdd 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdReduceAlu 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdReduceCmp 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAes 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAesMix 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha1Hash 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha256Hash 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShaSigma2 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShaSigma3 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdPredAlu 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::Matrix 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MatrixMov 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MatrixOP 0 0.00% 72.83% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MemRead 3165230 9.08% 81.91% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MemWrite 6301804 18.09% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMemRead 135 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMemWrite 542 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::total 34841936 # Class of committed instruction (Count)
system.cpu.commit.commitEligibleSamples 21520 # number cycles where commit BW limit reached (Cycle)
system.cpu.commitStats0.numInsts 25297289 # Number of instructions committed (thread level) (Count)
system.cpu.commitStats0.numOps 34841936 # Number of ops (including micro ops) committed (thread level) (Count)
system.cpu.commitStats0.numInstsNotNOP 25297289 # Number of instructions committed excluding NOPs or prefetches (Count)
system.cpu.commitStats0.numOpsNotNOP 34841936 # Number of Ops (including micro ops) Simulated (Count)
system.cpu.commitStats0.cpi 20.977725 # CPI: cycles per instruction (thread level) ((Cycle/Count))
system.cpu.commitStats0.ipc 0.047670 # IPC: instructions per cycle (thread level) ((Count/Cycle))
system.cpu.commitStats0.numMemRefs 9467711 # Number of memory references committed (Count)
system.cpu.commitStats0.numFpInsts 1611 # Number of float instructions (Count)
system.cpu.commitStats0.numIntInsts 34840630 # Number of integer instructions (Count)
system.cpu.commitStats0.numLoadInsts 3165365 # Number of load instructions (Count)
system.cpu.commitStats0.numStoreInsts 6302346 # Number of store instructions (Count)
system.cpu.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
system.cpu.commitStats0.committedInstType::No_OpClass 327 0.00% 0.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IntAlu 25373027 72.82% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IntMult 50 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IntDiv 63 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatAdd 154 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatCmp 0 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatCvt 0 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMult 0 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMultAcc 0 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatDiv 0 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMisc 0 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatSqrt 0 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAdd 10 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAddAcc 0 0.00% 72.82% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAlu 247 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdCmp 4 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdCvt 84 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMisc 256 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMult 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMultAcc 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShift 3 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdDiv 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSqrt 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMult 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAes 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::Matrix 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MatrixMov 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MatrixOP 0 0.00% 72.83% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MemRead 3165230 9.08% 81.91% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MemWrite 6301804 18.09% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMemRead 135 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMemWrite 542 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::total 34841936 # Class of committed instruction. (Count)
system.cpu.commitStats0.committedControl::IsControl 3179115 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsDirectControl 3174553 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsIndirectControl 4562 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsCondControl 3168897 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsUncondControl 10218 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsCall 2380 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsReturn 2375 # Class of control type instructions committed (Count)
system.cpu.dcache.demandHits::cpu.data 3171469 # number of demand (read+write) hits (Count)
system.cpu.dcache.demandHits::total 3171469 # number of demand (read+write) hits (Count)
system.cpu.dcache.overallHits::cpu.data 3171469 # number of overall hits (Count)
system.cpu.dcache.overallHits::total 3171469 # number of overall hits (Count)
system.cpu.dcache.demandMisses::cpu.data 3147777 # number of demand (read+write) misses (Count)
system.cpu.dcache.demandMisses::total 3147777 # number of demand (read+write) misses (Count)
system.cpu.dcache.overallMisses::cpu.data 3147777 # number of overall misses (Count)
system.cpu.dcache.overallMisses::total 3147777 # number of overall misses (Count)
system.cpu.dcache.demandMissLatency::cpu.data 261869657499 # number of demand (read+write) miss ticks (Tick)
system.cpu.dcache.demandMissLatency::total 261869657499 # number of demand (read+write) miss ticks (Tick)
system.cpu.dcache.overallMissLatency::cpu.data 261869657499 # number of overall miss ticks (Tick)
system.cpu.dcache.overallMissLatency::total 261869657499 # number of overall miss ticks (Tick)
system.cpu.dcache.demandAccesses::cpu.data 6319246 # number of demand (read+write) accesses (Count)
system.cpu.dcache.demandAccesses::total 6319246 # number of demand (read+write) accesses (Count)
system.cpu.dcache.overallAccesses::cpu.data 6319246 # number of overall (read+write) accesses (Count)
system.cpu.dcache.overallAccesses::total 6319246 # number of overall (read+write) accesses (Count)
system.cpu.dcache.demandMissRate::cpu.data 0.498125 # miss rate for demand accesses (Ratio)
system.cpu.dcache.demandMissRate::total 0.498125 # miss rate for demand accesses (Ratio)
system.cpu.dcache.overallMissRate::cpu.data 0.498125 # miss rate for overall accesses (Ratio)
system.cpu.dcache.overallMissRate::total 0.498125 # miss rate for overall accesses (Ratio)
system.cpu.dcache.demandAvgMissLatency::cpu.data 83191.934339 # average overall miss latency in ticks ((Tick/Count))
system.cpu.dcache.demandAvgMissLatency::total 83191.934339 # average overall miss latency in ticks ((Tick/Count))
system.cpu.dcache.overallAvgMissLatency::cpu.data 83191.934339 # average overall miss latency ((Tick/Count))
system.cpu.dcache.overallAvgMissLatency::total 83191.934339 # average overall miss latency ((Tick/Count))
system.cpu.dcache.blockedCycles::no_mshrs 1001 # number of cycles access was blocked (Cycle)
system.cpu.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
system.cpu.dcache.blockedCauses::no_mshrs 17 # number of times access was blocked (Count)
system.cpu.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
system.cpu.dcache.avgBlocked::no_mshrs 58.882353 # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dcache.writebacks::writebacks 3144953 # number of writebacks (Count)
system.cpu.dcache.writebacks::total 3144953 # number of writebacks (Count)
system.cpu.dcache.demandMshrHits::cpu.data 1096 # number of demand (read+write) MSHR hits (Count)
system.cpu.dcache.demandMshrHits::total 1096 # number of demand (read+write) MSHR hits (Count)
system.cpu.dcache.overallMshrHits::cpu.data 1096 # number of overall MSHR hits (Count)
system.cpu.dcache.overallMshrHits::total 1096 # number of overall MSHR hits (Count)
system.cpu.dcache.demandMshrMisses::cpu.data 3146681 # number of demand (read+write) MSHR misses (Count)
system.cpu.dcache.demandMshrMisses::total 3146681 # number of demand (read+write) MSHR misses (Count)
system.cpu.dcache.overallMshrMisses::cpu.data 3146681 # number of overall MSHR misses (Count)
system.cpu.dcache.overallMshrMisses::total 3146681 # number of overall MSHR misses (Count)
system.cpu.dcache.demandMshrMissLatency::cpu.data 258640553999 # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.dcache.demandMshrMissLatency::total 258640553999 # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.dcache.overallMshrMissLatency::cpu.data 258640553999 # number of overall MSHR miss ticks (Tick)
system.cpu.dcache.overallMshrMissLatency::total 258640553999 # number of overall MSHR miss ticks (Tick)
system.cpu.dcache.demandMshrMissRate::cpu.data 0.497952 # mshr miss ratio for demand accesses (Ratio)
system.cpu.dcache.demandMshrMissRate::total 0.497952 # mshr miss ratio for demand accesses (Ratio)
system.cpu.dcache.overallMshrMissRate::cpu.data 0.497952 # mshr miss ratio for overall accesses (Ratio)
system.cpu.dcache.overallMshrMissRate::total 0.497952 # mshr miss ratio for overall accesses (Ratio)
system.cpu.dcache.demandAvgMshrMissLatency::cpu.data 82194.716909 # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.demandAvgMshrMissLatency::total 82194.716909 # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.overallAvgMshrMissLatency::cpu.data 82194.716909 # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.overallAvgMshrMissLatency::total 82194.716909 # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.replacements 3145659 # number of replacements (Count)
system.cpu.dcache.LockedRMWReadReq.hits::cpu.data 26 # number of LockedRMWReadReq hits (Count)
system.cpu.dcache.LockedRMWReadReq.hits::total 26 # number of LockedRMWReadReq hits (Count)
system.cpu.dcache.LockedRMWReadReq.misses::cpu.data 4 # number of LockedRMWReadReq misses (Count)
system.cpu.dcache.LockedRMWReadReq.misses::total 4 # number of LockedRMWReadReq misses (Count)
system.cpu.dcache.LockedRMWReadReq.missLatency::cpu.data 385000 # number of LockedRMWReadReq miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.missLatency::total 385000 # number of LockedRMWReadReq miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.accesses::cpu.data 30 # number of LockedRMWReadReq accesses(hits+misses) (Count)
system.cpu.dcache.LockedRMWReadReq.accesses::total 30 # number of LockedRMWReadReq accesses(hits+misses) (Count)
system.cpu.dcache.LockedRMWReadReq.missRate::cpu.data 0.133333 # miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.missRate::total 0.133333 # miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::cpu.data 96250 # average LockedRMWReadReq miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::total 96250 # average LockedRMWReadReq miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWReadReq.mshrMisses::cpu.data 4 # number of LockedRMWReadReq MSHR misses (Count)
system.cpu.dcache.LockedRMWReadReq.mshrMisses::total 4 # number of LockedRMWReadReq MSHR misses (Count)
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::cpu.data 880000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::total 880000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::cpu.data 0.133333 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::total 0.133333 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu.data 220000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::total 220000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWWriteReq.hits::cpu.data 30 # number of LockedRMWWriteReq hits (Count)
system.cpu.dcache.LockedRMWWriteReq.hits::total 30 # number of LockedRMWWriteReq hits (Count)
system.cpu.dcache.LockedRMWWriteReq.accesses::cpu.data 30 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
system.cpu.dcache.LockedRMWWriteReq.accesses::total 30 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.hits::cpu.data 15043 # number of ReadReq hits (Count)
system.cpu.dcache.ReadReq.hits::total 15043 # number of ReadReq hits (Count)
system.cpu.dcache.ReadReq.misses::cpu.data 1887 # number of ReadReq misses (Count)
system.cpu.dcache.ReadReq.misses::total 1887 # number of ReadReq misses (Count)
system.cpu.dcache.ReadReq.missLatency::cpu.data 145748000 # number of ReadReq miss ticks (Tick)
system.cpu.dcache.ReadReq.missLatency::total 145748000 # number of ReadReq miss ticks (Tick)
system.cpu.dcache.ReadReq.accesses::cpu.data 16930 # number of ReadReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.accesses::total 16930 # number of ReadReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.missRate::cpu.data 0.111459 # miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.missRate::total 0.111459 # miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.avgMissLatency::cpu.data 77237.943826 # average ReadReq miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.avgMissLatency::total 77237.943826 # average ReadReq miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.mshrHits::cpu.data 1096 # number of ReadReq MSHR hits (Count)
system.cpu.dcache.ReadReq.mshrHits::total 1096 # number of ReadReq MSHR hits (Count)
system.cpu.dcache.ReadReq.mshrMisses::cpu.data 791 # number of ReadReq MSHR misses (Count)
system.cpu.dcache.ReadReq.mshrMisses::total 791 # number of ReadReq MSHR misses (Count)
system.cpu.dcache.ReadReq.mshrMissLatency::cpu.data 62534500 # number of ReadReq MSHR miss ticks (Tick)
system.cpu.dcache.ReadReq.mshrMissLatency::total 62534500 # number of ReadReq MSHR miss ticks (Tick)
system.cpu.dcache.ReadReq.mshrMissRate::cpu.data 0.046722 # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.mshrMissRate::total 0.046722 # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.avgMshrMissLatency::cpu.data 79057.522124 # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.avgMshrMissLatency::total 79057.522124 # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.hits::cpu.data 3156426 # number of WriteReq hits (Count)
system.cpu.dcache.WriteReq.hits::total 3156426 # number of WriteReq hits (Count)
system.cpu.dcache.WriteReq.misses::cpu.data 3145890 # number of WriteReq misses (Count)
system.cpu.dcache.WriteReq.misses::total 3145890 # number of WriteReq misses (Count)
system.cpu.dcache.WriteReq.missLatency::cpu.data 261723909499 # number of WriteReq miss ticks (Tick)
system.cpu.dcache.WriteReq.missLatency::total 261723909499 # number of WriteReq miss ticks (Tick)
system.cpu.dcache.WriteReq.accesses::cpu.data 6302316 # number of WriteReq accesses(hits+misses) (Count)
system.cpu.dcache.WriteReq.accesses::total 6302316 # number of WriteReq accesses(hits+misses) (Count)
system.cpu.dcache.WriteReq.missRate::cpu.data 0.499164 # miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.missRate::total 0.499164 # miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.avgMissLatency::cpu.data 83195.505723 # average WriteReq miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.avgMissLatency::total 83195.505723 # average WriteReq miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.mshrMisses::cpu.data 3145890 # number of WriteReq MSHR misses (Count)
system.cpu.dcache.WriteReq.mshrMisses::total 3145890 # number of WriteReq MSHR misses (Count)
system.cpu.dcache.WriteReq.mshrMissLatency::cpu.data 258578019499 # number of WriteReq MSHR miss ticks (Tick)
system.cpu.dcache.WriteReq.mshrMissLatency::total 258578019499 # number of WriteReq MSHR miss ticks (Tick)
system.cpu.dcache.WriteReq.mshrMissRate::cpu.data 0.499164 # mshr miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.mshrMissRate::total 0.499164 # mshr miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.avgMshrMissLatency::cpu.data 82195.505723 # average WriteReq mshr miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.avgMshrMissLatency::total 82195.505723 # average WriteReq mshr miss latency ((Tick/Count))
system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.dcache.tags.tagsInUse 1023.737805 # Average ticks per tags in use ((Tick/Count))
system.cpu.dcache.tags.totalRefs 6318210 # Total number of references to valid blocks. (Count)
system.cpu.dcache.tags.sampledRefs 3146683 # Sample count of references to valid blocks. (Count)
system.cpu.dcache.tags.avgRefs 2.007895 # Average number of references to valid blocks. ((Count/Count))
system.cpu.dcache.tags.warmupTick 176500 # The tick when the warmup percentage was hit. (Tick)
system.cpu.dcache.tags.occupancies::cpu.data 1023.737805 # Average occupied blocks per tick, per requestor ((Count/Tick))
system.cpu.dcache.tags.avgOccs::cpu.data 0.999744 # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.dcache.tags.avgOccs::total 0.999744 # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.dcache.tags.occupanciesTaskId::1024 1024 # Occupied blocks per task id (Count)
system.cpu.dcache.tags.ageTaskId_1024::0 47 # Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ageTaskId_1024::1 944 # Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ageTaskId_1024::2 32 # Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ageTaskId_1024::4 1 # Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
system.cpu.dcache.tags.tagAccesses 15785295 # Number of tag accesses (Count)
system.cpu.dcache.tags.dataAccesses 15785295 # Number of data accesses (Count)
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.decode.idleCycles 1631095 # Number of cycles decode is idle (Cycle)
system.cpu.decode.blockedCycles 524112434 # Number of cycles decode is blocked (Cycle)
system.cpu.decode.runCycles 507871 # Number of cycles decode is running (Cycle)
system.cpu.decode.unblockCycles 4348156 # Number of cycles decode is unblocking (Cycle)
system.cpu.decode.squashCycles 17160 # Number of cycles decode is squashing (Cycle)
system.cpu.decode.branchResolved 3434810 # Number of times decode resolved a branch (Count)
system.cpu.decode.branchMispred 373 # Number of times decode detected a branch misprediction (Count)
system.cpu.decode.decodedInsts 37937288 # Number of instructions handled by decode (Count)
system.cpu.decode.squashedInsts 1720 # Number of squashed instructions handled by decode (Count)
system.cpu.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
system.cpu.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
system.cpu.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
system.cpu.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
system.cpu.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dtb_walker_cache.replacements 0 # number of replacements (Count)
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
system.cpu.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
system.cpu.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
system.cpu.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
system.cpu.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
system.cpu.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
system.cpu.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.executeStats0.numInsts 37742496 # Number of executed instructions (Count)
system.cpu.executeStats0.numNop 0 # Number of nop insts executed (Count)
system.cpu.executeStats0.numBranches 3442558 # Number of branches executed (Count)
system.cpu.executeStats0.numLoadInsts 3429319 # Number of load instructions executed (Count)
system.cpu.executeStats0.numStoreInsts 6827557 # Number of stores executed (Count)
system.cpu.executeStats0.instRate 0.071121 # Inst execution rate ((Count/Cycle))
system.cpu.executeStats0.numCCRegReads 17201017 # Number of times the CC registers were read (Count)
system.cpu.executeStats0.numCCRegWrites 20532279 # Number of times the CC registers were written (Count)
system.cpu.executeStats0.numFpRegReads 2152 # Number of times the floating registers were read (Count)
system.cpu.executeStats0.numFpRegWrites 1105 # Number of times the floating registers were written (Count)
system.cpu.executeStats0.numIntRegReads 61673291 # Number of times the integer registers were read (Count)
system.cpu.executeStats0.numIntRegWrites 24037577 # Number of times the integer registers were written (Count)
system.cpu.executeStats0.numMemRefs 10256876 # Number of memory refs (Count)
system.cpu.executeStats0.numMiscRegReads 17141716 # Number of times the Misc registers were read (Count)
system.cpu.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
system.cpu.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
system.cpu.fetch.predictedBranches 3505222 # Number of branches that fetch has predicted taken (Count)
system.cpu.fetch.cycles 530549513 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
system.cpu.fetch.squashCycles 35054 # Number of cycles fetch has spent squashing (Cycle)
system.cpu.fetch.miscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
system.cpu.fetch.pendingTrapStallCycles 290 # Number of stall cycles due to pending traps (Cycle)
system.cpu.fetch.cacheLines 20558 # Number of cache lines fetched (Count)
system.cpu.fetch.icacheSquashes 528 # Number of outstanding Icache misses that were squashed (Count)
system.cpu.fetch.nisnDist::samples 530616716 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::mean 0.072996 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::stdev 0.677328 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::0 522773943 98.52% 98.52% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::1 821359 0.15% 98.68% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::2 820635 0.15% 98.83% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::3 1870282 0.35% 99.18% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::4 398448 0.08% 99.26% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::5 394666 0.07% 99.33% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::6 396785 0.07% 99.41% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::7 413384 0.08% 99.49% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::8 2727214 0.51% 100.00% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::total 530616716 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetchStats0.numInsts 28137249 # Number of instructions fetched (thread level) (Count)
system.cpu.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
system.cpu.fetchStats0.fetchRate 0.053021 # Number of inst fetches per cycle ((Count/Cycle))
system.cpu.fetchStats0.numBranches 3527917 # Number of branches fetched (Count)
system.cpu.fetchStats0.branchRate 0.006648 # Number of branch fetches per cycle (Ratio)
system.cpu.fetchStats0.icacheStallCycles 49334 # ICache total stall cycles (Cycle)
system.cpu.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
system.cpu.icache.demandHits::cpu.inst 19561 # number of demand (read+write) hits (Count)
system.cpu.icache.demandHits::total 19561 # number of demand (read+write) hits (Count)
system.cpu.icache.overallHits::cpu.inst 19561 # number of overall hits (Count)
system.cpu.icache.overallHits::total 19561 # number of overall hits (Count)
system.cpu.icache.demandMisses::cpu.inst 997 # number of demand (read+write) misses (Count)
system.cpu.icache.demandMisses::total 997 # number of demand (read+write) misses (Count)
system.cpu.icache.overallMisses::cpu.inst 997 # number of overall misses (Count)
system.cpu.icache.overallMisses::total 997 # number of overall misses (Count)
system.cpu.icache.demandMissLatency::cpu.inst 77118000 # number of demand (read+write) miss ticks (Tick)
system.cpu.icache.demandMissLatency::total 77118000 # number of demand (read+write) miss ticks (Tick)
system.cpu.icache.overallMissLatency::cpu.inst 77118000 # number of overall miss ticks (Tick)
system.cpu.icache.overallMissLatency::total 77118000 # number of overall miss ticks (Tick)
system.cpu.icache.demandAccesses::cpu.inst 20558 # number of demand (read+write) accesses (Count)
system.cpu.icache.demandAccesses::total 20558 # number of demand (read+write) accesses (Count)
system.cpu.icache.overallAccesses::cpu.inst 20558 # number of overall (read+write) accesses (Count)
system.cpu.icache.overallAccesses::total 20558 # number of overall (read+write) accesses (Count)
system.cpu.icache.demandMissRate::cpu.inst 0.048497 # miss rate for demand accesses (Ratio)
system.cpu.icache.demandMissRate::total 0.048497 # miss rate for demand accesses (Ratio)
system.cpu.icache.overallMissRate::cpu.inst 0.048497 # miss rate for overall accesses (Ratio)
system.cpu.icache.overallMissRate::total 0.048497 # miss rate for overall accesses (Ratio)
system.cpu.icache.demandAvgMissLatency::cpu.inst 77350.050150 # average overall miss latency in ticks ((Tick/Count))
system.cpu.icache.demandAvgMissLatency::total 77350.050150 # average overall miss latency in ticks ((Tick/Count))
system.cpu.icache.overallAvgMissLatency::cpu.inst 77350.050150 # average overall miss latency ((Tick/Count))
system.cpu.icache.overallAvgMissLatency::total 77350.050150 # average overall miss latency ((Tick/Count))
system.cpu.icache.blockedCycles::no_mshrs 318 # number of cycles access was blocked (Cycle)
system.cpu.icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
system.cpu.icache.blockedCauses::no_mshrs 6 # number of times access was blocked (Count)
system.cpu.icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
system.cpu.icache.avgBlocked::no_mshrs 53 # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.icache.writebacks::writebacks 340 # number of writebacks (Count)
system.cpu.icache.writebacks::total 340 # number of writebacks (Count)
system.cpu.icache.demandMshrHits::cpu.inst 194 # number of demand (read+write) MSHR hits (Count)
system.cpu.icache.demandMshrHits::total 194 # number of demand (read+write) MSHR hits (Count)
system.cpu.icache.overallMshrHits::cpu.inst 194 # number of overall MSHR hits (Count)
system.cpu.icache.overallMshrHits::total 194 # number of overall MSHR hits (Count)
system.cpu.icache.demandMshrMisses::cpu.inst 803 # number of demand (read+write) MSHR misses (Count)
system.cpu.icache.demandMshrMisses::total 803 # number of demand (read+write) MSHR misses (Count)
system.cpu.icache.overallMshrMisses::cpu.inst 803 # number of overall MSHR misses (Count)
system.cpu.icache.overallMshrMisses::total 803 # number of overall MSHR misses (Count)
system.cpu.icache.demandMshrMissLatency::cpu.inst 64885500 # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.icache.demandMshrMissLatency::total 64885500 # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.icache.overallMshrMissLatency::cpu.inst 64885500 # number of overall MSHR miss ticks (Tick)
system.cpu.icache.overallMshrMissLatency::total 64885500 # number of overall MSHR miss ticks (Tick)
system.cpu.icache.demandMshrMissRate::cpu.inst 0.039060 # mshr miss ratio for demand accesses (Ratio)
system.cpu.icache.demandMshrMissRate::total 0.039060 # mshr miss ratio for demand accesses (Ratio)
system.cpu.icache.overallMshrMissRate::cpu.inst 0.039060 # mshr miss ratio for overall accesses (Ratio)
system.cpu.icache.overallMshrMissRate::total 0.039060 # mshr miss ratio for overall accesses (Ratio)
system.cpu.icache.demandAvgMshrMissLatency::cpu.inst 80803.860523 # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.demandAvgMshrMissLatency::total 80803.860523 # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.overallAvgMshrMissLatency::cpu.inst 80803.860523 # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.overallAvgMshrMissLatency::total 80803.860523 # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.replacements 340 # number of replacements (Count)
system.cpu.icache.ReadReq.hits::cpu.inst 19561 # number of ReadReq hits (Count)
system.cpu.icache.ReadReq.hits::total 19561 # number of ReadReq hits (Count)
system.cpu.icache.ReadReq.misses::cpu.inst 997 # number of ReadReq misses (Count)
system.cpu.icache.ReadReq.misses::total 997 # number of ReadReq misses (Count)
system.cpu.icache.ReadReq.missLatency::cpu.inst 77118000 # number of ReadReq miss ticks (Tick)
system.cpu.icache.ReadReq.missLatency::total 77118000 # number of ReadReq miss ticks (Tick)
system.cpu.icache.ReadReq.accesses::cpu.inst 20558 # number of ReadReq accesses(hits+misses) (Count)
system.cpu.icache.ReadReq.accesses::total 20558 # number of ReadReq accesses(hits+misses) (Count)
system.cpu.icache.ReadReq.missRate::cpu.inst 0.048497 # miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.missRate::total 0.048497 # miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.avgMissLatency::cpu.inst 77350.050150 # average ReadReq miss latency ((Tick/Count))
system.cpu.icache.ReadReq.avgMissLatency::total 77350.050150 # average ReadReq miss latency ((Tick/Count))
system.cpu.icache.ReadReq.mshrHits::cpu.inst 194 # number of ReadReq MSHR hits (Count)
system.cpu.icache.ReadReq.mshrHits::total 194 # number of ReadReq MSHR hits (Count)
system.cpu.icache.ReadReq.mshrMisses::cpu.inst 803 # number of ReadReq MSHR misses (Count)
system.cpu.icache.ReadReq.mshrMisses::total 803 # number of ReadReq MSHR misses (Count)
system.cpu.icache.ReadReq.mshrMissLatency::cpu.inst 64885500 # number of ReadReq MSHR miss ticks (Tick)
system.cpu.icache.ReadReq.mshrMissLatency::total 64885500 # number of ReadReq MSHR miss ticks (Tick)
system.cpu.icache.ReadReq.mshrMissRate::cpu.inst 0.039060 # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.mshrMissRate::total 0.039060 # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.avgMshrMissLatency::cpu.inst 80803.860523 # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.icache.ReadReq.avgMshrMissLatency::total 80803.860523 # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.icache.tags.tagsInUse 407.969337 # Average ticks per tags in use ((Tick/Count))
system.cpu.icache.tags.totalRefs 20364 # Total number of references to valid blocks. (Count)
system.cpu.icache.tags.sampledRefs 803 # Sample count of references to valid blocks. (Count)
system.cpu.icache.tags.avgRefs 25.359900 # Average number of references to valid blocks. ((Count/Count))
system.cpu.icache.tags.warmupTick 87500 # The tick when the warmup percentage was hit. (Tick)
system.cpu.icache.tags.occupancies::cpu.inst 407.969337 # Average occupied blocks per tick, per requestor ((Count/Tick))
system.cpu.icache.tags.avgOccs::cpu.inst 0.796815 # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.icache.tags.avgOccs::total 0.796815 # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.icache.tags.occupanciesTaskId::1024 461 # Occupied blocks per task id (Count)
system.cpu.icache.tags.ageTaskId_1024::0 116 # Occupied blocks per task id, per block age (Count)
system.cpu.icache.tags.ageTaskId_1024::1 80 # Occupied blocks per task id, per block age (Count)
system.cpu.icache.tags.ageTaskId_1024::4 265 # Occupied blocks per task id, per block age (Count)
system.cpu.icache.tags.ratioOccsTaskId::1024 0.900391 # Ratio of occupied blocks and all blocks, per task id (Ratio)
system.cpu.icache.tags.tagAccesses 41919 # Number of tag accesses (Count)
system.cpu.icache.tags.dataAccesses 41919 # Number of data accesses (Count)
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
system.cpu.iew.squashCycles 17160 # Number of cycles IEW is squashing (Cycle)
system.cpu.iew.blockCycles 401882 # Number of cycles IEW is blocking (Cycle)
system.cpu.iew.unblockCycles 279150396 # Number of cycles IEW is unblocking (Cycle)
system.cpu.iew.dispatchedInsts 37751832 # Number of instructions dispatched to IQ (Count)
system.cpu.iew.dispSquashedInsts 91 # Number of squashed instructions skipped by dispatch (Count)
system.cpu.iew.dispLoadInsts 3430388 # Number of dispatched load instructions (Count)
system.cpu.iew.dispStoreInsts 6828306 # Number of dispatched store instructions (Count)
system.cpu.iew.dispNonSpecInsts 84 # Number of dispatched non-speculative instructions (Count)
system.cpu.iew.iqFullEvents 1637 # Number of times the IQ has become full, causing a stall (Count)
system.cpu.iew.lsqFullEvents 279165142 # Number of times the LSQ has become full, causing a stall (Count)
system.cpu.iew.memOrderViolationEvents 61 # Number of memory order violations (Count)
system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly (Count)
system.cpu.iew.predictedNotTakenIncorrect 738 # Number of branches that were predicted not taken incorrectly (Count)
system.cpu.iew.branchMispredicts 797 # Number of branch mispredicts detected at execute (Count)
system.cpu.iew.instsToCommit 37742088 # Cumulative count of insts sent to commit (Count)
system.cpu.iew.writebackCount 37479566 # Cumulative count of insts written-back (Count)
system.cpu.iew.producerInst 14704706 # Number of instructions producing a value (Count)
system.cpu.iew.consumerInst 23562581 # Number of instructions consuming a value (Count)
system.cpu.iew.wbRate 0.070626 # Insts written-back per cycle ((Count/Cycle))
system.cpu.iew.wbFanout 0.624070 # Average fanout of values written-back ((Count/Count))
system.cpu.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
system.cpu.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
system.cpu.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
system.cpu.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
system.cpu.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
system.cpu.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.itb_walker_cache.replacements 0 # number of replacements (Count)
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
system.cpu.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
system.cpu.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
system.cpu.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
system.cpu.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
system.cpu.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
system.cpu.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.lsq0.forwLoads 3412243 # Number of loads that had data forwarded from stores (Count)
system.cpu.lsq0.squashedLoads 265023 # Number of loads squashed (Count)
system.cpu.lsq0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed (Count)
system.cpu.lsq0.memOrderViolation 61 # Number of memory ordering violations (Count)
system.cpu.lsq0.squashedStores 525960 # Number of stores squashed (Count)
system.cpu.lsq0.rescheduledLoads 2 # Number of loads that were rescheduled (Count)
system.cpu.lsq0.blockedByCache 12 # Number of times an access to memory failed due to the cache being blocked (Count)
system.cpu.lsq0.loadToUse::samples 3165365 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::mean 2.087006 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::stdev 3.782300 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::0-9 3163669 99.95% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::10-19 1 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::20-29 8 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::100-109 2 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::110-119 6 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::120-129 45 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::130-139 52 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::140-149 1347 0.04% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::150-159 35 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::160-169 21 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::170-179 79 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::180-189 3 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::190-199 3 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::200-209 54 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::210-219 8 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::220-229 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::230-239 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::250-259 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::270-279 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::290-299 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::overflows 27 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::max_value 738 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::total 3165365 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.mmu.dtb.rdAccesses 3429290 # TLB accesses on read requests (Count)
system.cpu.mmu.dtb.wrAccesses 6827557 # TLB accesses on write requests (Count)
system.cpu.mmu.dtb.rdMisses 125 # TLB misses on read requests (Count)
system.cpu.mmu.dtb.wrMisses 311320 # TLB misses on write requests (Count)
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
system.cpu.mmu.itb.wrAccesses 20610 # TLB accesses on write requests (Count)
system.cpu.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
system.cpu.mmu.itb.wrMisses 124 # TLB misses on write requests (Count)
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.power_state.pwrStateResidencyTicks::ON 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.rename.squashCycles 17160 # Number of cycles rename is squashing (Cycle)
system.cpu.rename.idleCycles 2862461 # Number of cycles rename is idle (Cycle)
system.cpu.rename.blockCycles 279556404 # Number of cycles rename is blocking (Cycle)
system.cpu.rename.serializeStallCycles 1092 # count of cycles rename stalled for serializing inst (Cycle)
system.cpu.rename.runCycles 3607889 # Number of cycles rename is running (Cycle)
system.cpu.rename.unblockCycles 244571710 # Number of cycles rename is unblocking (Cycle)
system.cpu.rename.renamedInsts 37804276 # Number of instructions processed by rename (Count)
system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full (Count)
system.cpu.rename.IQFullEvents 10826 # Number of times rename has blocked due to IQ full (Count)
system.cpu.rename.SQFullEvents 243707440 # Number of times rename has blocked due to SQ full (Count)
system.cpu.rename.renamedOperands 79024819 # Number of destination operands rename has renamed (Count)
system.cpu.rename.lookups 154549551 # Number of register rename lookups that rename has made (Count)
system.cpu.rename.intLookups 61808940 # Number of integer rename lookups (Count)
system.cpu.rename.fpLookups 2258 # Number of floating rename lookups (Count)
system.cpu.rename.committedMaps 72751303 # Number of HB maps that are committed (Count)
system.cpu.rename.undoneMaps 6273507 # Number of HB maps that are undone due to squashing (Count)
system.cpu.rename.serializing 46 # count of serializing insts renamed (Count)
system.cpu.rename.tempSerializing 46 # count of temporary serializing insts renamed (Count)
system.cpu.rename.skidInsts 23395044 # count of insts added to the skid buffer (Count)
system.cpu.rob.reads 567654444 # The number of ROB reads (Count)
system.cpu.rob.writes 75588580 # The number of ROB writes (Count)
system.cpu.thread_0.numInsts 25297289 # Number of Instructions committed (Count)
system.cpu.thread_0.numOps 34841936 # Number of Ops committed (Count)
system.cpu.thread_0.numMemRefs 0 # Number of Memory References (Count)
system.cpu.workload.numSyscalls 18 # Number of system calls (Count)
system.cpu_clk_domain.clock 500 # Clock period in ticks (Tick)
system.cpu_voltage_domain.voltage 1 # Voltage in Volts (Volt)
system.l2.demandHits::cpu.inst 24 # number of demand (read+write) hits (Count)
system.l2.demandHits::cpu.data 4 # number of demand (read+write) hits (Count)
system.l2.demandHits::total 28 # number of demand (read+write) hits (Count)
system.l2.overallHits::cpu.inst 24 # number of overall hits (Count)
system.l2.overallHits::cpu.data 4 # number of overall hits (Count)
system.l2.overallHits::total 28 # number of overall hits (Count)
system.l2.demandMisses::cpu.inst 777 # number of demand (read+write) misses (Count)
system.l2.demandMisses::cpu.data 3146679 # number of demand (read+write) misses (Count)
system.l2.demandMisses::total 3147456 # number of demand (read+write) misses (Count)
system.l2.overallMisses::cpu.inst 777 # number of overall misses (Count)
system.l2.overallMisses::cpu.data 3146679 # number of overall misses (Count)
system.l2.overallMisses::total 3147456 # number of overall misses (Count)
system.l2.demandMissLatency::cpu.inst 63395000 # number of demand (read+write) miss ticks (Tick)
system.l2.demandMissLatency::cpu.data 253920824000 # number of demand (read+write) miss ticks (Tick)
system.l2.demandMissLatency::total 253984219000 # number of demand (read+write) miss ticks (Tick)
system.l2.overallMissLatency::cpu.inst 63395000 # number of overall miss ticks (Tick)
system.l2.overallMissLatency::cpu.data 253920824000 # number of overall miss ticks (Tick)
system.l2.overallMissLatency::total 253984219000 # number of overall miss ticks (Tick)
system.l2.demandAccesses::cpu.inst 801 # number of demand (read+write) accesses (Count)
system.l2.demandAccesses::cpu.data 3146683 # number of demand (read+write) accesses (Count)
system.l2.demandAccesses::total 3147484 # number of demand (read+write) accesses (Count)
system.l2.overallAccesses::cpu.inst 801 # number of overall (read+write) accesses (Count)
system.l2.overallAccesses::cpu.data 3146683 # number of overall (read+write) accesses (Count)
system.l2.overallAccesses::total 3147484 # number of overall (read+write) accesses (Count)
system.l2.demandMissRate::cpu.inst 0.970037 # miss rate for demand accesses (Ratio)
system.l2.demandMissRate::cpu.data 0.999999 # miss rate for demand accesses (Ratio)
system.l2.demandMissRate::total 0.999991 # miss rate for demand accesses (Ratio)
system.l2.overallMissRate::cpu.inst 0.970037 # miss rate for overall accesses (Ratio)
system.l2.overallMissRate::cpu.data 0.999999 # miss rate for overall accesses (Ratio)
system.l2.overallMissRate::total 0.999991 # miss rate for overall accesses (Ratio)
system.l2.demandAvgMissLatency::cpu.inst 81589.446589 # average overall miss latency in ticks ((Tick/Count))
system.l2.demandAvgMissLatency::cpu.data 80694.860836 # average overall miss latency in ticks ((Tick/Count))
system.l2.demandAvgMissLatency::total 80695.081679 # average overall miss latency in ticks ((Tick/Count))
system.l2.overallAvgMissLatency::cpu.inst 81589.446589 # average overall miss latency ((Tick/Count))
system.l2.overallAvgMissLatency::cpu.data 80694.860836 # average overall miss latency ((Tick/Count))
system.l2.overallAvgMissLatency::total 80695.081679 # average overall miss latency ((Tick/Count))
system.l2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
system.l2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
system.l2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
system.l2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
system.l2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
system.l2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
system.l2.writebacks::writebacks 3113553 # number of writebacks (Count)
system.l2.writebacks::total 3113553 # number of writebacks (Count)
system.l2.demandMshrMisses::cpu.inst 777 # number of demand (read+write) MSHR misses (Count)
system.l2.demandMshrMisses::cpu.data 3146679 # number of demand (read+write) MSHR misses (Count)
system.l2.demandMshrMisses::total 3147456 # number of demand (read+write) MSHR misses (Count)
system.l2.overallMshrMisses::cpu.inst 777 # number of overall MSHR misses (Count)
system.l2.overallMshrMisses::cpu.data 3146679 # number of overall MSHR misses (Count)
system.l2.overallMshrMisses::total 3147456 # number of overall MSHR misses (Count)
system.l2.demandMshrMissLatency::cpu.inst 55625000 # number of demand (read+write) MSHR miss ticks (Tick)
system.l2.demandMshrMissLatency::cpu.data 222454034000 # number of demand (read+write) MSHR miss ticks (Tick)
system.l2.demandMshrMissLatency::total 222509659000 # number of demand (read+write) MSHR miss ticks (Tick)
system.l2.overallMshrMissLatency::cpu.inst 55625000 # number of overall MSHR miss ticks (Tick)
system.l2.overallMshrMissLatency::cpu.data 222454034000 # number of overall MSHR miss ticks (Tick)
system.l2.overallMshrMissLatency::total 222509659000 # number of overall MSHR miss ticks (Tick)
system.l2.demandMshrMissRate::cpu.inst 0.970037 # mshr miss ratio for demand accesses (Ratio)
system.l2.demandMshrMissRate::cpu.data 0.999999 # mshr miss ratio for demand accesses (Ratio)
system.l2.demandMshrMissRate::total 0.999991 # mshr miss ratio for demand accesses (Ratio)
system.l2.overallMshrMissRate::cpu.inst 0.970037 # mshr miss ratio for overall accesses (Ratio)
system.l2.overallMshrMissRate::cpu.data 0.999999 # mshr miss ratio for overall accesses (Ratio)
system.l2.overallMshrMissRate::total 0.999991 # mshr miss ratio for overall accesses (Ratio)
system.l2.demandAvgMshrMissLatency::cpu.inst 71589.446589 # average overall mshr miss latency ((Tick/Count))
system.l2.demandAvgMshrMissLatency::cpu.data 70694.860836 # average overall mshr miss latency ((Tick/Count))
system.l2.demandAvgMshrMissLatency::total 70695.081679 # average overall mshr miss latency ((Tick/Count))
system.l2.overallAvgMshrMissLatency::cpu.inst 71589.446589 # average overall mshr miss latency ((Tick/Count))
system.l2.overallAvgMshrMissLatency::cpu.data 70694.860836 # average overall mshr miss latency ((Tick/Count))
system.l2.overallAvgMshrMissLatency::total 70695.081679 # average overall mshr miss latency ((Tick/Count))
system.l2.replacements 3114832 # number of replacements (Count)
system.l2.ReadCleanReq.hits::cpu.inst 24 # number of ReadCleanReq hits (Count)
system.l2.ReadCleanReq.hits::total 24 # number of ReadCleanReq hits (Count)
system.l2.ReadCleanReq.misses::cpu.inst 777 # number of ReadCleanReq misses (Count)
system.l2.ReadCleanReq.misses::total 777 # number of ReadCleanReq misses (Count)
system.l2.ReadCleanReq.missLatency::cpu.inst 63395000 # number of ReadCleanReq miss ticks (Tick)
system.l2.ReadCleanReq.missLatency::total 63395000 # number of ReadCleanReq miss ticks (Tick)
system.l2.ReadCleanReq.accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) (Count)
system.l2.ReadCleanReq.accesses::total 801 # number of ReadCleanReq accesses(hits+misses) (Count)
system.l2.ReadCleanReq.missRate::cpu.inst 0.970037 # miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.missRate::total 0.970037 # miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.avgMissLatency::cpu.inst 81589.446589 # average ReadCleanReq miss latency ((Tick/Count))
system.l2.ReadCleanReq.avgMissLatency::total 81589.446589 # average ReadCleanReq miss latency ((Tick/Count))
system.l2.ReadCleanReq.mshrMisses::cpu.inst 777 # number of ReadCleanReq MSHR misses (Count)
system.l2.ReadCleanReq.mshrMisses::total 777 # number of ReadCleanReq MSHR misses (Count)
system.l2.ReadCleanReq.mshrMissLatency::cpu.inst 55625000 # number of ReadCleanReq MSHR miss ticks (Tick)
system.l2.ReadCleanReq.mshrMissLatency::total 55625000 # number of ReadCleanReq MSHR miss ticks (Tick)
system.l2.ReadCleanReq.mshrMissRate::cpu.inst 0.970037 # mshr miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.mshrMissRate::total 0.970037 # mshr miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.avgMshrMissLatency::cpu.inst 71589.446589 # average ReadCleanReq mshr miss latency ((Tick/Count))
system.l2.ReadCleanReq.avgMshrMissLatency::total 71589.446589 # average ReadCleanReq mshr miss latency ((Tick/Count))
system.l2.ReadExReq.hits::cpu.data 2 # number of ReadExReq hits (Count)
system.l2.ReadExReq.hits::total 2 # number of ReadExReq hits (Count)
system.l2.ReadExReq.misses::cpu.data 3145890 # number of ReadExReq misses (Count)
system.l2.ReadExReq.misses::total 3145890 # number of ReadExReq misses (Count)
system.l2.ReadExReq.missLatency::cpu.data 253859512000 # number of ReadExReq miss ticks (Tick)
system.l2.ReadExReq.missLatency::total 253859512000 # number of ReadExReq miss ticks (Tick)
system.l2.ReadExReq.accesses::cpu.data 3145892 # number of ReadExReq accesses(hits+misses) (Count)
system.l2.ReadExReq.accesses::total 3145892 # number of ReadExReq accesses(hits+misses) (Count)
system.l2.ReadExReq.missRate::cpu.data 0.999999 # miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.missRate::total 0.999999 # miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.avgMissLatency::cpu.data 80695.609827 # average ReadExReq miss latency ((Tick/Count))
system.l2.ReadExReq.avgMissLatency::total 80695.609827 # average ReadExReq miss latency ((Tick/Count))
system.l2.ReadExReq.mshrMisses::cpu.data 3145890 # number of ReadExReq MSHR misses (Count)
system.l2.ReadExReq.mshrMisses::total 3145890 # number of ReadExReq MSHR misses (Count)
system.l2.ReadExReq.mshrMissLatency::cpu.data 222400612000 # number of ReadExReq MSHR miss ticks (Tick)
system.l2.ReadExReq.mshrMissLatency::total 222400612000 # number of ReadExReq MSHR miss ticks (Tick)
system.l2.ReadExReq.mshrMissRate::cpu.data 0.999999 # mshr miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.mshrMissRate::total 0.999999 # mshr miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.avgMshrMissLatency::cpu.data 70695.609827 # average ReadExReq mshr miss latency ((Tick/Count))
system.l2.ReadExReq.avgMshrMissLatency::total 70695.609827 # average ReadExReq mshr miss latency ((Tick/Count))
system.l2.ReadSharedReq.hits::cpu.data 2 # number of ReadSharedReq hits (Count)
system.l2.ReadSharedReq.hits::total 2 # number of ReadSharedReq hits (Count)
system.l2.ReadSharedReq.misses::cpu.data 789 # number of ReadSharedReq misses (Count)
system.l2.ReadSharedReq.misses::total 789 # number of ReadSharedReq misses (Count)
system.l2.ReadSharedReq.missLatency::cpu.data 61312000 # number of ReadSharedReq miss ticks (Tick)
system.l2.ReadSharedReq.missLatency::total 61312000 # number of ReadSharedReq miss ticks (Tick)
system.l2.ReadSharedReq.accesses::cpu.data 791 # number of ReadSharedReq accesses(hits+misses) (Count)
system.l2.ReadSharedReq.accesses::total 791 # number of ReadSharedReq accesses(hits+misses) (Count)
system.l2.ReadSharedReq.missRate::cpu.data 0.997472 # miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.missRate::total 0.997472 # miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.avgMissLatency::cpu.data 77708.491762 # average ReadSharedReq miss latency ((Tick/Count))
system.l2.ReadSharedReq.avgMissLatency::total 77708.491762 # average ReadSharedReq miss latency ((Tick/Count))
system.l2.ReadSharedReq.mshrMisses::cpu.data 789 # number of ReadSharedReq MSHR misses (Count)
system.l2.ReadSharedReq.mshrMisses::total 789 # number of ReadSharedReq MSHR misses (Count)
system.l2.ReadSharedReq.mshrMissLatency::cpu.data 53422000 # number of ReadSharedReq MSHR miss ticks (Tick)
system.l2.ReadSharedReq.mshrMissLatency::total 53422000 # number of ReadSharedReq MSHR miss ticks (Tick)
system.l2.ReadSharedReq.mshrMissRate::cpu.data 0.997472 # mshr miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.mshrMissRate::total 0.997472 # mshr miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.avgMshrMissLatency::cpu.data 67708.491762 # average ReadSharedReq mshr miss latency ((Tick/Count))
system.l2.ReadSharedReq.avgMshrMissLatency::total 67708.491762 # average ReadSharedReq mshr miss latency ((Tick/Count))
system.l2.UpgradeReq.hits::cpu.data 2 # number of UpgradeReq hits (Count)
system.l2.UpgradeReq.hits::total 2 # number of UpgradeReq hits (Count)
system.l2.UpgradeReq.accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) (Count)
system.l2.UpgradeReq.accesses::total 2 # number of UpgradeReq accesses(hits+misses) (Count)
system.l2.WritebackClean.hits::writebacks 340 # number of WritebackClean hits (Count)
system.l2.WritebackClean.hits::total 340 # number of WritebackClean hits (Count)
system.l2.WritebackClean.accesses::writebacks 340 # number of WritebackClean accesses(hits+misses) (Count)
system.l2.WritebackClean.accesses::total 340 # number of WritebackClean accesses(hits+misses) (Count)
system.l2.WritebackDirty.hits::writebacks 3144953 # number of WritebackDirty hits (Count)
system.l2.WritebackDirty.hits::total 3144953 # number of WritebackDirty hits (Count)
system.l2.WritebackDirty.accesses::writebacks 3144953 # number of WritebackDirty accesses(hits+misses) (Count)
system.l2.WritebackDirty.accesses::total 3144953 # number of WritebackDirty accesses(hits+misses) (Count)
system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.l2.tags.tagsInUse 32612.582114 # Average ticks per tags in use ((Tick/Count))
system.l2.tags.totalRefs 6293485 # Total number of references to valid blocks. (Count)
system.l2.tags.sampledRefs 3147600 # Sample count of references to valid blocks. (Count)
system.l2.tags.avgRefs 1.999455 # Average number of references to valid blocks. ((Count/Count))
system.l2.tags.warmupTick 77000 # The tick when the warmup percentage was hit. (Tick)
system.l2.tags.occupancies::writebacks 0.013576 # Average occupied blocks per tick, per requestor ((Count/Tick))
system.l2.tags.occupancies::cpu.inst 5.025274 # Average occupied blocks per tick, per requestor ((Count/Tick))
system.l2.tags.occupancies::cpu.data 32607.543264 # Average occupied blocks per tick, per requestor ((Count/Tick))
system.l2.tags.avgOccs::writebacks 0.000000 # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.avgOccs::cpu.inst 0.000153 # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.avgOccs::cpu.data 0.995103 # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.avgOccs::total 0.995257 # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.occupanciesTaskId::1024 32768 # Occupied blocks per task id (Count)
system.l2.tags.ageTaskId_1024::0 236 # Occupied blocks per task id, per block age (Count)
system.l2.tags.ageTaskId_1024::1 1190 # Occupied blocks per task id, per block age (Count)
system.l2.tags.ageTaskId_1024::2 10685 # Occupied blocks per task id, per block age (Count)
system.l2.tags.ageTaskId_1024::3 20657 # Occupied blocks per task id, per block age (Count)
system.l2.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
system.l2.tags.tagAccesses 53495480 # Number of tag accesses (Count)
system.l2.tags.dataAccesses 53495480 # Number of data accesses (Count)
system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.mem_ctrls.avgPriority_writebacks::samples 3113552.00 # Average QoS priority value for accepted requests (Count)
system.mem_ctrls.avgPriority_cpu.inst::samples 777.00 # Average QoS priority value for accepted requests (Count)
system.mem_ctrls.avgPriority_cpu.data::samples 3146679.00 # Average QoS priority value for accepted requests (Count)
system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (Second)
system.mem_ctrls.priorityMaxLatency 0.000071634500 # per QoS priority maximum request to response latency (Second)
system.mem_ctrls.numReadWriteTurnArounds 194593 # Number of turnarounds from READ to WRITE (Count)
system.mem_ctrls.numWriteReadTurnArounds 194593 # Number of turnarounds from WRITE to READ (Count)
system.mem_ctrls.numStayReadState 9278039 # Number of times bus staying in READ state (Count)
system.mem_ctrls.numStayWriteState 2920427 # Number of times bus staying in WRITE state (Count)
system.mem_ctrls.readReqs 3147456 # Number of read requests accepted (Count)
system.mem_ctrls.writeReqs 3113552 # Number of write requests accepted (Count)
system.mem_ctrls.readBursts 3147456 # Number of controller read bursts, including those serviced by the write queue (Count)
system.mem_ctrls.writeBursts 3113552 # Number of controller write bursts, including those merged in the write queue (Count)
system.mem_ctrls.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
system.mem_ctrls.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing ((Count/Tick))
system.mem_ctrls.avgWrQLen 25.99 # Average write queue length when enqueuing ((Count/Tick))
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry (Count)
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry (Count)
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::6 3147456 # Read request sizes (log2) (Count)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::6 3113552 # Write request sizes (log2) (Count)
system.mem_ctrls.rdQLenPdf::0 3147012 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::1 334 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::2 92 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::3 16 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::4 1 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::15 11 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::16 12 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::17 192318 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::18 194583 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::19 194590 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::20 194595 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::21 194615 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::22 194597 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::23 194602 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::24 194601 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::25 196844 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::26 194600 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::27 194599 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::28 194598 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::29 194593 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::30 194593 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::31 194593 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::32 194593 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.rdPerTurnAround::samples 194593 # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::mean 16.174523 # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::gmean 16.000177 # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::stdev 75.665346 # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::0-2047 194592 100.00% 100.00% # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
system.mem_ctrls.rdPerTurnAround::total 194593 # Reads before turning the bus around for writes (Count)
system.mem_ctrls.wrPerTurnAround::samples 194593 # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::mean 16.000195 # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::gmean 16.000179 # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::stdev 0.024203 # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::16 194579 99.99% 99.99% # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::17 2 0.00% 99.99% # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::18 2 0.00% 99.99% # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::19 8 0.00% 100.00% # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::20 2 0.00% 100.00% # Writes before turning the bus around for reads (Count)
system.mem_ctrls.wrPerTurnAround::total 194593 # Writes before turning the bus around for reads (Count)
system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
system.mem_ctrls.bytesReadSys 201437184 # Total read bytes from the system interface side (Byte)
system.mem_ctrls.bytesWrittenSys 199267328 # Total written bytes from the system interface side (Byte)
system.mem_ctrls.avgRdBWSys 759166918.88729644 # Average system read bandwidth in Byte/s ((Byte/Second))
system.mem_ctrls.avgWrBWSys 750989268.36002779 # Average system write bandwidth in Byte/s ((Byte/Second))
system.mem_ctrls.totGap 265339758500 # Total gap between requests (Tick)
system.mem_ctrls.avgGap 42379.72 # Average gap between requests ((Tick/Count))
system.mem_ctrls.requestorReadBytes::cpu.inst 49728 # Per-requestor bytes read from memory (Byte)
system.mem_ctrls.requestorReadBytes::cpu.data 201387456 # Per-requestor bytes read from memory (Byte)
system.mem_ctrls.requestorWriteBytes::writebacks 199265664 # Per-requestor bytes write to memory (Byte)
system.mem_ctrls.requestorReadRate::cpu.inst 187412.531255537586 # Per-requestor bytes read from memory rate ((Byte/Second))
system.mem_ctrls.requestorReadRate::cpu.data 758979506.356040954590 # Per-requestor bytes read from memory rate ((Byte/Second))
system.mem_ctrls.requestorWriteRate::writebacks 750982997.155635714531 # Per-requestor bytes write to memory rate ((Byte/Second))
system.mem_ctrls.requestorReadAccesses::cpu.inst 777 # Per-requestor read serviced memory accesses (Count)
system.mem_ctrls.requestorReadAccesses::cpu.data 3146679 # Per-requestor read serviced memory accesses (Count)
system.mem_ctrls.requestorWriteAccesses::writebacks 3113552 # Per-requestor write serviced memory accesses (Count)
system.mem_ctrls.requestorReadTotalLat::cpu.inst 23641750 # Per-requestor read total memory access latency (Tick)
system.mem_ctrls.requestorReadTotalLat::cpu.data 94197223000 # Per-requestor read total memory access latency (Tick)
system.mem_ctrls.requestorWriteTotalLat::writebacks 6478687482750 # Per-requestor write total memory access latency (Tick)
system.mem_ctrls.requestorReadAvgLat::cpu.inst 30426.96 # Per-requestor read average memory access latency ((Tick/Count))
system.mem_ctrls.requestorReadAvgLat::cpu.data 29935.44 # Per-requestor read average memory access latency ((Tick/Count))
system.mem_ctrls.requestorWriteAvgLat::writebacks 2080802.72 # Per-requestor write average memory access latency ((Tick/Count))
system.mem_ctrls.dram.bytesRead::cpu.inst 49728 # Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesRead::cpu.data 201387456 # Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesRead::total 201437184 # Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesInstRead::cpu.inst 49728 # Number of instructions bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesInstRead::total 49728 # Number of instructions bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesWritten::writebacks 199267328 # Number of bytes written to this memory (Byte)
system.mem_ctrls.dram.bytesWritten::total 199267328 # Number of bytes written to this memory (Byte)
system.mem_ctrls.dram.numReads::cpu.inst 777 # Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numReads::cpu.data 3146679 # Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numReads::total 3147456 # Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numWrites::writebacks 3113552 # Number of write requests responded to by this memory (Count)
system.mem_ctrls.dram.numWrites::total 3113552 # Number of write requests responded to by this memory (Count)
system.mem_ctrls.dram.bwRead::cpu.inst 187413 # Total read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwRead::cpu.data 758979506 # Total read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwRead::total 759166919 # Total read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwInstRead::cpu.inst 187413 # Instruction read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwInstRead::total 187413 # Instruction read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwWrite::writebacks 750989268 # Write bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwWrite::total 750989268 # Write bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::writebacks 750989268 # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::cpu.inst 187413 # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::cpu.data 758979506 # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::total 1510156187 # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.readBursts 3147456 # Number of DRAM read bursts (Count)
system.mem_ctrls.dram.writeBursts 3113526 # Number of DRAM write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::0 196842 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::1 196818 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::2 196711 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::3 196672 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::4 196761 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::5 196771 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::6 196633 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::7 196608 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::8 196667 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::9 196685 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::10 196666 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::11 196654 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::12 196646 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::13 196747 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::14 196826 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::15 196749 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::0 194616 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::1 194580 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::2 194602 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::3 194594 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::4 194614 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::5 194655 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::6 194567 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::7 194560 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::8 194603 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::9 194606 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::10 194605 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::11 194601 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::12 194586 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::13 194578 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::14 194596 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::15 194563 # Per bank write bursts (Count)
system.mem_ctrls.dram.totQLat 35206064750 # Total ticks spent queuing (Tick)
system.mem_ctrls.dram.totBusLat 15737280000 # Total ticks spent in databus transfers (Tick)
system.mem_ctrls.dram.totMemAccLat 94220864750 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
system.mem_ctrls.dram.avgQLat 11185.56 # Average queueing delay per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.avgBusLat 5000.00 # Average bus latency per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.avgMemAccLat 29935.56 # Average memory access latency per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.readRowHits 2896670 # Number of row buffer hits during reads (Count)
system.mem_ctrls.dram.writeRowHits 2893781 # Number of row buffer hits during writes (Count)
system.mem_ctrls.dram.readRowHitRate 92.03 # Row buffer hit rate for reads (Ratio)
system.mem_ctrls.dram.writeRowHitRate 92.94 # Row buffer hit rate for writes (Ratio)
system.mem_ctrls.dram.bytesPerActivate::samples 470517 # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::mean 851.617026 # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::gmean 739.888897 # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::stdev 302.836092 # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::0-127 8526 1.81% 1.81% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::128-255 35753 7.60% 9.41% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::256-383 23529 5.00% 14.41% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::384-511 9734 2.07% 16.48% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::512-639 8662 1.84% 18.32% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::640-767 14712 3.13% 21.45% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::768-895 26956 5.73% 27.18% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::896-1023 28530 6.06% 33.24% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::1024-1151 314115 66.76% 100.00% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::total 470517 # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesRead 201437184 # Total bytes read (Byte)
system.mem_ctrls.dram.bytesWritten 199265664 # Total bytes written (Byte)
system.mem_ctrls.dram.avgRdBW 759.166919 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
system.mem_ctrls.dram.avgWrBW 750.982997 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
system.mem_ctrls.dram.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
system.mem_ctrls.dram.busUtil 11.80 # Data bus utilization in percentage (Ratio)
system.mem_ctrls.dram.busUtilRead 5.93 # Data bus utilization in percentage for reads (Ratio)
system.mem_ctrls.dram.busUtilWrite 5.87 # Data bus utilization in percentage for writes (Ratio)
system.mem_ctrls.dram.pageHitRate 92.48 # Row buffer hit rate, read and write combined (Ratio)
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.mem_ctrls.dram.rank0.actEnergy 1679834940 # Energy for activate commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.preEnergy 892826880 # Energy for precharge commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.readEnergy 11237046240 # Energy for read commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.writeEnergy 8126433360 # Energy for write commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.refreshEnergy 20945087280.000004 # Energy for refresh commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.actBackEnergy 63662341830 # Energy for active background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.preBackEnergy 48280082880 # Energy for precharge background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.totalEnergy 154823653410 # Total energy per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.averagePower 583.492052 # Core power per rank (mW) (Watt)
system.mem_ctrls.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE 123429123500 # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::REF 8860020000 # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::ACT 133050637500 # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.actEnergy 1679756400 # Energy for activate commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.preEnergy 892785135 # Energy for precharge commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.readEnergy 11235789600 # Energy for read commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.writeEnergy 8126172360 # Energy for write commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.refreshEnergy 20945087280.000004 # Energy for refresh commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.actBackEnergy 63659147550 # Energy for active background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.preBackEnergy 48282772800 # Energy for precharge background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.totalEnergy 154821511125 # Total energy per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.averagePower 583.483979 # Core power per rank (mW) (Watt)
system.mem_ctrls.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE 123435597750 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::REF 8860020000 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::ACT 133044163250 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.membus.transDist::ReadResp 1566 # Transaction distribution (Count)
system.membus.transDist::WritebackDirty 3113552 # Transaction distribution (Count)
system.membus.transDist::CleanEvict 869 # Transaction distribution (Count)
system.membus.transDist::ReadExReq 3145890 # Transaction distribution (Count)
system.membus.transDist::ReadExResp 3145890 # Transaction distribution (Count)
system.membus.transDist::ReadSharedReq 1566 # Transaction distribution (Count)
system.membus.pktCount_system.l2.mem_side_port::system.mem_ctrls.port 9409333 # Packet count per connected requestor and responder (Count)
system.membus.pktCount_system.l2.mem_side_port::total 9409333 # Packet count per connected requestor and responder (Count)
system.membus.pktCount::total 9409333 # Packet count per connected requestor and responder (Count)
system.membus.pktSize_system.l2.mem_side_port::system.mem_ctrls.port 400704512 # Cumulative packet size per connected requestor and responder (Byte)
system.membus.pktSize_system.l2.mem_side_port::total 400704512 # Cumulative packet size per connected requestor and responder (Byte)
system.membus.pktSize::total 400704512 # Cumulative packet size per connected requestor and responder (Byte)
system.membus.snoops 0 # Total snoops (Count)
system.membus.snoopTraffic 0 # Total snoop traffic (Byte)
system.membus.snoopFanout::samples 3147456 # Request fanout histogram (Count)
system.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
system.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
system.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
system.membus.snoopFanout::0 3147456 100.00% 100.00% # Request fanout histogram (Count)
system.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
system.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
system.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
system.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
system.membus.snoopFanout::total 3147456 # Request fanout histogram (Count)
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.membus.reqLayer2.occupancy 18716538500 # Layer occupancy (ticks) (Tick)
system.membus.reqLayer2.utilization 0.1 # Layer utilization (Ratio)
system.membus.respLayer1.occupancy 16553480750 # Layer occupancy (ticks) (Tick)
system.membus.respLayer1.utilization 0.1 # Layer utilization (Ratio)
system.membus.snoop_filter.totRequests 6261877 # Total number of requests made to the snoop filter. (Count)
system.membus.snoop_filter.hitSingleRequests 3114421 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
system.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
system.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
system.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.tol2bus.transDist::ReadResp 1594 # Transaction distribution (Count)
system.tol2bus.transDist::WritebackDirty 6258506 # Transaction distribution (Count)
system.tol2bus.transDist::WritebackClean 340 # Transaction distribution (Count)
system.tol2bus.transDist::CleanEvict 1985 # Transaction distribution (Count)
system.tol2bus.transDist::UpgradeReq 2 # Transaction distribution (Count)
system.tol2bus.transDist::UpgradeResp 2 # Transaction distribution (Count)
system.tol2bus.transDist::ReadExReq 3145892 # Transaction distribution (Count)
system.tol2bus.transDist::ReadExResp 3145892 # Transaction distribution (Count)
system.tol2bus.transDist::ReadCleanReq 803 # Transaction distribution (Count)
system.tol2bus.transDist::ReadSharedReq 791 # Transaction distribution (Count)
system.tol2bus.pktCount_system.cpu.icache.mem_side_port::system.l2.cpu_side_port 1944 # Packet count per connected requestor and responder (Count)
system.tol2bus.pktCount_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port 9439029 # Packet count per connected requestor and responder (Count)
system.tol2bus.pktCount::total 9440973 # Packet count per connected requestor and responder (Count)
system.tol2bus.pktSize_system.cpu.icache.mem_side_port::system.l2.cpu_side_port 73024 # Cumulative packet size per connected requestor and responder (Byte)
system.tol2bus.pktSize_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port 402664704 # Cumulative packet size per connected requestor and responder (Byte)
system.tol2bus.pktSize::total 402737728 # Cumulative packet size per connected requestor and responder (Byte)
system.tol2bus.snoops 3114834 # Total snoops (Count)
system.tol2bus.snoopTraffic 199267520 # Total snoop traffic (Byte)
system.tol2bus.snoopFanout::samples 6262320 # Request fanout histogram (Count)
system.tol2bus.snoopFanout::mean 0.000066 # Request fanout histogram (Count)
system.tol2bus.snoopFanout::stdev 0.008150 # Request fanout histogram (Count)
system.tol2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::0 6261904 99.99% 99.99% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::1 416 0.01% 100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
system.tol2bus.snoopFanout::max_value 1 # Request fanout histogram (Count)
system.tol2bus.snoopFanout::total 6262320 # Request fanout histogram (Count)
system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 265339781000 # Cumulative time (in ticks) in various power states (Tick)
system.tol2bus.reqLayer0.occupancy 6292036500 # Layer occupancy (ticks) (Tick)
system.tol2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
system.tol2bus.respLayer0.occupancy 1204999 # Layer occupancy (ticks) (Tick)
system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
system.tol2bus.respLayer1.occupancy 4720025500 # Layer occupancy (ticks) (Tick)
system.tol2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
system.tol2bus.snoop_filter.totRequests 6293487 # Total number of requests made to the snoop filter. (Count)
system.tol2bus.snoop_filter.hitSingleRequests 3145999 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
system.tol2bus.snoop_filter.hitMultiRequests 4 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.tol2bus.snoop_filter.totSnoops 412 # Total number of snoops made to the snoop filter. (Count)
system.tol2bus.snoop_filter.hitSingleSnoops 412 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
system.tol2bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.voltage_domain.voltage 1 # Voltage in Volts (Volt)
system.workload.inst.arm 0 # number of arm instructions executed (Count)
system.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
Reference in New Issue View Git Blame Copy Permalink