1412 lines
179 KiB
Plaintext
1412 lines
179 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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simSeconds 0.209538 # Number of seconds simulated (Second)
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simTicks 209538034000 # Number of ticks simulated (Tick)
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finalTick 209538034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
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simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
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hostSeconds 283.34 # Real time elapsed on the host (Second)
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hostTickRate 739540990 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
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hostMemory 674316 # Number of bytes of host memory used (Byte)
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simInsts 20000000 # Number of instructions simulated (Count)
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simOps 27556226 # Number of ops (including micro ops) simulated (Count)
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hostInstRate 70588 # Simulator instruction rate (inst/s) ((Count/Second))
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hostOpRate 97257 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
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system.clk_domain.clock 1000 # Clock period in ticks (Tick)
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system.cpu.numCycles 419076069 # Number of cpu cycles simulated (Cycle)
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system.cpu.cpi 20.953803 # CPI: cycles per instruction (core level) ((Cycle/Count))
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system.cpu.ipc 0.047724 # IPC: instructions per cycle (core level) ((Count/Cycle))
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system.cpu.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
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system.cpu.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
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system.cpu.instsAdded 28083146 # Number of instructions added to the IQ (excludes non-spec) (Count)
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system.cpu.nonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ (Count)
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system.cpu.instsIssued 28082447 # Number of instructions issued (Count)
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system.cpu.squashedInstsIssued 295 # Number of squashed instructions issued (Count)
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system.cpu.squashedInstsExamined 526962 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
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system.cpu.squashedOperandsExamined 200093 # Number of squashed operands that are examined and possibly removed from graph (Count)
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system.cpu.squashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed (Count)
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system.cpu.numIssuedDist::samples 419020433 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::mean 0.067019 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::stdev 0.250055 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::0 390937986 93.30% 93.30% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::1 28082447 6.70% 100.00% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::max_value 1 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::total 419020433 # Number of insts issued each cycle (Count)
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system.cpu.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideStore 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorStridedLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorStridedStore 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIndexedLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIndexedStore 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorWholeRegisterLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorWholeRegisterStore 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIntegerArith 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorFloatArith 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorFloatConvert 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIntegerReduce 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorFloatReduce 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorMisc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIntegerExtension 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorConfig 0 # attempts to use FU when none available (Count)
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system.cpu.statIssuedInstType_0::No_OpClass 307 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::IntAlu 20452358 72.83% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::IntMult 45 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::IntDiv 58 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatAdd 148 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatCmp 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatCvt 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMult 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMultAcc 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatDiv 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMisc 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatSqrt 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAdd 10 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAddAcc 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAlu 239 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdCmp 4 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdCvt 76 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMisc 239 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMult 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMultAcc 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdShift 3 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdShiftAcc 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdDiv 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSqrt 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatAdd 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatAlu 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatCmp 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatCvt 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatDiv 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMisc 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMult 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdReduceAdd 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdReduceAlu 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdReduceCmp 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAes 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAesMix 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSha1Hash 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSha256Hash 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdShaSigma2 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdShaSigma3 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdPredAlu 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::Matrix 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::MatrixMov 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::MatrixOP 0 0.00% 72.83% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::MemRead 2552094 9.09% 81.92% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::MemWrite 5076204 18.08% 100.00% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMemRead 133 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMemWrite 529 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
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|
system.cpu.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
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|
system.cpu.statIssuedInstType_0::total 28082447 # Number of instructions issued per FU type, per thread (Count)
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|
system.cpu.issueRate 0.067010 # Inst issue rate ((Count/Cycle))
|
|
system.cpu.fuBusy 0 # FU busy when requested (Count)
|
|
system.cpu.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
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|
system.cpu.intInstQueueReads 475182523 # Number of integer instruction queue reads (Count)
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system.cpu.intInstQueueWrites 28608572 # Number of integer instruction queue writes (Count)
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|
system.cpu.intInstQueueWakeupAccesses 28031231 # Number of integer instruction queue wakeup accesses (Count)
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|
system.cpu.fpInstQueueReads 3098 # Number of floating instruction queue reads (Count)
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|
system.cpu.fpInstQueueWrites 1591 # Number of floating instruction queue writes (Count)
|
|
system.cpu.fpInstQueueWakeupAccesses 1529 # Number of floating instruction queue wakeup accesses (Count)
|
|
system.cpu.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
|
|
system.cpu.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
|
|
system.cpu.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
|
|
system.cpu.intAluAccesses 28080594 # Number of integer alu accesses (Count)
|
|
system.cpu.fpAluAccesses 1546 # Number of floating point alu accesses (Count)
|
|
system.cpu.vecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu.numSquashedInsts 389 # Number of squashed instructions skipped in execute (Count)
|
|
system.cpu.numSwp 0 # Number of swp insts executed (Count)
|
|
system.cpu.timesIdled 430 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
|
|
system.cpu.idleCycles 55636 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
|
|
system.cpu.MemDepUnit__0.insertedLoads 2552301 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__0.insertedStores 5076806 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__0.conflictingLoads 2486 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__0.conflictingStores 18 # Number of conflicting stores. (Count)
|
|
system.cpu.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu.branchPred.lookups 2615748 # Number of BP lookups (Count)
|
|
system.cpu.branchPred.condPredicted 2605420 # Number of conditional branches predicted (Count)
|
|
system.cpu.branchPred.condIncorrect 702 # Number of conditional branches incorrect (Count)
|
|
system.cpu.branchPred.BTBLookups 2591963 # Number of BTB lookups (Count)
|
|
system.cpu.branchPred.BTBUpdates 571 # Number of BTB updates (Count)
|
|
system.cpu.branchPred.BTBHits 2591659 # Number of BTB hits (Count)
|
|
system.cpu.branchPred.BTBHitRatio 0.999883 # BTB Hit Ratio (Ratio)
|
|
system.cpu.branchPred.RASUsed 2362 # Number of times the RAS was used to get a target. (Count)
|
|
system.cpu.branchPred.RASIncorrect 1 # Number of incorrect RAS predictions. (Count)
|
|
system.cpu.branchPred.indirectLookups 2211 # Number of indirect predictor lookups. (Count)
|
|
system.cpu.branchPred.indirectHits 2112 # Number of indirect target hits. (Count)
|
|
system.cpu.branchPred.indirectMisses 99 # Number of indirect misses. (Count)
|
|
system.cpu.branchPred.indirectMispredicted 60 # Number of mispredicted indirect branches. (Count)
|
|
system.cpu.branchPred.loop_predictor.correct 2504825 # Number of times the loop predictor is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.loop_predictor.wrong 1832 # Number of times the loop predictor is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.longestMatchProviderCorrect 393221 # Number of times TAGE Longest Match is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.tage.altMatchProviderCorrect 57 # Number of times TAGE Alt Match is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 36 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.tage.bimodalProviderCorrect 2112936 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct (Count)
|
|
system.cpu.branchPred.tage.longestMatchProviderWrong 62 # Number of times TAGE Longest Match is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.altMatchProviderWrong 19 # Number of times TAGE Alt Match is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 24 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.bimodalProviderWrong 302 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.altMatchProviderWouldHaveHit 21 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct (Count)
|
|
system.cpu.branchPred.tage.longestMatchProviderWouldHaveHit 31 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::0 0 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::1 387942 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::2 333 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::3 1540 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::4 2029 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::5 127 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::6 735 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::7 125 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::8 245 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::9 81 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::10 119 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::11 83 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::12 0 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::0 390333 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::1 291 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::2 1225 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::3 490 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::4 4 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::5 363 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::6 144 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::7 294 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::8 16 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::9 116 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::10 83 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::11 0 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::12 0 # TAGE provider for alt match (Count)
|
|
system.cpu.commit.commitSquashedInsts 526861 # The number of squashed insts skipped by commit (Count)
|
|
system.cpu.commit.commitNonSpecStalls 42 # The number of times commit has been forced to stall to communicate backwards (Count)
|
|
system.cpu.commit.branchMispredicts 489 # The number of times a branch was mispredicted (Count)
|
|
system.cpu.commit.numCommittedDist::samples 418954244 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::mean 0.065774 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::stdev 0.247886 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::0 391398018 93.42% 93.42% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::1 27556226 6.58% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::max_value 1 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::total 418954244 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.amos 0 # Number of atomic instructions committed (Count)
|
|
system.cpu.commit.membars 28 # Number of memory barriers committed (Count)
|
|
system.cpu.commit.functionCalls 2307 # Number of function calls committed. (Count)
|
|
system.cpu.commit.committedInstType_0::No_OpClass 250 0.00% 0.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IntAlu 20074104 72.85% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IntMult 41 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IntDiv 56 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatAdd 146 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAdd 10 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAlu 237 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdCmp 4 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdCvt 76 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMisc 235 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShift 3 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAes 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAesMix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::Matrix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MatrixMov 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MatrixOP 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MemRead 2502668 9.08% 81.93% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MemWrite 4977757 18.06% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMemRead 125 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::total 27556226 # Class of committed instruction (Count)
|
|
system.cpu.commit.commitEligibleSamples 27556226 # number cycles where commit BW limit reached (Cycle)
|
|
system.cpu.commitStats0.numInsts 20000000 # Number of instructions committed (thread level) (Count)
|
|
system.cpu.commitStats0.numOps 27556226 # Number of ops (including micro ops) committed (thread level) (Count)
|
|
system.cpu.commitStats0.numInstsNotNOP 20000000 # Number of instructions committed excluding NOPs or prefetches (Count)
|
|
system.cpu.commitStats0.numOpsNotNOP 27556226 # Number of Ops (including micro ops) Simulated (Count)
|
|
system.cpu.commitStats0.cpi 20.953803 # CPI: cycles per instruction (thread level) ((Cycle/Count))
|
|
system.cpu.commitStats0.ipc 0.047724 # IPC: instructions per cycle (thread level) ((Count/Cycle))
|
|
system.cpu.commitStats0.numMemRefs 7481064 # Number of memory references committed (Count)
|
|
system.cpu.commitStats0.numFpInsts 1513 # Number of float instructions (Count)
|
|
system.cpu.commitStats0.numIntInsts 27555088 # Number of integer instructions (Count)
|
|
system.cpu.commitStats0.numLoadInsts 2502793 # Number of load instructions (Count)
|
|
system.cpu.commitStats0.numStoreInsts 4978271 # Number of store instructions (Count)
|
|
system.cpu.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
|
|
system.cpu.commitStats0.committedInstType::No_OpClass 250 0.00% 0.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IntAlu 20074104 72.85% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IntMult 41 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IntDiv 56 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatAdd 146 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAdd 10 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAlu 237 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdCmp 4 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdCvt 76 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMisc 235 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShift 3 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAes 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::Matrix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MatrixMov 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MatrixOP 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MemRead 2502668 9.08% 81.93% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MemWrite 4977757 18.06% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMemRead 125 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::total 27556226 # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedControl::IsControl 2516676 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsDirectControl 2512216 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsIndirectControl 4460 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsCondControl 2506658 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsUncondControl 10018 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsCall 2307 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsReturn 2304 # Class of control type instructions committed (Count)
|
|
system.cpu.dcache.demandHits::cpu.data 2510846 # number of demand (read+write) hits (Count)
|
|
system.cpu.dcache.demandHits::total 2510846 # number of demand (read+write) hits (Count)
|
|
system.cpu.dcache.overallHits::cpu.data 2510846 # number of overall hits (Count)
|
|
system.cpu.dcache.overallHits::total 2510846 # number of overall hits (Count)
|
|
system.cpu.dcache.demandMisses::cpu.data 2485341 # number of demand (read+write) misses (Count)
|
|
system.cpu.dcache.demandMisses::total 2485341 # number of demand (read+write) misses (Count)
|
|
system.cpu.dcache.overallMisses::cpu.data 2485341 # number of overall misses (Count)
|
|
system.cpu.dcache.overallMisses::total 2485341 # number of overall misses (Count)
|
|
system.cpu.dcache.demandMissLatency::cpu.data 206718475500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.dcache.demandMissLatency::total 206718475500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.dcache.overallMissLatency::cpu.data 206718475500 # number of overall miss ticks (Tick)
|
|
system.cpu.dcache.overallMissLatency::total 206718475500 # number of overall miss ticks (Tick)
|
|
system.cpu.dcache.demandAccesses::cpu.data 4996187 # number of demand (read+write) accesses (Count)
|
|
system.cpu.dcache.demandAccesses::total 4996187 # number of demand (read+write) accesses (Count)
|
|
system.cpu.dcache.overallAccesses::cpu.data 4996187 # number of overall (read+write) accesses (Count)
|
|
system.cpu.dcache.overallAccesses::total 4996187 # number of overall (read+write) accesses (Count)
|
|
system.cpu.dcache.demandMissRate::cpu.data 0.497448 # miss rate for demand accesses (Ratio)
|
|
system.cpu.dcache.demandMissRate::total 0.497448 # miss rate for demand accesses (Ratio)
|
|
system.cpu.dcache.overallMissRate::cpu.data 0.497448 # miss rate for overall accesses (Ratio)
|
|
system.cpu.dcache.overallMissRate::total 0.497448 # miss rate for overall accesses (Ratio)
|
|
system.cpu.dcache.demandAvgMissLatency::cpu.data 83175.095691 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.dcache.demandAvgMissLatency::total 83175.095691 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMissLatency::cpu.data 83175.095691 # average overall miss latency ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMissLatency::total 83175.095691 # average overall miss latency ((Tick/Count))
|
|
system.cpu.dcache.blockedCycles::no_mshrs 184 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dcache.blockedCauses::no_mshrs 1 # number of times access was blocked (Count)
|
|
system.cpu.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.dcache.avgBlocked::no_mshrs 184 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dcache.writebacks::writebacks 2483103 # number of writebacks (Count)
|
|
system.cpu.dcache.writebacks::total 2483103 # number of writebacks (Count)
|
|
system.cpu.dcache.demandMshrHits::cpu.data 516 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.dcache.demandMshrHits::total 516 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.dcache.overallMshrHits::cpu.data 516 # number of overall MSHR hits (Count)
|
|
system.cpu.dcache.overallMshrHits::total 516 # number of overall MSHR hits (Count)
|
|
system.cpu.dcache.demandMshrMisses::cpu.data 2484825 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.dcache.demandMshrMisses::total 2484825 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.dcache.overallMshrMisses::cpu.data 2484825 # number of overall MSHR misses (Count)
|
|
system.cpu.dcache.overallMshrMisses::total 2484825 # number of overall MSHR misses (Count)
|
|
system.cpu.dcache.demandMshrMissLatency::cpu.data 204194408500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.dcache.demandMshrMissLatency::total 204194408500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.dcache.overallMshrMissLatency::cpu.data 204194408500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.dcache.overallMshrMissLatency::total 204194408500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.dcache.demandMshrMissRate::cpu.data 0.497344 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.dcache.demandMshrMissRate::total 0.497344 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.dcache.overallMshrMissRate::cpu.data 0.497344 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.dcache.overallMshrMissRate::total 0.497344 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.dcache.demandAvgMshrMissLatency::cpu.data 82176.575212 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.demandAvgMshrMissLatency::total 82176.575212 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMshrMissLatency::cpu.data 82176.575212 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMshrMissLatency::total 82176.575212 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.replacements 2483800 # number of replacements (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.hits::cpu.data 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.hits::total 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.misses::cpu.data 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.misses::total 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.missLatency::cpu.data 86000 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.missLatency::total 86000 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.accesses::cpu.data 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.accesses::total 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.missRate::cpu.data 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.missRate::total 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::cpu.data 86000 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::total 86000 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMisses::cpu.data 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMisses::total 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::cpu.data 226000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::total 226000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::cpu.data 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::total 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu.data 226000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::total 226000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWWriteReq.hits::cpu.data 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu.dcache.LockedRMWWriteReq.hits::total 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu.dcache.LockedRMWWriteReq.accesses::cpu.data 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.LockedRMWWriteReq.accesses::total 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.ReadReq.hits::cpu.data 16706 # number of ReadReq hits (Count)
|
|
system.cpu.dcache.ReadReq.hits::total 16706 # number of ReadReq hits (Count)
|
|
system.cpu.dcache.ReadReq.misses::cpu.data 1239 # number of ReadReq misses (Count)
|
|
system.cpu.dcache.ReadReq.misses::total 1239 # number of ReadReq misses (Count)
|
|
system.cpu.dcache.ReadReq.missLatency::cpu.data 95730000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.missLatency::total 95730000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.accesses::cpu.data 17945 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.ReadReq.accesses::total 17945 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.ReadReq.missRate::cpu.data 0.069044 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.missRate::total 0.069044 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.avgMissLatency::cpu.data 77263.922518 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.ReadReq.avgMissLatency::total 77263.922518 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.ReadReq.mshrHits::cpu.data 516 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.dcache.ReadReq.mshrHits::total 516 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.dcache.ReadReq.mshrMisses::cpu.data 723 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.dcache.ReadReq.mshrMisses::total 723 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.dcache.ReadReq.mshrMissLatency::cpu.data 55764000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.mshrMissLatency::total 55764000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.mshrMissRate::cpu.data 0.040290 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.mshrMissRate::total 0.040290 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.avgMshrMissLatency::cpu.data 77128.630705 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.ReadReq.avgMshrMissLatency::total 77128.630705 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.hits::cpu.data 2494140 # number of WriteReq hits (Count)
|
|
system.cpu.dcache.WriteReq.hits::total 2494140 # number of WriteReq hits (Count)
|
|
system.cpu.dcache.WriteReq.misses::cpu.data 2484102 # number of WriteReq misses (Count)
|
|
system.cpu.dcache.WriteReq.misses::total 2484102 # number of WriteReq misses (Count)
|
|
system.cpu.dcache.WriteReq.missLatency::cpu.data 206622745500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.missLatency::total 206622745500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.accesses::cpu.data 4978242 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.WriteReq.accesses::total 4978242 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.WriteReq.missRate::cpu.data 0.498992 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.missRate::total 0.498992 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.avgMissLatency::cpu.data 83178.044018 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.avgMissLatency::total 83178.044018 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.mshrMisses::cpu.data 2484102 # number of WriteReq MSHR misses (Count)
|
|
system.cpu.dcache.WriteReq.mshrMisses::total 2484102 # number of WriteReq MSHR misses (Count)
|
|
system.cpu.dcache.WriteReq.mshrMissLatency::cpu.data 204138644500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.mshrMissLatency::total 204138644500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.mshrMissRate::cpu.data 0.498992 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.mshrMissRate::total 0.498992 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.avgMshrMissLatency::cpu.data 82178.044420 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.avgMshrMissLatency::total 82178.044420 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.dcache.tags.tagsInUse 1023.415663 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.dcache.tags.totalRefs 4995698 # Total number of references to valid blocks. (Count)
|
|
system.cpu.dcache.tags.sampledRefs 2484824 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.dcache.tags.avgRefs 2.010484 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.dcache.tags.warmupTick 178500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.dcache.tags.occupancies::cpu.data 1023.415663 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu.dcache.tags.avgOccs::cpu.data 0.999429 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.dcache.tags.avgOccs::total 0.999429 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.dcache.tags.occupanciesTaskId::1024 1024 # Occupied blocks per task id (Count)
|
|
system.cpu.dcache.tags.ageTaskId_1024::0 117 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.dcache.tags.ageTaskId_1024::1 906 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.dcache.tags.ageTaskId_1024::4 1 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu.dcache.tags.tagAccesses 12477254 # Number of tag accesses (Count)
|
|
system.cpu.dcache.tags.dataAccesses 12477254 # Number of data accesses (Count)
|
|
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.decode.idleCycles 2457925 # Number of cycles decode is idle (Cycle)
|
|
system.cpu.decode.blockedCycles 388444635 # Number of cycles decode is blocked (Cycle)
|
|
system.cpu.decode.runCycles 23262464 # Number of cycles decode is running (Cycle)
|
|
system.cpu.decode.unblockCycles 4838509 # Number of cycles decode is unblocking (Cycle)
|
|
system.cpu.decode.squashCycles 16900 # Number of cycles decode is squashing (Cycle)
|
|
system.cpu.decode.branchResolved 2542634 # Number of times decode resolved a branch (Count)
|
|
system.cpu.decode.branchMispred 235 # Number of times decode detected a branch misprediction (Count)
|
|
system.cpu.decode.decodedInsts 28100764 # Number of instructions handled by decode (Count)
|
|
system.cpu.decode.squashedInsts 209 # Number of squashed instructions handled by decode (Count)
|
|
system.cpu.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dtb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.executeStats0.numInsts 28082057 # Number of executed instructions (Count)
|
|
system.cpu.executeStats0.numNop 0 # Number of nop insts executed (Count)
|
|
system.cpu.executeStats0.numBranches 2565924 # Number of branches executed (Count)
|
|
system.cpu.executeStats0.numLoadInsts 2552158 # Number of load instructions executed (Count)
|
|
system.cpu.executeStats0.numStoreInsts 5076716 # Number of stores executed (Count)
|
|
system.cpu.executeStats0.instRate 0.067009 # Inst execution rate ((Count/Cycle))
|
|
system.cpu.executeStats0.numCCRegReads 12820424 # Number of times the CC registers were read (Count)
|
|
system.cpu.executeStats0.numCCRegWrites 15279122 # Number of times the CC registers were written (Count)
|
|
system.cpu.executeStats0.numFpRegReads 1868 # Number of times the floating registers were read (Count)
|
|
system.cpu.executeStats0.numFpRegWrites 937 # Number of times the floating registers were written (Count)
|
|
system.cpu.executeStats0.numIntRegReads 45887803 # Number of times the integer registers were read (Count)
|
|
system.cpu.executeStats0.numIntRegWrites 17881446 # Number of times the integer registers were written (Count)
|
|
system.cpu.executeStats0.numMemRefs 7628874 # Number of memory refs (Count)
|
|
system.cpu.executeStats0.numMiscRegReads 12758752 # Number of times the Misc registers were read (Count)
|
|
system.cpu.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
|
|
system.cpu.fetch.predictedBranches 2596133 # Number of branches that fetch has predicted taken (Count)
|
|
system.cpu.fetch.cycles 418967994 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
|
|
system.cpu.fetch.squashCycles 34260 # Number of cycles fetch has spent squashing (Cycle)
|
|
system.cpu.fetch.miscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
|
|
system.cpu.fetch.pendingTrapStallCycles 107 # Number of stall cycles due to pending traps (Cycle)
|
|
system.cpu.fetch.cacheLines 17861 # Number of cache lines fetched (Count)
|
|
system.cpu.fetch.icacheSquashes 161 # Number of outstanding Icache misses that were squashed (Count)
|
|
system.cpu.fetch.nisnDist::samples 419020433 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::mean 0.068400 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::stdev 0.252431 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::0 390359333 93.16% 93.16% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::1 28661100 6.84% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::max_value 1 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::total 419020433 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetchStats0.numInsts 20806883 # Number of instructions fetched (thread level) (Count)
|
|
system.cpu.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
|
|
system.cpu.fetchStats0.fetchRate 0.049649 # Number of inst fetches per cycle ((Count/Cycle))
|
|
system.cpu.fetchStats0.numBranches 2615748 # Number of branches fetched (Count)
|
|
system.cpu.fetchStats0.branchRate 0.006242 # Number of branch fetches per cycle (Ratio)
|
|
system.cpu.fetchStats0.icacheStallCycles 35184 # ICache total stall cycles (Cycle)
|
|
system.cpu.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
|
|
system.cpu.icache.demandHits::cpu.inst 17299 # number of demand (read+write) hits (Count)
|
|
system.cpu.icache.demandHits::total 17299 # number of demand (read+write) hits (Count)
|
|
system.cpu.icache.overallHits::cpu.inst 17299 # number of overall hits (Count)
|
|
system.cpu.icache.overallHits::total 17299 # number of overall hits (Count)
|
|
system.cpu.icache.demandMisses::cpu.inst 562 # number of demand (read+write) misses (Count)
|
|
system.cpu.icache.demandMisses::total 562 # number of demand (read+write) misses (Count)
|
|
system.cpu.icache.overallMisses::cpu.inst 562 # number of overall misses (Count)
|
|
system.cpu.icache.overallMisses::total 562 # number of overall misses (Count)
|
|
system.cpu.icache.demandMissLatency::cpu.inst 43706000 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.icache.demandMissLatency::total 43706000 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.icache.overallMissLatency::cpu.inst 43706000 # number of overall miss ticks (Tick)
|
|
system.cpu.icache.overallMissLatency::total 43706000 # number of overall miss ticks (Tick)
|
|
system.cpu.icache.demandAccesses::cpu.inst 17861 # number of demand (read+write) accesses (Count)
|
|
system.cpu.icache.demandAccesses::total 17861 # number of demand (read+write) accesses (Count)
|
|
system.cpu.icache.overallAccesses::cpu.inst 17861 # number of overall (read+write) accesses (Count)
|
|
system.cpu.icache.overallAccesses::total 17861 # number of overall (read+write) accesses (Count)
|
|
system.cpu.icache.demandMissRate::cpu.inst 0.031465 # miss rate for demand accesses (Ratio)
|
|
system.cpu.icache.demandMissRate::total 0.031465 # miss rate for demand accesses (Ratio)
|
|
system.cpu.icache.overallMissRate::cpu.inst 0.031465 # miss rate for overall accesses (Ratio)
|
|
system.cpu.icache.overallMissRate::total 0.031465 # miss rate for overall accesses (Ratio)
|
|
system.cpu.icache.demandAvgMissLatency::cpu.inst 77768.683274 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.icache.demandAvgMissLatency::total 77768.683274 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.icache.overallAvgMissLatency::cpu.inst 77768.683274 # average overall miss latency ((Tick/Count))
|
|
system.cpu.icache.overallAvgMissLatency::total 77768.683274 # average overall miss latency ((Tick/Count))
|
|
system.cpu.icache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.icache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu.icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.icache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.icache.writebacks::writebacks 128 # number of writebacks (Count)
|
|
system.cpu.icache.writebacks::total 128 # number of writebacks (Count)
|
|
system.cpu.icache.demandMshrHits::cpu.inst 42 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.icache.demandMshrHits::total 42 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.icache.overallMshrHits::cpu.inst 42 # number of overall MSHR hits (Count)
|
|
system.cpu.icache.overallMshrHits::total 42 # number of overall MSHR hits (Count)
|
|
system.cpu.icache.demandMshrMisses::cpu.inst 520 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.icache.demandMshrMisses::total 520 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.icache.overallMshrMisses::cpu.inst 520 # number of overall MSHR misses (Count)
|
|
system.cpu.icache.overallMshrMisses::total 520 # number of overall MSHR misses (Count)
|
|
system.cpu.icache.demandMshrMissLatency::cpu.inst 40837500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.icache.demandMshrMissLatency::total 40837500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.icache.overallMshrMissLatency::cpu.inst 40837500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.icache.overallMshrMissLatency::total 40837500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.icache.demandMshrMissRate::cpu.inst 0.029114 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.icache.demandMshrMissRate::total 0.029114 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.icache.overallMshrMissRate::cpu.inst 0.029114 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.icache.overallMshrMissRate::total 0.029114 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.icache.demandAvgMshrMissLatency::cpu.inst 78533.653846 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.demandAvgMshrMissLatency::total 78533.653846 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.overallAvgMshrMissLatency::cpu.inst 78533.653846 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.overallAvgMshrMissLatency::total 78533.653846 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.replacements 128 # number of replacements (Count)
|
|
system.cpu.icache.ReadReq.hits::cpu.inst 17299 # number of ReadReq hits (Count)
|
|
system.cpu.icache.ReadReq.hits::total 17299 # number of ReadReq hits (Count)
|
|
system.cpu.icache.ReadReq.misses::cpu.inst 562 # number of ReadReq misses (Count)
|
|
system.cpu.icache.ReadReq.misses::total 562 # number of ReadReq misses (Count)
|
|
system.cpu.icache.ReadReq.missLatency::cpu.inst 43706000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.missLatency::total 43706000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.accesses::cpu.inst 17861 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.icache.ReadReq.accesses::total 17861 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.icache.ReadReq.missRate::cpu.inst 0.031465 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.missRate::total 0.031465 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.avgMissLatency::cpu.inst 77768.683274 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.icache.ReadReq.avgMissLatency::total 77768.683274 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.icache.ReadReq.mshrHits::cpu.inst 42 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.icache.ReadReq.mshrHits::total 42 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.icache.ReadReq.mshrMisses::cpu.inst 520 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.icache.ReadReq.mshrMisses::total 520 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.icache.ReadReq.mshrMissLatency::cpu.inst 40837500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.mshrMissLatency::total 40837500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.mshrMissRate::cpu.inst 0.029114 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.mshrMissRate::total 0.029114 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.avgMshrMissLatency::cpu.inst 78533.653846 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.ReadReq.avgMshrMissLatency::total 78533.653846 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.icache.tags.tagsInUse 390.939856 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.icache.tags.totalRefs 17819 # Total number of references to valid blocks. (Count)
|
|
system.cpu.icache.tags.sampledRefs 520 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.icache.tags.avgRefs 34.267308 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.icache.tags.warmupTick 87500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.icache.tags.occupancies::cpu.inst 390.939856 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu.icache.tags.avgOccs::cpu.inst 0.763554 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.icache.tags.avgOccs::total 0.763554 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.icache.tags.occupanciesTaskId::1024 391 # Occupied blocks per task id (Count)
|
|
system.cpu.icache.tags.ageTaskId_1024::4 391 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.icache.tags.ratioOccsTaskId::1024 0.763672 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu.icache.tags.tagAccesses 36242 # Number of tag accesses (Count)
|
|
system.cpu.icache.tags.dataAccesses 36242 # Number of data accesses (Count)
|
|
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
|
|
system.cpu.iew.squashCycles 16900 # Number of cycles IEW is squashing (Cycle)
|
|
system.cpu.iew.blockCycles 61638 # Number of cycles IEW is blocking (Cycle)
|
|
system.cpu.iew.unblockCycles 69 # Number of cycles IEW is unblocking (Cycle)
|
|
system.cpu.iew.dispatchedInsts 28083191 # Number of instructions dispatched to IQ (Count)
|
|
system.cpu.iew.dispSquashedInsts 354 # Number of squashed instructions skipped by dispatch (Count)
|
|
system.cpu.iew.dispLoadInsts 2552301 # Number of dispatched load instructions (Count)
|
|
system.cpu.iew.dispStoreInsts 5076806 # Number of dispatched store instructions (Count)
|
|
system.cpu.iew.dispNonSpecInsts 15 # Number of dispatched non-speculative instructions (Count)
|
|
system.cpu.iew.iqFullEvents 4 # Number of times the IQ has become full, causing a stall (Count)
|
|
system.cpu.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
|
|
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations (Count)
|
|
system.cpu.iew.predictedTakenIncorrect 74 # Number of branches that were predicted taken incorrectly (Count)
|
|
system.cpu.iew.predictedNotTakenIncorrect 419 # Number of branches that were predicted not taken incorrectly (Count)
|
|
system.cpu.iew.branchMispredicts 493 # Number of branch mispredicts detected at execute (Count)
|
|
system.cpu.iew.instsToCommit 28081978 # Cumulative count of insts sent to commit (Count)
|
|
system.cpu.iew.writebackCount 28032760 # Cumulative count of insts written-back (Count)
|
|
system.cpu.iew.producerInst 7733338 # Number of instructions producing a value (Count)
|
|
system.cpu.iew.consumerInst 7795685 # Number of instructions consuming a value (Count)
|
|
system.cpu.iew.wbRate 0.066892 # Insts written-back per cycle ((Count/Cycle))
|
|
system.cpu.iew.wbFanout 0.992002 # Average fanout of values written-back ((Count/Count))
|
|
system.cpu.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
|
|
system.cpu.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.itb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.lsq0.forwLoads 2534185 # Number of loads that had data forwarded from stores (Count)
|
|
system.cpu.lsq0.squashedLoads 49507 # Number of loads squashed (Count)
|
|
system.cpu.lsq0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed (Count)
|
|
system.cpu.lsq0.memOrderViolation 10 # Number of memory ordering violations (Count)
|
|
system.cpu.lsq0.squashedStores 98535 # Number of stores squashed (Count)
|
|
system.cpu.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
|
|
system.cpu.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
|
|
system.cpu.lsq0.loadToUse::samples 2502793 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::mean 2.080026 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::stdev 3.595430 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::0-9 2501601 99.95% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::20-29 3 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::30-39 1 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::110-119 1 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::120-129 5 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::130-139 7 0.00% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::140-149 1018 0.04% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::150-159 13 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::160-169 7 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::170-179 69 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::190-199 4 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::200-209 31 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::210-219 5 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::240-249 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::280-289 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::290-299 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::overflows 22 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::max_value 688 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::total 2502793 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.mmu.dtb.rdAccesses 2552161 # TLB accesses on read requests (Count)
|
|
system.cpu.mmu.dtb.wrAccesses 5076716 # TLB accesses on write requests (Count)
|
|
system.cpu.mmu.dtb.rdMisses 40 # TLB misses on read requests (Count)
|
|
system.cpu.mmu.dtb.wrMisses 87978 # TLB misses on write requests (Count)
|
|
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
|
|
system.cpu.mmu.itb.wrAccesses 17879 # TLB accesses on write requests (Count)
|
|
system.cpu.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
|
|
system.cpu.mmu.itb.wrMisses 60 # TLB misses on write requests (Count)
|
|
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.power_state.pwrStateResidencyTicks::ON 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.rename.squashCycles 16900 # Number of cycles rename is squashing (Cycle)
|
|
system.cpu.rename.idleCycles 4877693 # Number of cycles rename is idle (Cycle)
|
|
system.cpu.rename.blockCycles 17090658 # Number of cycles rename is blocking (Cycle)
|
|
system.cpu.rename.serializeStallCycles 464 # count of cycles rename stalled for serializing inst (Cycle)
|
|
system.cpu.rename.runCycles 25663975 # Number of cycles rename is running (Cycle)
|
|
system.cpu.rename.unblockCycles 371370743 # Number of cycles rename is unblocking (Cycle)
|
|
system.cpu.rename.renamedInsts 28083994 # Number of instructions processed by rename (Count)
|
|
system.cpu.rename.ROBFullEvents 16890 # Number of times rename has blocked due to ROB full (Count)
|
|
system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full (Count)
|
|
system.cpu.rename.SQFullEvents 368950693 # Number of times rename has blocked due to SQ full (Count)
|
|
system.cpu.rename.renamedOperands 58641319 # Number of destination operands rename has renamed (Count)
|
|
system.cpu.rename.lookups 114770176 # Number of register rename lookups that rename has made (Count)
|
|
system.cpu.rename.intLookups 45890535 # Number of integer rename lookups (Count)
|
|
system.cpu.rename.fpLookups 1898 # Number of floating rename lookups (Count)
|
|
system.cpu.rename.committedMaps 57521754 # Number of HB maps that are committed (Count)
|
|
system.cpu.rename.undoneMaps 1119562 # Number of HB maps that are undone due to squashing (Count)
|
|
system.cpu.rename.serializing 31 # count of serializing insts renamed (Count)
|
|
system.cpu.rename.tempSerializing 31 # count of temporary serializing insts renamed (Count)
|
|
system.cpu.rename.skidInsts 4838525 # count of insts added to the skid buffer (Count)
|
|
system.cpu.rob.reads 419267879 # The number of ROB reads (Count)
|
|
system.cpu.rob.writes 56232365 # The number of ROB writes (Count)
|
|
system.cpu.thread_0.numInsts 20000000 # Number of Instructions committed (Count)
|
|
system.cpu.thread_0.numOps 27556226 # Number of Ops committed (Count)
|
|
system.cpu.thread_0.numMemRefs 0 # Number of Memory References (Count)
|
|
system.cpu.workload.numSyscalls 14 # Number of system calls (Count)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks (Tick)
|
|
system.cpu_voltage_domain.voltage 1 # Voltage in Volts (Volt)
|
|
system.l2.demandHits::cpu.inst 8 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu.data 5 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::total 13 # number of demand (read+write) hits (Count)
|
|
system.l2.overallHits::cpu.inst 8 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu.data 5 # number of overall hits (Count)
|
|
system.l2.overallHits::total 13 # number of overall hits (Count)
|
|
system.l2.demandMisses::cpu.inst 511 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu.data 2484820 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::total 2485331 # number of demand (read+write) misses (Count)
|
|
system.l2.overallMisses::cpu.inst 511 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu.data 2484820 # number of overall misses (Count)
|
|
system.l2.overallMisses::total 2485331 # number of overall misses (Count)
|
|
system.l2.demandMissLatency::cpu.inst 39969000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu.data 200467192000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::total 200507161000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu.inst 39969000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu.data 200467192000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::total 200507161000 # number of overall miss ticks (Tick)
|
|
system.l2.demandAccesses::cpu.inst 519 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu.data 2484825 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::total 2485344 # number of demand (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu.inst 519 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu.data 2484825 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::total 2485344 # number of overall (read+write) accesses (Count)
|
|
system.l2.demandMissRate::cpu.inst 0.984586 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu.data 0.999998 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::total 0.999995 # miss rate for demand accesses (Ratio)
|
|
system.l2.overallMissRate::cpu.inst 0.984586 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu.data 0.999998 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::total 0.999995 # miss rate for overall accesses (Ratio)
|
|
system.l2.demandAvgMissLatency::cpu.inst 78217.221135 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu.data 80676.746002 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::total 80676.240308 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu.inst 78217.221135 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu.data 80676.746002 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::total 80676.240308 # average overall miss latency ((Tick/Count))
|
|
system.l2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.l2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.l2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.l2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.l2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.l2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.l2.writebacks::writebacks 2451353 # number of writebacks (Count)
|
|
system.l2.writebacks::total 2451353 # number of writebacks (Count)
|
|
system.l2.demandMshrMisses::cpu.inst 511 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu.data 2484820 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::total 2485331 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu.inst 511 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu.data 2484820 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::total 2485331 # number of overall MSHR misses (Count)
|
|
system.l2.demandMshrMissLatency::cpu.inst 34859000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu.data 175619002000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::total 175653861000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu.inst 34859000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu.data 175619002000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::total 175653861000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissRate::cpu.inst 0.984586 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu.data 0.999998 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::total 0.999995 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu.inst 0.984586 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu.data 0.999998 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::total 0.999995 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.demandAvgMshrMissLatency::cpu.inst 68217.221135 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu.data 70676.750026 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::total 70676.244331 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu.inst 68217.221135 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu.data 70676.750026 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::total 70676.244331 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.replacements 2452563 # number of replacements (Count)
|
|
system.l2.ReadCleanReq.hits::cpu.inst 8 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.hits::total 8 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.misses::cpu.inst 511 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.misses::total 511 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.missLatency::cpu.inst 39969000 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.missLatency::total 39969000 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.accesses::cpu.inst 519 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.accesses::total 519 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.missRate::cpu.inst 0.984586 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.missRate::total 0.984586 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.avgMissLatency::cpu.inst 78217.221135 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMissLatency::total 78217.221135 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.mshrMisses::cpu.inst 511 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMisses::total 511 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMissLatency::cpu.inst 34859000 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissLatency::total 34859000 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissRate::cpu.inst 0.984586 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.mshrMissRate::total 0.984586 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::cpu.inst 68217.221135 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::total 68217.221135 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.hits::cpu.data 2 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.hits::total 2 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.misses::cpu.data 2484100 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.misses::total 2484100 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.missLatency::cpu.data 200412544000 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.missLatency::total 200412544000 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.accesses::cpu.data 2484102 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.accesses::total 2484102 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.missRate::cpu.data 0.999999 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.missRate::total 0.999999 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.avgMissLatency::cpu.data 80678.130510 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMissLatency::total 80678.130510 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.mshrMisses::cpu.data 2484100 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMisses::total 2484100 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMissLatency::cpu.data 175571554000 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissLatency::total 175571554000 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissRate::cpu.data 0.999999 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.mshrMissRate::total 0.999999 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.avgMshrMissLatency::cpu.data 70678.134536 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMshrMissLatency::total 70678.134536 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.hits::cpu.data 3 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.hits::total 3 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.misses::cpu.data 720 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.misses::total 720 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.missLatency::cpu.data 54648000 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.missLatency::total 54648000 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.accesses::cpu.data 723 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.accesses::total 723 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.missRate::cpu.data 0.995851 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.missRate::total 0.995851 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.avgMissLatency::cpu.data 75900 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMissLatency::total 75900 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.mshrMisses::cpu.data 720 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMisses::total 720 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMissLatency::cpu.data 47448000 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissLatency::total 47448000 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissRate::cpu.data 0.995851 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.mshrMissRate::total 0.995851 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::cpu.data 65900 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::total 65900 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.UpgradeReq.hits::cpu.data 1 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.hits::total 1 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.UpgradeReq.accesses::total 1 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.WritebackClean.hits::writebacks 128 # number of WritebackClean hits (Count)
|
|
system.l2.WritebackClean.hits::total 128 # number of WritebackClean hits (Count)
|
|
system.l2.WritebackClean.accesses::writebacks 128 # number of WritebackClean accesses(hits+misses) (Count)
|
|
system.l2.WritebackClean.accesses::total 128 # number of WritebackClean accesses(hits+misses) (Count)
|
|
system.l2.WritebackDirty.hits::writebacks 2483103 # number of WritebackDirty hits (Count)
|
|
system.l2.WritebackDirty.hits::total 2483103 # number of WritebackDirty hits (Count)
|
|
system.l2.WritebackDirty.accesses::writebacks 2483103 # number of WritebackDirty accesses(hits+misses) (Count)
|
|
system.l2.WritebackDirty.accesses::total 2483103 # number of WritebackDirty accesses(hits+misses) (Count)
|
|
system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.l2.tags.tagsInUse 32556.180373 # Average ticks per tags in use ((Tick/Count))
|
|
system.l2.tags.totalRefs 4969272 # Total number of references to valid blocks. (Count)
|
|
system.l2.tags.sampledRefs 2485331 # Sample count of references to valid blocks. (Count)
|
|
system.l2.tags.avgRefs 1.999441 # Average number of references to valid blocks. ((Count/Count))
|
|
system.l2.tags.warmupTick 77000 # The tick when the warmup percentage was hit. (Tick)
|
|
system.l2.tags.occupancies::writebacks 0.012004 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu.inst 5.874483 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu.data 32550.293885 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.avgOccs::writebacks 0.000000 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu.inst 0.000179 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu.data 0.993356 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::total 0.993536 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.occupanciesTaskId::1024 32768 # Occupied blocks per task id (Count)
|
|
system.l2.tags.ageTaskId_1024::0 117 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::1 1069 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::2 10685 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::3 20897 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.l2.tags.tagAccesses 42239515 # Number of tag accesses (Count)
|
|
system.l2.tags.dataAccesses 42239515 # Number of data accesses (Count)
|
|
system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.mem_ctrls.avgPriority_writebacks::samples 2451353.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu.inst::samples 511.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu.data::samples 2484819.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (Second)
|
|
system.mem_ctrls.priorityMaxLatency 0.000071218500 # per QoS priority maximum request to response latency (Second)
|
|
system.mem_ctrls.numReadWriteTurnArounds 153207 # Number of turnarounds from READ to WRITE (Count)
|
|
system.mem_ctrls.numWriteReadTurnArounds 153207 # Number of turnarounds from WRITE to READ (Count)
|
|
system.mem_ctrls.numStayReadState 7319327 # Number of times bus staying in READ state (Count)
|
|
system.mem_ctrls.numStayWriteState 2299770 # Number of times bus staying in WRITE state (Count)
|
|
system.mem_ctrls.readReqs 2485330 # Number of read requests accepted (Count)
|
|
system.mem_ctrls.writeReqs 2451353 # Number of write requests accepted (Count)
|
|
system.mem_ctrls.readBursts 2485330 # Number of controller read bursts, including those serviced by the write queue (Count)
|
|
system.mem_ctrls.writeBursts 2451353 # Number of controller write bursts, including those merged in the write queue (Count)
|
|
system.mem_ctrls.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
|
|
system.mem_ctrls.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
|
|
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
|
|
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing ((Count/Tick))
|
|
system.mem_ctrls.avgWrQLen 25.91 # Average write queue length when enqueuing ((Count/Tick))
|
|
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry (Count)
|
|
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry (Count)
|
|
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::6 2485330 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::6 2451353 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.rdQLenPdf::0 2485155 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::1 150 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::2 22 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::3 2 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::4 1 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::17 151444 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::18 153208 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::19 153209 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::20 153209 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::21 153213 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::22 153208 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::23 153208 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::24 153208 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::25 154970 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::26 153208 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::27 153207 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::28 153207 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::29 153207 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::30 153207 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::31 153207 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::32 153207 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdPerTurnAround::samples 153207 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::mean 16.221981 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::gmean 16.001361 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::stdev 85.098583 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::0-2047 153206 100.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::total 153207 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.wrPerTurnAround::samples 153207 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::mean 16.000098 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::gmean 16.000090 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::stdev 0.016359 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::16 153201 100.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::17 1 0.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::18 1 0.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::19 4 0.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::total 153207 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
|
|
system.mem_ctrls.bytesReadSys 159061120 # Total read bytes from the system interface side (Byte)
|
|
system.mem_ctrls.bytesWrittenSys 156886592 # Total written bytes from the system interface side (Byte)
|
|
system.mem_ctrls.avgRdBWSys 759103810.24191523 # Average system read bandwidth in Byte/s ((Byte/Second))
|
|
system.mem_ctrls.avgWrBWSys 748726085.69000888 # Average system write bandwidth in Byte/s ((Byte/Second))
|
|
system.mem_ctrls.totGap 209538013500 # Total gap between requests (Tick)
|
|
system.mem_ctrls.avgGap 42445.10 # Average gap between requests ((Tick/Count))
|
|
system.mem_ctrls.requestorReadBytes::cpu.inst 32704 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu.data 159028416 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorWriteBytes::writebacks 156884928 # Per-requestor bytes write to memory (Byte)
|
|
system.mem_ctrls.requestorReadRate::cpu.inst 156076.676752631931 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu.data 758947733.565162658691 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorWriteRate::writebacks 748718144.410956859589 # Per-requestor bytes write to memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadAccesses::cpu.inst 511 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu.data 2484819 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorWriteAccesses::writebacks 2451353 # Per-requestor write serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu.inst 13839750 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu.data 74331957250 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorWriteTotalLat::writebacks 5100322824500 # Per-requestor write total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadAvgLat::cpu.inst 27083.66 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu.data 29914.44 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorWriteAvgLat::writebacks 2080615.41 # Per-requestor write average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.dram.bytesRead::cpu.inst 32704 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu.data 159028416 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::total 159061120 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::cpu.inst 32704 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::total 32704 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesWritten::writebacks 156886592 # Number of bytes written to this memory (Byte)
|
|
system.mem_ctrls.dram.bytesWritten::total 156886592 # Number of bytes written to this memory (Byte)
|
|
system.mem_ctrls.dram.numReads::cpu.inst 511 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu.data 2484819 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::total 2485330 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numWrites::writebacks 2451353 # Number of write requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numWrites::total 2451353 # Number of write requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.bwRead::cpu.inst 156077 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu.data 758947734 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::total 759103810 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::cpu.inst 156077 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::total 156077 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwWrite::writebacks 748726086 # Write bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwWrite::total 748726086 # Write bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::writebacks 748726086 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu.inst 156077 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu.data 758947734 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::total 1507829896 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.readBursts 2485330 # Number of DRAM read bursts (Count)
|
|
system.mem_ctrls.dram.writeBursts 2451327 # Number of DRAM write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::0 155445 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::1 155455 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::2 155323 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::3 155297 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::4 155369 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::5 155388 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::6 155285 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::7 155264 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::8 155311 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::9 155237 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::10 155169 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::11 155238 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::12 155291 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::13 155389 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::14 155468 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::15 155401 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::0 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::1 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::2 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::3 153225 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::4 153221 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::5 153274 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::6 153218 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::7 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::8 153237 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::9 153133 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::10 153109 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::11 153182 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::12 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::13 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::14 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::15 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.totQLat 27745859500 # Total ticks spent queuing (Tick)
|
|
system.mem_ctrls.dram.totBusLat 12426650000 # Total ticks spent in databus transfers (Tick)
|
|
system.mem_ctrls.dram.totMemAccLat 74345797000 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
|
|
system.mem_ctrls.dram.avgQLat 11163.85 # Average queueing delay per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.avgBusLat 5000.00 # Average bus latency per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.avgMemAccLat 29913.85 # Average memory access latency per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.readRowHits 2287496 # Number of row buffer hits during reads (Count)
|
|
system.mem_ctrls.dram.writeRowHits 2278230 # Number of row buffer hits during writes (Count)
|
|
system.mem_ctrls.dram.readRowHitRate 92.04 # Row buffer hit rate for reads (Ratio)
|
|
system.mem_ctrls.dram.writeRowHitRate 92.94 # Row buffer hit rate for writes (Ratio)
|
|
system.mem_ctrls.dram.bytesPerActivate::samples 370930 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::mean 851.765756 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::gmean 723.933933 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::stdev 309.332661 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::0-127 17161 4.63% 4.63% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::128-255 15200 4.10% 8.72% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::256-383 20621 5.56% 14.28% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::384-511 8380 2.26% 16.54% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::512-639 6268 1.69% 18.23% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::640-767 15020 4.05% 22.28% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::768-895 10029 2.70% 24.99% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::896-1023 30051 8.10% 33.09% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::1024-1151 248200 66.91% 100.00% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::total 370930 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesRead 159061120 # Total bytes read (Byte)
|
|
system.mem_ctrls.dram.bytesWritten 156884928 # Total bytes written (Byte)
|
|
system.mem_ctrls.dram.avgRdBW 759.103810 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
|
|
system.mem_ctrls.dram.avgWrBW 748.718144 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
|
|
system.mem_ctrls.dram.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
|
|
system.mem_ctrls.dram.busUtil 11.78 # Data bus utilization in percentage (Ratio)
|
|
system.mem_ctrls.dram.busUtilRead 5.93 # Data bus utilization in percentage for reads (Ratio)
|
|
system.mem_ctrls.dram.busUtilWrite 5.85 # Data bus utilization in percentage for writes (Ratio)
|
|
system.mem_ctrls.dram.pageHitRate 92.49 # Row buffer hit rate, read and write combined (Ratio)
|
|
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.mem_ctrls.dram.rank0.actEnergy 1325919420 # Energy for activate commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.preEnergy 704742885 # Energy for precharge commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.readEnergy 8873777640 # Energy for read commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.writeEnergy 6398686440 # Energy for write commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.refreshEnergy 16540577040.000002 # Energy for refresh commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.actBackEnergy 50381006100 # Energy for active background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.preBackEnergy 38036495040 # Energy for precharge background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.totalEnergy 122261204565 # Total energy per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.averagePower 583.479773 # Core power per rank (mW) (Watt)
|
|
system.mem_ctrls.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE 97271935000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::REF 6996860000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::ACT 105269239000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.actEnergy 1322527920 # Energy for activate commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.preEnergy 702936465 # Energy for precharge commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.readEnergy 8871478560 # Energy for read commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.writeEnergy 6397240500 # Energy for write commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.refreshEnergy 16540577040.000002 # Energy for refresh commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.actBackEnergy 50111852100 # Energy for active background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.preBackEnergy 38263151040 # Energy for precharge background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.totalEnergy 122209763625 # Total energy per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.averagePower 583.234276 # Core power per rank (mW) (Watt)
|
|
system.mem_ctrls.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE 97851199750 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::REF 6996860000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::ACT 104689974250 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.membus.transDist::ReadResp 1231 # Transaction distribution (Count)
|
|
system.membus.transDist::WritebackDirty 2451353 # Transaction distribution (Count)
|
|
system.membus.transDist::CleanEvict 817 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadExReq 2484099 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadExResp 2484099 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadSharedReq 1231 # Transaction distribution (Count)
|
|
system.membus.pktCount_system.l2.mem_side_port::system.mem_ctrls.port 7422830 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktCount_system.l2.mem_side_port::total 7422830 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktCount::total 7422830 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktSize_system.l2.mem_side_port::system.mem_ctrls.port 315947712 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.pktSize_system.l2.mem_side_port::total 315947712 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.pktSize::total 315947712 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.snoops 0 # Total snoops (Count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (Byte)
|
|
system.membus.snoopFanout::samples 2485330 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::0 2485330 100.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::total 2485330 # Request fanout histogram (Count)
|
|
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.membus.reqLayer2.occupancy 14751486500 # Layer occupancy (ticks) (Tick)
|
|
system.membus.reqLayer2.utilization 0.1 # Layer utilization (Ratio)
|
|
system.membus.respLayer1.occupancy 13070219000 # Layer occupancy (ticks) (Tick)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (Ratio)
|
|
system.membus.snoop_filter.totRequests 4937500 # Total number of requests made to the snoop filter. (Count)
|
|
system.membus.snoop_filter.hitSingleRequests 2452170 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
|
|
system.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.tol2bus.transDist::ReadResp 1243 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::WritebackDirty 4934456 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::WritebackClean 128 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::CleanEvict 1907 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::UpgradeReq 1 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::UpgradeResp 1 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadExReq 2484102 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadExResp 2484101 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadCleanReq 520 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadSharedReq 723 # Transaction distribution (Count)
|
|
system.tol2bus.pktCount_system.cpu.icache.mem_side_port::system.l2.cpu_side_port 1167 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port 7453451 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount::total 7454618 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktSize_system.cpu.icache.mem_side_port::system.l2.cpu_side_port 41408 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port 317947328 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize::total 317988736 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.snoops 2452564 # Total snoops (Count)
|
|
system.tol2bus.snoopTraffic 156886656 # Total snoop traffic (Byte)
|
|
system.tol2bus.snoopFanout::samples 4937909 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::mean 0.000080 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::stdev 0.008955 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::0 4937513 99.99% 99.99% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::1 396 0.01% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::max_value 1 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::total 4937909 # Request fanout histogram (Count)
|
|
system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 209538034000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.tol2bus.reqLayer0.occupancy 4967868000 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer0.occupancy 780000 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer1.occupancy 3727236500 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.snoop_filter.totRequests 4969274 # Total number of requests made to the snoop filter. (Count)
|
|
system.tol2bus.snoop_filter.hitSingleRequests 2483928 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.hitMultiRequests 2 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.totSnoops 394 # Total number of snoops made to the snoop filter. (Count)
|
|
system.tol2bus.snoop_filter.hitSingleSnoops 394 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.voltage_domain.voltage 1 # Voltage in Volts (Volt)
|
|
system.workload.inst.arm 0 # number of arm instructions executed (Count)
|
|
system.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
|
|
|
|
---------- End Simulation Statistics ----------
|