1422 lines
181 KiB
Plaintext
1422 lines
181 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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simSeconds 0.209591 # Number of seconds simulated (Second)
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simTicks 209590996000 # Number of ticks simulated (Tick)
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finalTick 209590996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
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simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
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hostSeconds 279.08 # Real time elapsed on the host (Second)
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hostTickRate 751000146 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
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hostMemory 677376 # Number of bytes of host memory used (Byte)
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simInsts 20000001 # Number of instructions simulated (Count)
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simOps 27556228 # Number of ops (including micro ops) simulated (Count)
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hostInstRate 71663 # Simulator instruction rate (inst/s) ((Count/Second))
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hostOpRate 98739 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
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system.clk_domain.clock 1000 # Clock period in ticks (Tick)
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system.cpu.numCycles 419181993 # Number of cpu cycles simulated (Cycle)
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system.cpu.cpi 20.959099 # CPI: cycles per instruction (core level) ((Cycle/Count))
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system.cpu.ipc 0.047712 # IPC: instructions per cycle (core level) ((Count/Cycle))
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system.cpu.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
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system.cpu.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
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system.cpu.instsAdded 29665710 # Number of instructions added to the IQ (excludes non-spec) (Count)
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system.cpu.nonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ (Count)
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system.cpu.instsIssued 29662186 # Number of instructions issued (Count)
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system.cpu.squashedInstsIssued 266 # Number of squashed instructions issued (Count)
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system.cpu.squashedInstsExamined 2109550 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
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system.cpu.squashedOperandsExamined 806507 # Number of squashed operands that are examined and possibly removed from graph (Count)
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system.cpu.squashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed (Count)
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system.cpu.numIssuedDist::samples 419137987 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::mean 0.070770 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::stdev 0.452854 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::0 406945301 97.09% 97.09% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::1 3936996 0.94% 98.03% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::2 1554815 0.37% 98.40% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::3 4187940 1.00% 99.40% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::4 2512935 0.60% 100.00% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::max_value 4 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::total 419137987 # Number of insts issued each cycle (Count)
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system.cpu.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideStore 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorStridedLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorStridedStore 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIndexedLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIndexedStore 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorWholeRegisterLoad 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorWholeRegisterStore 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIntegerArith 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorFloatArith 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorFloatConvert 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIntegerReduce 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorFloatReduce 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorMisc 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIntegerExtension 0 # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorConfig 0 # attempts to use FU when none available (Count)
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system.cpu.statIssuedInstType_0::No_OpClass 408 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::IntAlu 21604718 72.84% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::IntMult 47 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::IntDiv 82 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatAdd 163 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAdd 10 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAddAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAlu 279 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdCmp 4 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdCvt 84 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMisc 254 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdShift 4 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdShiftAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdReduceAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAes 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAesMix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSha1Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSha256Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdShaSigma2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdShaSigma3 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdPredAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::Matrix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
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system.cpu.statIssuedInstType_0::MatrixMov 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::MatrixOP 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::MemRead 2683927 9.05% 81.89% # Number of instructions issued per FU type, per thread (Count)
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|
system.cpu.statIssuedInstType_0::MemWrite 5371490 18.11% 100.00% # Number of instructions issued per FU type, per thread (Count)
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|
system.cpu.statIssuedInstType_0::FloatMemRead 157 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
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|
system.cpu.statIssuedInstType_0::FloatMemWrite 559 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::total 29662186 # Number of instructions issued per FU type, per thread (Count)
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|
system.cpu.issueRate 0.070762 # Inst issue rate ((Count/Cycle))
|
|
system.cpu.fuBusy 0 # FU busy when requested (Count)
|
|
system.cpu.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
|
|
system.cpu.intInstQueueReads 478459247 # Number of integer instruction queue reads (Count)
|
|
system.cpu.intInstQueueWrites 31773411 # Number of integer instruction queue writes (Count)
|
|
system.cpu.intInstQueueWakeupAccesses 29462756 # Number of integer instruction queue wakeup accesses (Count)
|
|
system.cpu.fpInstQueueReads 3378 # Number of floating instruction queue reads (Count)
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|
system.cpu.fpInstQueueWrites 1957 # Number of floating instruction queue writes (Count)
|
|
system.cpu.fpInstQueueWakeupAccesses 1653 # Number of floating instruction queue wakeup accesses (Count)
|
|
system.cpu.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
|
|
system.cpu.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
|
|
system.cpu.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
|
|
system.cpu.intAluAccesses 29660091 # Number of integer alu accesses (Count)
|
|
system.cpu.fpAluAccesses 1687 # Number of floating point alu accesses (Count)
|
|
system.cpu.vecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu.numSquashedInsts 756 # Number of squashed instructions skipped in execute (Count)
|
|
system.cpu.numSwp 0 # Number of swp insts executed (Count)
|
|
system.cpu.timesIdled 369 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
|
|
system.cpu.idleCycles 44006 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
|
|
system.cpu.MemDepUnit__0.insertedLoads 2684380 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__0.insertedStores 5372361 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__0.conflictingLoads 614456 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__0.conflictingStores 475315 # Number of conflicting stores. (Count)
|
|
system.cpu.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu.branchPred.lookups 2764681 # Number of BP lookups (Count)
|
|
system.cpu.branchPred.condPredicted 2753885 # Number of conditional branches predicted (Count)
|
|
system.cpu.branchPred.condIncorrect 744 # Number of conditional branches incorrect (Count)
|
|
system.cpu.branchPred.BTBLookups 2739914 # Number of BTB lookups (Count)
|
|
system.cpu.branchPred.BTBUpdates 622 # Number of BTB updates (Count)
|
|
system.cpu.branchPred.BTBHits 2739571 # Number of BTB hits (Count)
|
|
system.cpu.branchPred.BTBHitRatio 0.999875 # BTB Hit Ratio (Ratio)
|
|
system.cpu.branchPred.RASUsed 2485 # Number of times the RAS was used to get a target. (Count)
|
|
system.cpu.branchPred.RASIncorrect 9 # Number of incorrect RAS predictions. (Count)
|
|
system.cpu.branchPred.indirectLookups 2304 # Number of indirect predictor lookups. (Count)
|
|
system.cpu.branchPred.indirectHits 2156 # Number of indirect target hits. (Count)
|
|
system.cpu.branchPred.indirectMisses 148 # Number of indirect misses. (Count)
|
|
system.cpu.branchPred.indirectMispredicted 62 # Number of mispredicted indirect branches. (Count)
|
|
system.cpu.branchPred.loop_predictor.correct 2504796 # Number of times the loop predictor is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.loop_predictor.wrong 1861 # Number of times the loop predictor is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.longestMatchProviderCorrect 1441765 # Number of times TAGE Longest Match is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.tage.altMatchProviderCorrect 80 # Number of times TAGE Alt Match is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 76 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.tage.bimodalProviderCorrect 1064343 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct (Count)
|
|
system.cpu.branchPred.tage.longestMatchProviderWrong 47 # Number of times TAGE Longest Match is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.altMatchProviderWrong 17 # Number of times TAGE Alt Match is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 26 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.bimodalProviderWrong 303 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.altMatchProviderWouldHaveHit 5 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct (Count)
|
|
system.cpu.branchPred.tage.longestMatchProviderWouldHaveHit 28 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::0 0 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::1 1049102 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::2 387089 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::3 2108 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::4 1436 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::5 1513 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::6 68 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::7 264 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::8 101 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::9 141 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::10 4 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::11 83 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::12 0 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::0 1052322 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::1 387093 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::2 1318 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::3 8 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::4 535 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::5 76 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::6 236 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::7 100 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::8 135 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::9 86 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::10 0 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::11 0 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::12 0 # TAGE provider for alt match (Count)
|
|
system.cpu.commit.commitSquashedInsts 2109349 # The number of squashed insts skipped by commit (Count)
|
|
system.cpu.commit.commitNonSpecStalls 42 # The number of times commit has been forced to stall to communicate backwards (Count)
|
|
system.cpu.commit.branchMispredicts 508 # The number of times a branch was mispredicted (Count)
|
|
system.cpu.commit.numCommittedDist::samples 418874012 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::mean 0.065786 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::stdev 0.437025 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::0 407369888 97.25% 97.25% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::1 3992379 0.95% 98.21% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::2 1507864 0.36% 98.57% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::3 3467403 0.83% 99.39% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::4 2536478 0.61% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::max_value 4 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::total 418874012 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.amos 0 # Number of atomic instructions committed (Count)
|
|
system.cpu.commit.membars 28 # Number of memory barriers committed (Count)
|
|
system.cpu.commit.functionCalls 2307 # Number of function calls committed. (Count)
|
|
system.cpu.commit.committedInstType_0::No_OpClass 250 0.00% 0.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IntAlu 20074105 72.85% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IntMult 41 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IntDiv 56 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatAdd 146 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAdd 10 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAlu 237 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdCmp 4 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdCvt 76 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMisc 235 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShift 3 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAes 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAesMix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::Matrix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MatrixMov 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MatrixOP 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MemRead 2502669 9.08% 81.93% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MemWrite 4977757 18.06% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMemRead 125 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::total 27556228 # Class of committed instruction (Count)
|
|
system.cpu.commit.commitEligibleSamples 2536478 # number cycles where commit BW limit reached (Cycle)
|
|
system.cpu.commitStats0.numInsts 20000001 # Number of instructions committed (thread level) (Count)
|
|
system.cpu.commitStats0.numOps 27556228 # Number of ops (including micro ops) committed (thread level) (Count)
|
|
system.cpu.commitStats0.numInstsNotNOP 20000001 # Number of instructions committed excluding NOPs or prefetches (Count)
|
|
system.cpu.commitStats0.numOpsNotNOP 27556228 # Number of Ops (including micro ops) Simulated (Count)
|
|
system.cpu.commitStats0.cpi 20.959099 # CPI: cycles per instruction (thread level) ((Cycle/Count))
|
|
system.cpu.commitStats0.ipc 0.047712 # IPC: instructions per cycle (thread level) ((Count/Cycle))
|
|
system.cpu.commitStats0.numMemRefs 7481065 # Number of memory references committed (Count)
|
|
system.cpu.commitStats0.numFpInsts 1513 # Number of float instructions (Count)
|
|
system.cpu.commitStats0.numIntInsts 27555090 # Number of integer instructions (Count)
|
|
system.cpu.commitStats0.numLoadInsts 2502794 # Number of load instructions (Count)
|
|
system.cpu.commitStats0.numStoreInsts 4978271 # Number of store instructions (Count)
|
|
system.cpu.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
|
|
system.cpu.commitStats0.committedInstType::No_OpClass 250 0.00% 0.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IntAlu 20074105 72.85% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IntMult 41 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IntDiv 56 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatAdd 146 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAdd 10 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAlu 237 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdCmp 4 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdCvt 76 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMisc 235 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShift 3 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAes 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::Matrix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MatrixMov 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MatrixOP 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MemRead 2502669 9.08% 81.93% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MemWrite 4977757 18.06% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMemRead 125 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::total 27556228 # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedControl::IsControl 2516676 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsDirectControl 2512216 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsIndirectControl 4460 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsCondControl 2506658 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsUncondControl 10018 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsCall 2307 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsReturn 2304 # Class of control type instructions committed (Count)
|
|
system.cpu.dcache.demandHits::cpu.data 2507401 # number of demand (read+write) hits (Count)
|
|
system.cpu.dcache.demandHits::total 2507401 # number of demand (read+write) hits (Count)
|
|
system.cpu.dcache.overallHits::cpu.data 2507401 # number of overall hits (Count)
|
|
system.cpu.dcache.overallHits::total 2507401 # number of overall hits (Count)
|
|
system.cpu.dcache.demandMisses::cpu.data 2485833 # number of demand (read+write) misses (Count)
|
|
system.cpu.dcache.demandMisses::total 2485833 # number of demand (read+write) misses (Count)
|
|
system.cpu.dcache.overallMisses::cpu.data 2485833 # number of overall misses (Count)
|
|
system.cpu.dcache.overallMisses::total 2485833 # number of overall misses (Count)
|
|
system.cpu.dcache.demandMissLatency::cpu.data 206800739500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.dcache.demandMissLatency::total 206800739500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.dcache.overallMissLatency::cpu.data 206800739500 # number of overall miss ticks (Tick)
|
|
system.cpu.dcache.overallMissLatency::total 206800739500 # number of overall miss ticks (Tick)
|
|
system.cpu.dcache.demandAccesses::cpu.data 4993234 # number of demand (read+write) accesses (Count)
|
|
system.cpu.dcache.demandAccesses::total 4993234 # number of demand (read+write) accesses (Count)
|
|
system.cpu.dcache.overallAccesses::cpu.data 4993234 # number of overall (read+write) accesses (Count)
|
|
system.cpu.dcache.overallAccesses::total 4993234 # number of overall (read+write) accesses (Count)
|
|
system.cpu.dcache.demandMissRate::cpu.data 0.497840 # miss rate for demand accesses (Ratio)
|
|
system.cpu.dcache.demandMissRate::total 0.497840 # miss rate for demand accesses (Ratio)
|
|
system.cpu.dcache.overallMissRate::cpu.data 0.497840 # miss rate for overall accesses (Ratio)
|
|
system.cpu.dcache.overallMissRate::total 0.497840 # miss rate for overall accesses (Ratio)
|
|
system.cpu.dcache.demandAvgMissLatency::cpu.data 83191.726677 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.dcache.demandAvgMissLatency::total 83191.726677 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMissLatency::cpu.data 83191.726677 # average overall miss latency ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMissLatency::total 83191.726677 # average overall miss latency ((Tick/Count))
|
|
system.cpu.dcache.blockedCycles::no_mshrs 363 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dcache.blockedCauses::no_mshrs 9 # number of times access was blocked (Count)
|
|
system.cpu.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.dcache.avgBlocked::no_mshrs 40.333333 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dcache.writebacks::writebacks 2483079 # number of writebacks (Count)
|
|
system.cpu.dcache.writebacks::total 2483079 # number of writebacks (Count)
|
|
system.cpu.dcache.demandMshrHits::cpu.data 1026 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.dcache.demandMshrHits::total 1026 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.dcache.overallMshrHits::cpu.data 1026 # number of overall MSHR hits (Count)
|
|
system.cpu.dcache.overallMshrHits::total 1026 # number of overall MSHR hits (Count)
|
|
system.cpu.dcache.demandMshrMisses::cpu.data 2484807 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.dcache.demandMshrMisses::total 2484807 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.dcache.overallMshrMisses::cpu.data 2484807 # number of overall MSHR misses (Count)
|
|
system.cpu.dcache.overallMshrMisses::total 2484807 # number of overall MSHR misses (Count)
|
|
system.cpu.dcache.demandMshrMissLatency::cpu.data 204239097500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.dcache.demandMshrMissLatency::total 204239097500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.dcache.overallMshrMissLatency::cpu.data 204239097500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.dcache.overallMshrMissLatency::total 204239097500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.dcache.demandMshrMissRate::cpu.data 0.497635 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.dcache.demandMshrMissRate::total 0.497635 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.dcache.overallMshrMissRate::cpu.data 0.497635 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.dcache.overallMshrMissRate::total 0.497635 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.dcache.demandAvgMshrMissLatency::cpu.data 82195.155398 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.demandAvgMshrMissLatency::total 82195.155398 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMshrMissLatency::cpu.data 82195.155398 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMshrMissLatency::total 82195.155398 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.replacements 2483781 # number of replacements (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.hits::cpu.data 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.hits::total 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.misses::cpu.data 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.misses::total 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.missLatency::cpu.data 102000 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.missLatency::total 102000 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.accesses::cpu.data 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.accesses::total 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.missRate::cpu.data 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.missRate::total 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::cpu.data 102000 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::total 102000 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMisses::cpu.data 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMisses::total 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::cpu.data 255000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::total 255000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::cpu.data 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::total 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu.data 255000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::total 255000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWWriteReq.hits::cpu.data 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu.dcache.LockedRMWWriteReq.hits::total 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu.dcache.LockedRMWWriteReq.accesses::cpu.data 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.LockedRMWWriteReq.accesses::total 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.ReadReq.hits::cpu.data 13285 # number of ReadReq hits (Count)
|
|
system.cpu.dcache.ReadReq.hits::total 13285 # number of ReadReq hits (Count)
|
|
system.cpu.dcache.ReadReq.misses::cpu.data 1755 # number of ReadReq misses (Count)
|
|
system.cpu.dcache.ReadReq.misses::total 1755 # number of ReadReq misses (Count)
|
|
system.cpu.dcache.ReadReq.missLatency::cpu.data 133835000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.missLatency::total 133835000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.accesses::cpu.data 15040 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.ReadReq.accesses::total 15040 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.ReadReq.missRate::cpu.data 0.116689 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.missRate::total 0.116689 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.avgMissLatency::cpu.data 76259.259259 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.ReadReq.avgMissLatency::total 76259.259259 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.ReadReq.mshrHits::cpu.data 1026 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.dcache.ReadReq.mshrHits::total 1026 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.dcache.ReadReq.mshrMisses::cpu.data 729 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.dcache.ReadReq.mshrMisses::total 729 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.dcache.ReadReq.mshrMissLatency::cpu.data 56270000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.mshrMissLatency::total 56270000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.mshrMissRate::cpu.data 0.048471 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.mshrMissRate::total 0.048471 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.avgMshrMissLatency::cpu.data 77187.928669 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.ReadReq.avgMshrMissLatency::total 77187.928669 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.hits::cpu.data 2494116 # number of WriteReq hits (Count)
|
|
system.cpu.dcache.WriteReq.hits::total 2494116 # number of WriteReq hits (Count)
|
|
system.cpu.dcache.WriteReq.misses::cpu.data 2484078 # number of WriteReq misses (Count)
|
|
system.cpu.dcache.WriteReq.misses::total 2484078 # number of WriteReq misses (Count)
|
|
system.cpu.dcache.WriteReq.missLatency::cpu.data 206666904500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.missLatency::total 206666904500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.accesses::cpu.data 4978194 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.WriteReq.accesses::total 4978194 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.WriteReq.missRate::cpu.data 0.498992 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.missRate::total 0.498992 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.avgMissLatency::cpu.data 83196.624462 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.avgMissLatency::total 83196.624462 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.mshrMisses::cpu.data 2484078 # number of WriteReq MSHR misses (Count)
|
|
system.cpu.dcache.WriteReq.mshrMisses::total 2484078 # number of WriteReq MSHR misses (Count)
|
|
system.cpu.dcache.WriteReq.mshrMissLatency::cpu.data 204182827500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.mshrMissLatency::total 204182827500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.mshrMissRate::cpu.data 0.498992 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.mshrMissRate::total 0.498992 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.avgMshrMissLatency::cpu.data 82196.624864 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.avgMshrMissLatency::total 82196.624864 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.dcache.tags.tagsInUse 1023.645030 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.dcache.tags.totalRefs 4992235 # Total number of references to valid blocks. (Count)
|
|
system.cpu.dcache.tags.sampledRefs 2484805 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.dcache.tags.avgRefs 2.009105 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.dcache.tags.warmupTick 176500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.dcache.tags.occupancies::cpu.data 1023.645030 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu.dcache.tags.avgOccs::cpu.data 0.999653 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.dcache.tags.avgOccs::total 0.999653 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.dcache.tags.occupanciesTaskId::1024 1024 # Occupied blocks per task id (Count)
|
|
system.cpu.dcache.tags.ageTaskId_1024::0 117 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.dcache.tags.ageTaskId_1024::1 906 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.dcache.tags.ageTaskId_1024::4 1 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu.dcache.tags.tagAccesses 12471329 # Number of tag accesses (Count)
|
|
system.cpu.dcache.tags.dataAccesses 12471329 # Number of data accesses (Count)
|
|
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.decode.idleCycles 1700986 # Number of cycles decode is idle (Cycle)
|
|
system.cpu.decode.blockedCycles 409966674 # Number of cycles decode is blocked (Cycle)
|
|
system.cpu.decode.runCycles 3627074 # Number of cycles decode is running (Cycle)
|
|
system.cpu.decode.unblockCycles 3826303 # Number of cycles decode is unblocking (Cycle)
|
|
system.cpu.decode.squashCycles 16950 # Number of cycles decode is squashing (Cycle)
|
|
system.cpu.decode.branchResolved 2690519 # Number of times decode resolved a branch (Count)
|
|
system.cpu.decode.branchMispred 262 # Number of times decode detected a branch misprediction (Count)
|
|
system.cpu.decode.decodedInsts 29734386 # Number of instructions handled by decode (Count)
|
|
system.cpu.decode.squashedInsts 759 # Number of squashed instructions handled by decode (Count)
|
|
system.cpu.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dtb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.executeStats0.numInsts 29661430 # Number of executed instructions (Count)
|
|
system.cpu.executeStats0.numNop 0 # Number of nop insts executed (Count)
|
|
system.cpu.executeStats0.numBranches 2697537 # Number of branches executed (Count)
|
|
system.cpu.executeStats0.numLoadInsts 2683946 # Number of load instructions executed (Count)
|
|
system.cpu.executeStats0.numStoreInsts 5371977 # Number of stores executed (Count)
|
|
system.cpu.executeStats0.instRate 0.070760 # Inst execution rate ((Count/Cycle))
|
|
system.cpu.executeStats0.numCCRegReads 13477364 # Number of times the CC registers were read (Count)
|
|
system.cpu.executeStats0.numCCRegWrites 16165209 # Number of times the CC registers were written (Count)
|
|
system.cpu.executeStats0.numFpRegReads 2044 # Number of times the floating registers were read (Count)
|
|
system.cpu.executeStats0.numFpRegWrites 1032 # Number of times the floating registers were written (Count)
|
|
system.cpu.executeStats0.numIntRegReads 48450456 # Number of times the integer registers were read (Count)
|
|
system.cpu.executeStats0.numIntRegWrites 18885874 # Number of times the integer registers were written (Count)
|
|
system.cpu.executeStats0.numMemRefs 8055923 # Number of memory refs (Count)
|
|
system.cpu.executeStats0.numMiscRegReads 13466035 # Number of times the Misc registers were read (Count)
|
|
system.cpu.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
|
|
system.cpu.fetch.predictedBranches 2744212 # Number of branches that fetch has predicted taken (Count)
|
|
system.cpu.fetch.cycles 419080771 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
|
|
system.cpu.fetch.squashCycles 34418 # Number of cycles fetch has spent squashing (Cycle)
|
|
system.cpu.fetch.miscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
|
|
system.cpu.fetch.pendingTrapStallCycles 144 # Number of stall cycles due to pending traps (Cycle)
|
|
system.cpu.fetch.cacheLines 18783 # Number of cache lines fetched (Count)
|
|
system.cpu.fetch.icacheSquashes 332 # Number of outstanding Icache misses that were squashed (Count)
|
|
system.cpu.fetch.nisnDist::samples 419137987 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::mean 0.072360 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::stdev 0.504229 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::0 409786542 97.77% 97.77% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::1 1078998 0.26% 98.03% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::2 1100224 0.26% 98.29% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::3 1639475 0.39% 98.68% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::4 5532748 1.32% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::max_value 4 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::total 419137987 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetchStats0.numInsts 22026235 # Number of instructions fetched (thread level) (Count)
|
|
system.cpu.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
|
|
system.cpu.fetchStats0.fetchRate 0.052546 # Number of inst fetches per cycle ((Count/Cycle))
|
|
system.cpu.fetchStats0.numBranches 2764681 # Number of branches fetched (Count)
|
|
system.cpu.fetchStats0.branchRate 0.006595 # Number of branch fetches per cycle (Ratio)
|
|
system.cpu.fetchStats0.icacheStallCycles 39837 # ICache total stall cycles (Cycle)
|
|
system.cpu.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
|
|
system.cpu.icache.demandHits::cpu.inst 18089 # number of demand (read+write) hits (Count)
|
|
system.cpu.icache.demandHits::total 18089 # number of demand (read+write) hits (Count)
|
|
system.cpu.icache.overallHits::cpu.inst 18089 # number of overall hits (Count)
|
|
system.cpu.icache.overallHits::total 18089 # number of overall hits (Count)
|
|
system.cpu.icache.demandMisses::cpu.inst 694 # number of demand (read+write) misses (Count)
|
|
system.cpu.icache.demandMisses::total 694 # number of demand (read+write) misses (Count)
|
|
system.cpu.icache.overallMisses::cpu.inst 694 # number of overall misses (Count)
|
|
system.cpu.icache.overallMisses::total 694 # number of overall misses (Count)
|
|
system.cpu.icache.demandMissLatency::cpu.inst 51567000 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.icache.demandMissLatency::total 51567000 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.icache.overallMissLatency::cpu.inst 51567000 # number of overall miss ticks (Tick)
|
|
system.cpu.icache.overallMissLatency::total 51567000 # number of overall miss ticks (Tick)
|
|
system.cpu.icache.demandAccesses::cpu.inst 18783 # number of demand (read+write) accesses (Count)
|
|
system.cpu.icache.demandAccesses::total 18783 # number of demand (read+write) accesses (Count)
|
|
system.cpu.icache.overallAccesses::cpu.inst 18783 # number of overall (read+write) accesses (Count)
|
|
system.cpu.icache.overallAccesses::total 18783 # number of overall (read+write) accesses (Count)
|
|
system.cpu.icache.demandMissRate::cpu.inst 0.036948 # miss rate for demand accesses (Ratio)
|
|
system.cpu.icache.demandMissRate::total 0.036948 # miss rate for demand accesses (Ratio)
|
|
system.cpu.icache.overallMissRate::cpu.inst 0.036948 # miss rate for overall accesses (Ratio)
|
|
system.cpu.icache.overallMissRate::total 0.036948 # miss rate for overall accesses (Ratio)
|
|
system.cpu.icache.demandAvgMissLatency::cpu.inst 74304.034582 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.icache.demandAvgMissLatency::total 74304.034582 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.icache.overallAvgMissLatency::cpu.inst 74304.034582 # average overall miss latency ((Tick/Count))
|
|
system.cpu.icache.overallAvgMissLatency::total 74304.034582 # average overall miss latency ((Tick/Count))
|
|
system.cpu.icache.blockedCycles::no_mshrs 419 # number of cycles access was blocked (Cycle)
|
|
system.cpu.icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.icache.blockedCauses::no_mshrs 3 # number of times access was blocked (Count)
|
|
system.cpu.icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.icache.avgBlocked::no_mshrs 139.666667 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.icache.writebacks::writebacks 158 # number of writebacks (Count)
|
|
system.cpu.icache.writebacks::total 158 # number of writebacks (Count)
|
|
system.cpu.icache.demandMshrHits::cpu.inst 130 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.icache.demandMshrHits::total 130 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.icache.overallMshrHits::cpu.inst 130 # number of overall MSHR hits (Count)
|
|
system.cpu.icache.overallMshrHits::total 130 # number of overall MSHR hits (Count)
|
|
system.cpu.icache.demandMshrMisses::cpu.inst 564 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.icache.demandMshrMisses::total 564 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.icache.overallMshrMisses::cpu.inst 564 # number of overall MSHR misses (Count)
|
|
system.cpu.icache.overallMshrMisses::total 564 # number of overall MSHR misses (Count)
|
|
system.cpu.icache.demandMshrMissLatency::cpu.inst 43601000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.icache.demandMshrMissLatency::total 43601000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.icache.overallMshrMissLatency::cpu.inst 43601000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.icache.overallMshrMissLatency::total 43601000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.icache.demandMshrMissRate::cpu.inst 0.030027 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.icache.demandMshrMissRate::total 0.030027 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.icache.overallMshrMissRate::cpu.inst 0.030027 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.icache.overallMshrMissRate::total 0.030027 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.icache.demandAvgMshrMissLatency::cpu.inst 77306.737589 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.demandAvgMshrMissLatency::total 77306.737589 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.overallAvgMshrMissLatency::cpu.inst 77306.737589 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.overallAvgMshrMissLatency::total 77306.737589 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.replacements 158 # number of replacements (Count)
|
|
system.cpu.icache.ReadReq.hits::cpu.inst 18089 # number of ReadReq hits (Count)
|
|
system.cpu.icache.ReadReq.hits::total 18089 # number of ReadReq hits (Count)
|
|
system.cpu.icache.ReadReq.misses::cpu.inst 694 # number of ReadReq misses (Count)
|
|
system.cpu.icache.ReadReq.misses::total 694 # number of ReadReq misses (Count)
|
|
system.cpu.icache.ReadReq.missLatency::cpu.inst 51567000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.missLatency::total 51567000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.accesses::cpu.inst 18783 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.icache.ReadReq.accesses::total 18783 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.icache.ReadReq.missRate::cpu.inst 0.036948 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.missRate::total 0.036948 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.avgMissLatency::cpu.inst 74304.034582 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.icache.ReadReq.avgMissLatency::total 74304.034582 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.icache.ReadReq.mshrHits::cpu.inst 130 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.icache.ReadReq.mshrHits::total 130 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.icache.ReadReq.mshrMisses::cpu.inst 564 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.icache.ReadReq.mshrMisses::total 564 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.icache.ReadReq.mshrMissLatency::cpu.inst 43601000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.mshrMissLatency::total 43601000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.mshrMissRate::cpu.inst 0.030027 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.mshrMissRate::total 0.030027 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.avgMshrMissLatency::cpu.inst 77306.737589 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.ReadReq.avgMshrMissLatency::total 77306.737589 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.icache.tags.tagsInUse 403.957471 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.icache.tags.totalRefs 18653 # Total number of references to valid blocks. (Count)
|
|
system.cpu.icache.tags.sampledRefs 564 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.icache.tags.avgRefs 33.072695 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.icache.tags.warmupTick 87500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.icache.tags.occupancies::cpu.inst 403.957471 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu.icache.tags.avgOccs::cpu.inst 0.788979 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.icache.tags.avgOccs::total 0.788979 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.icache.tags.occupanciesTaskId::1024 404 # Occupied blocks per task id (Count)
|
|
system.cpu.icache.tags.ageTaskId_1024::4 404 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.icache.tags.ratioOccsTaskId::1024 0.789062 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu.icache.tags.tagAccesses 38130 # Number of tag accesses (Count)
|
|
system.cpu.icache.tags.dataAccesses 38130 # Number of data accesses (Count)
|
|
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
|
|
system.cpu.iew.squashCycles 16950 # Number of cycles IEW is squashing (Cycle)
|
|
system.cpu.iew.blockCycles 248029 # Number of cycles IEW is blocking (Cycle)
|
|
system.cpu.iew.unblockCycles 154414998 # Number of cycles IEW is unblocking (Cycle)
|
|
system.cpu.iew.dispatchedInsts 29665779 # Number of instructions dispatched to IQ (Count)
|
|
system.cpu.iew.dispSquashedInsts 137 # Number of squashed instructions skipped by dispatch (Count)
|
|
system.cpu.iew.dispLoadInsts 2684380 # Number of dispatched load instructions (Count)
|
|
system.cpu.iew.dispStoreInsts 5372361 # Number of dispatched store instructions (Count)
|
|
system.cpu.iew.dispNonSpecInsts 24 # Number of dispatched non-speculative instructions (Count)
|
|
system.cpu.iew.iqFullEvents 6 # Number of times the IQ has become full, causing a stall (Count)
|
|
system.cpu.iew.lsqFullEvents 154414984 # Number of times the LSQ has become full, causing a stall (Count)
|
|
system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations (Count)
|
|
system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly (Count)
|
|
system.cpu.iew.predictedNotTakenIncorrect 483 # Number of branches that were predicted not taken incorrectly (Count)
|
|
system.cpu.iew.branchMispredicts 554 # Number of branch mispredicts detected at execute (Count)
|
|
system.cpu.iew.instsToCommit 29661192 # Cumulative count of insts sent to commit (Count)
|
|
system.cpu.iew.writebackCount 29464409 # Cumulative count of insts written-back (Count)
|
|
system.cpu.iew.producerInst 11229019 # Number of instructions producing a value (Count)
|
|
system.cpu.iew.consumerInst 16338522 # Number of instructions consuming a value (Count)
|
|
system.cpu.iew.wbRate 0.070290 # Insts written-back per cycle ((Count/Cycle))
|
|
system.cpu.iew.wbFanout 0.687273 # Average fanout of values written-back ((Count/Count))
|
|
system.cpu.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
|
|
system.cpu.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.itb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.lsq0.forwLoads 2668824 # Number of loads that had data forwarded from stores (Count)
|
|
system.cpu.lsq0.squashedLoads 181586 # Number of loads squashed (Count)
|
|
system.cpu.lsq0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed (Count)
|
|
system.cpu.lsq0.memOrderViolation 42 # Number of memory ordering violations (Count)
|
|
system.cpu.lsq0.squashedStores 394090 # Number of stores squashed (Count)
|
|
system.cpu.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
|
|
system.cpu.lsq0.blockedByCache 8 # Number of times an access to memory failed due to the cache being blocked (Count)
|
|
system.cpu.lsq0.loadToUse::samples 2502793 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::mean 2.105097 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::stdev 4.253246 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::0-9 2501160 99.93% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::10-19 1 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::20-29 5 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::30-39 1 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::110-119 6 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::120-129 16 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::130-139 417 0.02% 99.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::140-149 984 0.04% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::150-159 23 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::160-169 31 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::170-179 72 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::180-189 4 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::200-209 32 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::210-219 5 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::220-229 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::270-279 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::280-289 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::290-299 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::overflows 31 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::max_value 714 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::total 2502793 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.mmu.dtb.rdAccesses 2683931 # TLB accesses on read requests (Count)
|
|
system.cpu.mmu.dtb.wrAccesses 5371977 # TLB accesses on write requests (Count)
|
|
system.cpu.mmu.dtb.rdMisses 75 # TLB misses on read requests (Count)
|
|
system.cpu.mmu.dtb.wrMisses 235433 # TLB misses on write requests (Count)
|
|
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
|
|
system.cpu.mmu.itb.wrAccesses 18809 # TLB accesses on write requests (Count)
|
|
system.cpu.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
|
|
system.cpu.mmu.itb.wrMisses 69 # TLB misses on write requests (Count)
|
|
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.power_state.pwrStateResidencyTicks::ON 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.rename.squashCycles 16950 # Number of cycles rename is squashing (Cycle)
|
|
system.cpu.rename.idleCycles 3118418 # Number of cycles rename is idle (Cycle)
|
|
system.cpu.rename.blockCycles 209018733 # Number of cycles rename is blocking (Cycle)
|
|
system.cpu.rename.serializeStallCycles 1504 # count of cycles rename stalled for serializing inst (Cycle)
|
|
system.cpu.rename.runCycles 6002477 # Number of cycles rename is running (Cycle)
|
|
system.cpu.rename.unblockCycles 200979905 # Number of cycles rename is unblocking (Cycle)
|
|
system.cpu.rename.renamedInsts 29667786 # Number of instructions processed by rename (Count)
|
|
system.cpu.rename.ROBFullEvents 20186 # Number of times rename has blocked due to ROB full (Count)
|
|
system.cpu.rename.IQFullEvents 520 # Number of times rename has blocked due to IQ full (Count)
|
|
system.cpu.rename.SQFullEvents 200048403 # Number of times rename has blocked due to SQ full (Count)
|
|
system.cpu.rename.renamedOperands 62017972 # Number of destination operands rename has renamed (Count)
|
|
system.cpu.rename.lookups 121212664 # Number of register rename lookups that rename has made (Count)
|
|
system.cpu.rename.intLookups 48461023 # Number of integer rename lookups (Count)
|
|
system.cpu.rename.fpLookups 2145 # Number of floating rename lookups (Count)
|
|
system.cpu.rename.committedMaps 57521754 # Number of HB maps that are committed (Count)
|
|
system.cpu.rename.undoneMaps 4496215 # Number of HB maps that are undone due to squashing (Count)
|
|
system.cpu.rename.serializing 37 # count of serializing insts renamed (Count)
|
|
system.cpu.rename.tempSerializing 37 # count of temporary serializing insts renamed (Count)
|
|
system.cpu.rename.skidInsts 11265614 # count of insts added to the skid buffer (Count)
|
|
system.cpu.rob.reads 445789885 # The number of ROB reads (Count)
|
|
system.cpu.rob.writes 59595134 # The number of ROB writes (Count)
|
|
system.cpu.thread_0.numInsts 20000001 # Number of Instructions committed (Count)
|
|
system.cpu.thread_0.numOps 27556228 # Number of Ops committed (Count)
|
|
system.cpu.thread_0.numMemRefs 0 # Number of Memory References (Count)
|
|
system.cpu.workload.numSyscalls 14 # Number of system calls (Count)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks (Tick)
|
|
system.cpu_voltage_domain.voltage 1 # Voltage in Volts (Volt)
|
|
system.l2.demandHits::cpu.inst 11 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu.data 5 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::total 16 # number of demand (read+write) hits (Count)
|
|
system.l2.overallHits::cpu.inst 11 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu.data 5 # number of overall hits (Count)
|
|
system.l2.overallHits::total 16 # number of overall hits (Count)
|
|
system.l2.demandMisses::cpu.inst 551 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu.data 2484801 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::total 2485352 # number of demand (read+write) misses (Count)
|
|
system.l2.overallMisses::cpu.inst 551 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu.data 2484801 # number of overall misses (Count)
|
|
system.l2.overallMisses::total 2485352 # number of overall misses (Count)
|
|
system.l2.demandMissLatency::cpu.inst 42634500 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu.data 200511901000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::total 200554535500 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu.inst 42634500 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu.data 200511901000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::total 200554535500 # number of overall miss ticks (Tick)
|
|
system.l2.demandAccesses::cpu.inst 562 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu.data 2484806 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::total 2485368 # number of demand (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu.inst 562 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu.data 2484806 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::total 2485368 # number of overall (read+write) accesses (Count)
|
|
system.l2.demandMissRate::cpu.inst 0.980427 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu.data 0.999998 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::total 0.999994 # miss rate for demand accesses (Ratio)
|
|
system.l2.overallMissRate::cpu.inst 0.980427 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu.data 0.999998 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::total 0.999994 # miss rate for overall accesses (Ratio)
|
|
system.l2.demandAvgMissLatency::cpu.inst 77376.588022 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu.data 80695.355886 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::total 80694.620118 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu.inst 77376.588022 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu.data 80695.355886 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::total 80694.620118 # average overall miss latency ((Tick/Count))
|
|
system.l2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.l2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.l2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.l2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.l2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.l2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.l2.writebacks::writebacks 2451329 # number of writebacks (Count)
|
|
system.l2.writebacks::total 2451329 # number of writebacks (Count)
|
|
system.l2.demandMshrMisses::cpu.inst 551 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu.data 2484801 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::total 2485352 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu.inst 551 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu.data 2484801 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::total 2485352 # number of overall MSHR misses (Count)
|
|
system.l2.demandMshrMissLatency::cpu.inst 37124500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu.data 175663901000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::total 175701025500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu.inst 37124500 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu.data 175663901000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::total 175701025500 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissRate::cpu.inst 0.980427 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu.data 0.999998 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::total 0.999994 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu.inst 0.980427 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu.data 0.999998 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::total 0.999994 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.demandAvgMshrMissLatency::cpu.inst 67376.588022 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu.data 70695.359910 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::total 70694.624142 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu.inst 67376.588022 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu.data 70695.359910 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::total 70694.624142 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.replacements 2452584 # number of replacements (Count)
|
|
system.l2.ReadCleanReq.hits::cpu.inst 11 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.hits::total 11 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.misses::cpu.inst 551 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.misses::total 551 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.missLatency::cpu.inst 42634500 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.missLatency::total 42634500 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.accesses::cpu.inst 562 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.accesses::total 562 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.missRate::cpu.inst 0.980427 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.missRate::total 0.980427 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.avgMissLatency::cpu.inst 77376.588022 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMissLatency::total 77376.588022 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.mshrMisses::cpu.inst 551 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMisses::total 551 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMissLatency::cpu.inst 37124500 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissLatency::total 37124500 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissRate::cpu.inst 0.980427 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.mshrMissRate::total 0.980427 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::cpu.inst 67376.588022 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::total 67376.588022 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.hits::cpu.data 2 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.hits::total 2 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.misses::cpu.data 2484075 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.misses::total 2484075 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.missLatency::cpu.data 200456767500 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.missLatency::total 200456767500 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.accesses::cpu.data 2484077 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.accesses::total 2484077 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.missRate::cpu.data 0.999999 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.missRate::total 0.999999 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.avgMissLatency::cpu.data 80696.745267 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMissLatency::total 80696.745267 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.mshrMisses::cpu.data 2484075 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMisses::total 2484075 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMissLatency::cpu.data 175616027500 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissLatency::total 175616027500 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissRate::cpu.data 0.999999 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.mshrMissRate::total 0.999999 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.avgMshrMissLatency::cpu.data 70696.749293 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMshrMissLatency::total 70696.749293 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.hits::cpu.data 3 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.hits::total 3 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.misses::cpu.data 726 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.misses::total 726 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.missLatency::cpu.data 55133500 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.missLatency::total 55133500 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.accesses::cpu.data 729 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.accesses::total 729 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.missRate::cpu.data 0.995885 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.missRate::total 0.995885 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.avgMissLatency::cpu.data 75941.460055 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMissLatency::total 75941.460055 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.mshrMisses::cpu.data 726 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMisses::total 726 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMissLatency::cpu.data 47873500 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissLatency::total 47873500 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissRate::cpu.data 0.995885 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.mshrMissRate::total 0.995885 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::cpu.data 65941.460055 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::total 65941.460055 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.UpgradeReq.hits::cpu.data 2 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.hits::total 2 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.UpgradeReq.accesses::total 2 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.WritebackClean.hits::writebacks 158 # number of WritebackClean hits (Count)
|
|
system.l2.WritebackClean.hits::total 158 # number of WritebackClean hits (Count)
|
|
system.l2.WritebackClean.accesses::writebacks 158 # number of WritebackClean accesses(hits+misses) (Count)
|
|
system.l2.WritebackClean.accesses::total 158 # number of WritebackClean accesses(hits+misses) (Count)
|
|
system.l2.WritebackDirty.hits::writebacks 2483079 # number of WritebackDirty hits (Count)
|
|
system.l2.WritebackDirty.hits::total 2483079 # number of WritebackDirty hits (Count)
|
|
system.l2.WritebackDirty.accesses::writebacks 2483079 # number of WritebackDirty accesses(hits+misses) (Count)
|
|
system.l2.WritebackDirty.accesses::total 2483079 # number of WritebackDirty accesses(hits+misses) (Count)
|
|
system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.l2.tags.tagsInUse 32569.685536 # Average ticks per tags in use ((Tick/Count))
|
|
system.l2.tags.totalRefs 4969308 # Total number of references to valid blocks. (Count)
|
|
system.l2.tags.sampledRefs 2485352 # Sample count of references to valid blocks. (Count)
|
|
system.l2.tags.avgRefs 1.999438 # Average number of references to valid blocks. ((Count/Count))
|
|
system.l2.tags.warmupTick 77000 # The tick when the warmup percentage was hit. (Tick)
|
|
system.l2.tags.occupancies::writebacks 0.011250 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu.inst 6.149205 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu.data 32563.525081 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.avgOccs::writebacks 0.000000 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu.inst 0.000188 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu.data 0.993760 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::total 0.993948 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.occupanciesTaskId::1024 32768 # Occupied blocks per task id (Count)
|
|
system.l2.tags.ageTaskId_1024::0 117 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::1 1071 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::2 10684 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::3 20896 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.l2.tags.tagAccesses 42239824 # Number of tag accesses (Count)
|
|
system.l2.tags.dataAccesses 42239824 # Number of data accesses (Count)
|
|
system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.mem_ctrls.avgPriority_writebacks::samples 2451329.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu.inst::samples 551.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu.data::samples 2484800.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (Second)
|
|
system.mem_ctrls.priorityMaxLatency 0.000071636500 # per QoS priority maximum request to response latency (Second)
|
|
system.mem_ctrls.numReadWriteTurnArounds 153205 # Number of turnarounds from READ to WRITE (Count)
|
|
system.mem_ctrls.numWriteReadTurnArounds 153206 # Number of turnarounds from WRITE to READ (Count)
|
|
system.mem_ctrls.numStayReadState 7319672 # Number of times bus staying in READ state (Count)
|
|
system.mem_ctrls.numStayWriteState 2299489 # Number of times bus staying in WRITE state (Count)
|
|
system.mem_ctrls.readReqs 2485351 # Number of read requests accepted (Count)
|
|
system.mem_ctrls.writeReqs 2451329 # Number of write requests accepted (Count)
|
|
system.mem_ctrls.readBursts 2485351 # Number of controller read bursts, including those serviced by the write queue (Count)
|
|
system.mem_ctrls.writeBursts 2451329 # Number of controller write bursts, including those merged in the write queue (Count)
|
|
system.mem_ctrls.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
|
|
system.mem_ctrls.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
|
|
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
|
|
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing ((Count/Tick))
|
|
system.mem_ctrls.avgWrQLen 25.92 # Average write queue length when enqueuing ((Count/Tick))
|
|
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry (Count)
|
|
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry (Count)
|
|
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::6 2485351 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::6 2451329 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.rdQLenPdf::0 2485046 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::1 222 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::2 61 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::3 20 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::17 151694 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::18 153205 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::19 153206 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::20 153207 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::21 153221 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::22 153206 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::23 153207 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::24 153207 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::25 154706 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::26 153206 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::27 153206 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::28 153207 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::29 153206 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::30 153206 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::31 153206 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::32 153206 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdPerTurnAround::samples 153206 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::mean 16.222282 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::gmean 16.001469 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::stdev 85.213802 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::0-2047 153205 100.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::total 153206 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.wrPerTurnAround::samples 153205 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::mean 16.000104 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::gmean 16.000096 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::stdev 0.017328 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::16 153199 100.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::17 1 0.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::19 5 0.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::total 153205 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
|
|
system.mem_ctrls.bytesReadSys 159062464 # Total read bytes from the system interface side (Byte)
|
|
system.mem_ctrls.bytesWrittenSys 156885056 # Total written bytes from the system interface side (Byte)
|
|
system.mem_ctrls.avgRdBWSys 758918403.15506685 # Average system read bandwidth in Byte/s ((Byte/Second))
|
|
system.mem_ctrls.avgWrBWSys 748529559.92441583 # Average system write bandwidth in Byte/s ((Byte/Second))
|
|
system.mem_ctrls.totGap 209590977500 # Total gap between requests (Tick)
|
|
system.mem_ctrls.avgGap 42455.86 # Average gap between requests ((Tick/Count))
|
|
system.mem_ctrls.requestorReadBytes::cpu.inst 35264 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu.data 159027200 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorWriteBytes::writebacks 156883072 # Per-requestor bytes write to memory (Byte)
|
|
system.mem_ctrls.requestorReadRate::cpu.inst 168251.502559775981 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu.data 758750151.652507066727 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorWriteRate::writebacks 748520093.868917942047 # Per-requestor bytes write to memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadAccesses::cpu.inst 551 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu.data 2484800 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorWriteAccesses::writebacks 2451329 # Per-requestor write serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu.inst 14470500 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu.data 74376814250 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorWriteTotalLat::writebacks 5103152395750 # Per-requestor write total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadAvgLat::cpu.inst 26262.25 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu.data 29932.72 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorWriteAvgLat::writebacks 2081790.08 # Per-requestor write average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.dram.bytesRead::cpu.inst 35264 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu.data 159027200 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::total 159062464 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::cpu.inst 35264 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::total 35264 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesWritten::writebacks 156885056 # Number of bytes written to this memory (Byte)
|
|
system.mem_ctrls.dram.bytesWritten::total 156885056 # Number of bytes written to this memory (Byte)
|
|
system.mem_ctrls.dram.numReads::cpu.inst 551 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu.data 2484800 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::total 2485351 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numWrites::writebacks 2451329 # Number of write requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numWrites::total 2451329 # Number of write requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.bwRead::cpu.inst 168252 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu.data 758750152 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::total 758918403 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::cpu.inst 168252 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::total 168252 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwWrite::writebacks 748529560 # Write bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwWrite::total 748529560 # Write bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::writebacks 748529560 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu.inst 168252 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu.data 758750152 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::total 1507447963 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.readBursts 2485351 # Number of DRAM read bursts (Count)
|
|
system.mem_ctrls.dram.writeBursts 2451298 # Number of DRAM write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::0 155449 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::1 155458 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::2 155324 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::3 155297 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::4 155380 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::5 155392 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::6 155285 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::7 155264 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::8 155314 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::9 155214 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::10 155173 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::11 155239 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::12 155292 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::13 155397 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::14 155471 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::15 155402 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::0 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::1 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::2 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::3 153225 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::4 153221 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::5 153274 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::6 153218 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::7 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::8 153237 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::9 153104 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::10 153109 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::11 153182 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::12 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::13 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::14 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::15 153216 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.totQLat 27790953500 # Total ticks spent queuing (Tick)
|
|
system.mem_ctrls.dram.totBusLat 12426755000 # Total ticks spent in databus transfers (Tick)
|
|
system.mem_ctrls.dram.totMemAccLat 74391284750 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
|
|
system.mem_ctrls.dram.avgQLat 11181.90 # Average queueing delay per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.avgBusLat 5000.00 # Average bus latency per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.avgMemAccLat 29931.90 # Average memory access latency per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.readRowHits 2287524 # Number of row buffer hits during reads (Count)
|
|
system.mem_ctrls.dram.writeRowHits 2278250 # Number of row buffer hits during writes (Count)
|
|
system.mem_ctrls.dram.readRowHitRate 92.04 # Row buffer hit rate for reads (Ratio)
|
|
system.mem_ctrls.dram.writeRowHitRate 92.94 # Row buffer hit rate for writes (Ratio)
|
|
system.mem_ctrls.dram.bytesPerActivate::samples 370874 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::mean 851.894196 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::gmean 743.949636 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::stdev 300.214771 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::0-127 6453 1.74% 1.74% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::128-255 24964 6.73% 8.47% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::256-383 22304 6.01% 14.48% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::384-511 7323 1.97% 16.46% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::512-639 6789 1.83% 18.29% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::640-767 13425 3.62% 21.91% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::768-895 21247 5.73% 27.64% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::896-1023 20721 5.59% 33.23% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::1024-1151 247648 66.77% 100.00% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::total 370874 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesRead 159062464 # Total bytes read (Byte)
|
|
system.mem_ctrls.dram.bytesWritten 156883072 # Total bytes written (Byte)
|
|
system.mem_ctrls.dram.avgRdBW 758.918403 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
|
|
system.mem_ctrls.dram.avgWrBW 748.520094 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
|
|
system.mem_ctrls.dram.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
|
|
system.mem_ctrls.dram.busUtil 11.78 # Data bus utilization in percentage (Ratio)
|
|
system.mem_ctrls.dram.busUtilRead 5.93 # Data bus utilization in percentage for reads (Ratio)
|
|
system.mem_ctrls.dram.busUtilWrite 5.85 # Data bus utilization in percentage for writes (Ratio)
|
|
system.mem_ctrls.dram.pageHitRate 92.49 # Row buffer hit rate, read and write combined (Ratio)
|
|
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.mem_ctrls.dram.rank0.actEnergy 1324220100 # Energy for activate commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.preEnergy 703839675 # Energy for precharge commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.readEnergy 8873941860 # Energy for read commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.writeEnergy 6398686440 # Energy for write commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.refreshEnergy 16544879520.000002 # Energy for refresh commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.actBackEnergy 50314495650 # Energy for active background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.preBackEnergy 38112840960 # Energy for precharge background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.totalEnergy 122272904205 # Total energy per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.averagePower 583.388154 # Core power per rank (mW) (Watt)
|
|
system.mem_ctrls.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE 97430171750 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::REF 6998680000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::ACT 105162144250 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.actEnergy 1323820260 # Energy for activate commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.preEnergy 703627155 # Energy for precharge commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.readEnergy 8871464280 # Energy for read commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.writeEnergy 6397078680 # Energy for write commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.refreshEnergy 16544879520.000002 # Energy for refresh commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.actBackEnergy 50307142080 # Energy for active background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.preBackEnergy 38119033440 # Energy for precharge background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.totalEnergy 122267045415 # Total energy per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.averagePower 583.360200 # Core power per rank (mW) (Watt)
|
|
system.mem_ctrls.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE 97446930250 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::REF 6998680000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::ACT 105145385750 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.membus.transDist::ReadResp 1277 # Transaction distribution (Count)
|
|
system.membus.transDist::WritebackDirty 2451329 # Transaction distribution (Count)
|
|
system.membus.transDist::CleanEvict 849 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadExReq 2484074 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadExResp 2484074 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadSharedReq 1277 # Transaction distribution (Count)
|
|
system.membus.pktCount_system.l2.mem_side_port::system.mem_ctrls.port 7422880 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktCount_system.l2.mem_side_port::total 7422880 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktCount::total 7422880 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktSize_system.l2.mem_side_port::system.mem_ctrls.port 315947520 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.pktSize_system.l2.mem_side_port::total 315947520 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.pktSize::total 315947520 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.snoops 0 # Total snoops (Count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (Byte)
|
|
system.membus.snoopFanout::samples 2485351 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::0 2485351 100.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::total 2485351 # Request fanout histogram (Count)
|
|
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.membus.reqLayer2.occupancy 14751409500 # Layer occupancy (ticks) (Tick)
|
|
system.membus.reqLayer2.utilization 0.1 # Layer utilization (Ratio)
|
|
system.membus.respLayer1.occupancy 13071126000 # Layer occupancy (ticks) (Tick)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (Ratio)
|
|
system.membus.snoop_filter.totRequests 4937529 # Total number of requests made to the snoop filter. (Count)
|
|
system.membus.snoop_filter.hitSingleRequests 2452178 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
|
|
system.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.tol2bus.transDist::ReadResp 1293 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::WritebackDirty 4934408 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::WritebackClean 158 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::CleanEvict 1957 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::UpgradeReq 2 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::UpgradeResp 2 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadExReq 2484077 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadExResp 2484076 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadCleanReq 564 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadSharedReq 729 # Transaction distribution (Count)
|
|
system.tol2bus.pktCount_system.cpu.icache.mem_side_port::system.l2.cpu_side_port 1284 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port 7453396 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount::total 7454680 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktSize_system.cpu.icache.mem_side_port::system.l2.cpu_side_port 46080 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port 317944576 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize::total 317990656 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.snoops 2452586 # Total snoops (Count)
|
|
system.tol2bus.snoopTraffic 156885184 # Total snoop traffic (Byte)
|
|
system.tol2bus.snoopFanout::samples 4937956 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::mean 0.000083 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::stdev 0.009134 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::0 4937544 99.99% 99.99% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::1 412 0.01% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::max_value 1 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::total 4937956 # Request fanout histogram (Count)
|
|
system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 209590996000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.tol2bus.reqLayer0.occupancy 4967892500 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer0.occupancy 846000 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer1.occupancy 3727208500 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.snoop_filter.totRequests 4969311 # Total number of requests made to the snoop filter. (Count)
|
|
system.tol2bus.snoop_filter.hitSingleRequests 2483939 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.hitMultiRequests 4 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.totSnoops 408 # Total number of snoops made to the snoop filter. (Count)
|
|
system.tol2bus.snoop_filter.hitSingleSnoops 408 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.voltage_domain.voltage 1 # Voltage in Volts (Volt)
|
|
system.workload.inst.arm 0 # number of arm instructions executed (Count)
|
|
system.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
|
|
|
|
---------- End Simulation Statistics ----------
|