1433 lines
182 KiB
Plaintext
1433 lines
182 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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simSeconds 0.209718 # Number of seconds simulated (Second)
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simTicks 209718110000 # Number of ticks simulated (Tick)
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finalTick 209718110000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
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simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
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hostSeconds 279.20 # Real time elapsed on the host (Second)
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hostTickRate 751138247 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
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hostMemory 670348 # Number of bytes of host memory used (Byte)
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simInsts 20000000 # Number of instructions simulated (Count)
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simOps 27556226 # Number of ops (including micro ops) simulated (Count)
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hostInstRate 71633 # Simulator instruction rate (inst/s) ((Count/Second))
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hostOpRate 98697 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
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system.clk_domain.clock 1000 # Clock period in ticks (Tick)
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system.cpu.numCycles 419436221 # Number of cpu cycles simulated (Cycle)
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system.cpu.cpi 20.971811 # CPI: cycles per instruction (core level) ((Cycle/Count))
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system.cpu.ipc 0.047683 # IPC: instructions per cycle (core level) ((Count/Cycle))
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system.cpu.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
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system.cpu.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
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system.cpu.instsAdded 30460560 # Number of instructions added to the IQ (excludes non-spec) (Count)
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system.cpu.nonSpecInstsAdded 103 # Number of non-speculative instructions added to the IQ (Count)
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system.cpu.instsIssued 30454266 # Number of instructions issued (Count)
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system.cpu.squashedInstsIssued 91 # Number of squashed instructions issued (Count)
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system.cpu.squashedInstsExamined 2904434 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
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system.cpu.squashedOperandsExamined 1084578 # Number of squashed operands that are examined and possibly removed from graph (Count)
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system.cpu.squashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed (Count)
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system.cpu.numIssuedDist::samples 419394733 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::mean 0.072615 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::stdev 0.477785 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::0 407823827 97.24% 97.24% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::1 3246803 0.77% 98.02% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::2 1041647 0.25% 98.26% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::3 4632595 1.10% 99.37% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::4 2280911 0.54% 99.91% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::5 236027 0.06% 99.97% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::6 26429 0.01% 99.97% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::7 87921 0.02% 100.00% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::8 18573 0.00% 100.00% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
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system.cpu.numIssuedDist::total 419394733 # Number of insts issued each cycle (Count)
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system.cpu.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IntAlu 24568 99.55% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IntMult 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IntDiv 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatAdd 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatCmp 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatCvt 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMult 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMultAcc 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatDiv 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMisc 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatSqrt 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAdd 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAddAcc 0 0.00% 99.55% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAlu 26 0.11% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdCvt 1 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMisc 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMult 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdMatMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShift 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShiftAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdDiv 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSqrt 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatAdd 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatAlu 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatCvt 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatDiv 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMisc 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMult 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatMatMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatSqrt 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdReduceAdd 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdReduceAlu 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdReduceCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatReduceAdd 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdFloatReduceCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAes 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdAesMix 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha1Hash 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha1Hash2 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha256Hash 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdSha256Hash2 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShaSigma2 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdShaSigma3 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::SimdPredAlu 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::Matrix 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MatrixMov 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MatrixOP 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MemRead 45 0.18% 99.84% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::MemWrite 27 0.11% 99.95% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMemRead 2 0.01% 99.96% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::FloatMemWrite 10 0.04% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIntegerArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorFloatArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorFloatConvert 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIntegerReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorFloatReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorMisc 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorIntegerExtension 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statFuBusy::VectorConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu.statIssuedInstType_0::No_OpClass 465 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::IntAlu 22182823 72.84% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::IntMult 47 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::IntDiv 83 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatAdd 168 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::FloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAdd 10 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAddAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdAlu 313 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdCmp 4 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdCvt 84 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMisc 257 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdShift 7 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdShiftAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdReduceAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
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system.cpu.statIssuedInstType_0::SimdAes 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::SimdAesMix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::SimdSha1Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::SimdSha256Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::SimdShaSigma2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::SimdShaSigma3 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::SimdPredAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::Matrix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::MatrixMov 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::MatrixOP 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::MemRead 2766380 9.08% 81.93% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::MemWrite 5502880 18.07% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::FloatMemRead 168 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::FloatMemWrite 577 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.statIssuedInstType_0::total 30454266 # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu.issueRate 0.072608 # Inst issue rate ((Count/Cycle))
|
|
system.cpu.fuBusy 24679 # FU busy when requested (Count)
|
|
system.cpu.fuBusyRate 0.000810 # FU busy rate (busy events/executed inst) ((Count/Count))
|
|
system.cpu.intInstQueueReads 480324469 # Number of integer instruction queue reads (Count)
|
|
system.cpu.intInstQueueWrites 33362986 # Number of integer instruction queue writes (Count)
|
|
system.cpu.intInstQueueWakeupAccesses 30188910 # Number of integer instruction queue wakeup accesses (Count)
|
|
system.cpu.fpInstQueueReads 3566 # Number of floating instruction queue reads (Count)
|
|
system.cpu.fpInstQueueWrites 2169 # Number of floating instruction queue writes (Count)
|
|
system.cpu.fpInstQueueWakeupAccesses 1727 # Number of floating instruction queue wakeup accesses (Count)
|
|
system.cpu.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
|
|
system.cpu.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
|
|
system.cpu.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
|
|
system.cpu.intAluAccesses 30476678 # Number of integer alu accesses (Count)
|
|
system.cpu.fpAluAccesses 1802 # Number of floating point alu accesses (Count)
|
|
system.cpu.vecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu.numSquashedInsts 940 # Number of squashed instructions skipped in execute (Count)
|
|
system.cpu.numSwp 0 # Number of swp insts executed (Count)
|
|
system.cpu.timesIdled 366 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
|
|
system.cpu.idleCycles 41488 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
|
|
system.cpu.MemDepUnit__0.insertedLoads 2767147 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__0.insertedStores 5503938 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__0.conflictingLoads 1787966 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__0.conflictingStores 230137 # Number of conflicting stores. (Count)
|
|
system.cpu.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu.branchPred.lookups 2864431 # Number of BP lookups (Count)
|
|
system.cpu.branchPred.condPredicted 2853201 # Number of conditional branches predicted (Count)
|
|
system.cpu.branchPred.condIncorrect 771 # Number of conditional branches incorrect (Count)
|
|
system.cpu.branchPred.BTBLookups 2838743 # Number of BTB lookups (Count)
|
|
system.cpu.branchPred.BTBUpdates 646 # Number of BTB updates (Count)
|
|
system.cpu.branchPred.BTBHits 2838323 # Number of BTB hits (Count)
|
|
system.cpu.branchPred.BTBHitRatio 0.999852 # BTB Hit Ratio (Ratio)
|
|
system.cpu.branchPred.RASUsed 2587 # Number of times the RAS was used to get a target. (Count)
|
|
system.cpu.branchPred.RASIncorrect 9 # Number of incorrect RAS predictions. (Count)
|
|
system.cpu.branchPred.indirectLookups 2386 # Number of indirect predictor lookups. (Count)
|
|
system.cpu.branchPred.indirectHits 2177 # Number of indirect target hits. (Count)
|
|
system.cpu.branchPred.indirectMisses 209 # Number of indirect misses. (Count)
|
|
system.cpu.branchPred.indirectMispredicted 63 # Number of mispredicted indirect branches. (Count)
|
|
system.cpu.branchPred.loop_predictor.correct 2504786 # Number of times the loop predictor is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.loop_predictor.wrong 1871 # Number of times the loop predictor is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.longestMatchProviderCorrect 1441773 # Number of times TAGE Longest Match is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.tage.altMatchProviderCorrect 54 # Number of times TAGE Alt Match is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.tage.bimodalAltMatchProviderCorrect 81 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct (Count)
|
|
system.cpu.branchPred.tage.bimodalProviderCorrect 1064348 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct (Count)
|
|
system.cpu.branchPred.tage.longestMatchProviderWrong 47 # Number of times TAGE Longest Match is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.altMatchProviderWrong 19 # Number of times TAGE Alt Match is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.bimodalAltMatchProviderWrong 29 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.bimodalProviderWrong 306 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong (Count)
|
|
system.cpu.branchPred.tage.altMatchProviderWouldHaveHit 9 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct (Count)
|
|
system.cpu.branchPred.tage.longestMatchProviderWouldHaveHit 37 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::0 0 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::1 1049928 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::2 388116 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::3 104 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::4 1306 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::5 1102 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::6 663 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::7 389 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::8 25 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::9 10 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::10 89 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::11 0 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.longestMatchProvider::12 161 # TAGE provider for longest match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::0 1052329 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::1 386989 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::2 146 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::3 1021 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::4 414 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::5 568 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::6 142 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::7 113 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::8 8 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::9 2 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::10 161 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::11 0 # TAGE provider for alt match (Count)
|
|
system.cpu.branchPred.tage.altMatchProvider::12 0 # TAGE provider for alt match (Count)
|
|
system.cpu.commit.commitSquashedInsts 2773101 # The number of squashed insts skipped by commit (Count)
|
|
system.cpu.commit.commitNonSpecStalls 42 # The number of times commit has been forced to stall to communicate backwards (Count)
|
|
system.cpu.commit.branchMispredicts 529 # The number of times a branch was mispredicted (Count)
|
|
system.cpu.commit.numCommittedDist::samples 419047696 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::mean 0.065759 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::stdev 0.457816 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::0 408755263 97.54% 97.54% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::1 3031744 0.72% 98.27% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::2 318407 0.08% 98.34% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::3 4464727 1.07% 99.41% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::4 1961203 0.47% 99.88% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::5 493407 0.12% 99.99% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::6 323 0.00% 99.99% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::7 1274 0.00% 99.99% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::8 21348 0.01% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.numCommittedDist::total 419047696 # Number of insts commited each cycle (Count)
|
|
system.cpu.commit.amos 0 # Number of atomic instructions committed (Count)
|
|
system.cpu.commit.membars 28 # Number of memory barriers committed (Count)
|
|
system.cpu.commit.functionCalls 2307 # Number of function calls committed. (Count)
|
|
system.cpu.commit.committedInstType_0::No_OpClass 250 0.00% 0.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IntAlu 20074104 72.85% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IntMult 41 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IntDiv 56 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatAdd 146 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAdd 10 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAlu 237 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdCmp 4 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdCvt 76 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMisc 235 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShift 3 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAes 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdAesMix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::Matrix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MatrixMov 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MatrixOP 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MemRead 2502668 9.08% 81.93% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::MemWrite 4977757 18.06% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMemRead 125 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu.commit.committedInstType_0::total 27556226 # Class of committed instruction (Count)
|
|
system.cpu.commit.commitEligibleSamples 21348 # number cycles where commit BW limit reached (Cycle)
|
|
system.cpu.commitStats0.numInsts 20000000 # Number of instructions committed (thread level) (Count)
|
|
system.cpu.commitStats0.numOps 27556226 # Number of ops (including micro ops) committed (thread level) (Count)
|
|
system.cpu.commitStats0.numInstsNotNOP 20000000 # Number of instructions committed excluding NOPs or prefetches (Count)
|
|
system.cpu.commitStats0.numOpsNotNOP 27556226 # Number of Ops (including micro ops) Simulated (Count)
|
|
system.cpu.commitStats0.cpi 20.971811 # CPI: cycles per instruction (thread level) ((Cycle/Count))
|
|
system.cpu.commitStats0.ipc 0.047683 # IPC: instructions per cycle (thread level) ((Count/Cycle))
|
|
system.cpu.commitStats0.numMemRefs 7481064 # Number of memory references committed (Count)
|
|
system.cpu.commitStats0.numFpInsts 1513 # Number of float instructions (Count)
|
|
system.cpu.commitStats0.numIntInsts 27555088 # Number of integer instructions (Count)
|
|
system.cpu.commitStats0.numLoadInsts 2502793 # Number of load instructions (Count)
|
|
system.cpu.commitStats0.numStoreInsts 4978271 # Number of store instructions (Count)
|
|
system.cpu.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
|
|
system.cpu.commitStats0.committedInstType::No_OpClass 250 0.00% 0.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IntAlu 20074104 72.85% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IntMult 41 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IntDiv 56 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatAdd 146 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAdd 10 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAlu 237 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdCmp 4 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdCvt 76 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMisc 235 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShift 3 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAes 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::Matrix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MatrixMov 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MatrixOP 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MemRead 2502668 9.08% 81.93% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::MemWrite 4977757 18.06% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMemRead 125 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedInstType::total 27556226 # Class of committed instruction. (Count)
|
|
system.cpu.commitStats0.committedControl::IsControl 2516676 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsDirectControl 2512216 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsIndirectControl 4460 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsCondControl 2506658 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsUncondControl 10018 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsCall 2307 # Class of control type instructions committed (Count)
|
|
system.cpu.commitStats0.committedControl::IsReturn 2304 # Class of control type instructions committed (Count)
|
|
system.cpu.dcache.demandHits::cpu.data 2508144 # number of demand (read+write) hits (Count)
|
|
system.cpu.dcache.demandHits::total 2508144 # number of demand (read+write) hits (Count)
|
|
system.cpu.dcache.overallHits::cpu.data 2508144 # number of overall hits (Count)
|
|
system.cpu.dcache.overallHits::total 2508144 # number of overall hits (Count)
|
|
system.cpu.dcache.demandMisses::cpu.data 2485889 # number of demand (read+write) misses (Count)
|
|
system.cpu.dcache.demandMisses::total 2485889 # number of demand (read+write) misses (Count)
|
|
system.cpu.dcache.overallMisses::cpu.data 2485889 # number of overall misses (Count)
|
|
system.cpu.dcache.overallMisses::total 2485889 # number of overall misses (Count)
|
|
system.cpu.dcache.demandMissLatency::cpu.data 206912572500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.dcache.demandMissLatency::total 206912572500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.dcache.overallMissLatency::cpu.data 206912572500 # number of overall miss ticks (Tick)
|
|
system.cpu.dcache.overallMissLatency::total 206912572500 # number of overall miss ticks (Tick)
|
|
system.cpu.dcache.demandAccesses::cpu.data 4994033 # number of demand (read+write) accesses (Count)
|
|
system.cpu.dcache.demandAccesses::total 4994033 # number of demand (read+write) accesses (Count)
|
|
system.cpu.dcache.overallAccesses::cpu.data 4994033 # number of overall (read+write) accesses (Count)
|
|
system.cpu.dcache.overallAccesses::total 4994033 # number of overall (read+write) accesses (Count)
|
|
system.cpu.dcache.demandMissRate::cpu.data 0.497772 # miss rate for demand accesses (Ratio)
|
|
system.cpu.dcache.demandMissRate::total 0.497772 # miss rate for demand accesses (Ratio)
|
|
system.cpu.dcache.overallMissRate::cpu.data 0.497772 # miss rate for overall accesses (Ratio)
|
|
system.cpu.dcache.overallMissRate::total 0.497772 # miss rate for overall accesses (Ratio)
|
|
system.cpu.dcache.demandAvgMissLatency::cpu.data 83234.839729 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.dcache.demandAvgMissLatency::total 83234.839729 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMissLatency::cpu.data 83234.839729 # average overall miss latency ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMissLatency::total 83234.839729 # average overall miss latency ((Tick/Count))
|
|
system.cpu.dcache.blockedCycles::no_mshrs 517 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dcache.blockedCauses::no_mshrs 10 # number of times access was blocked (Count)
|
|
system.cpu.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.dcache.avgBlocked::no_mshrs 51.700000 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dcache.writebacks::writebacks 2483627 # number of writebacks (Count)
|
|
system.cpu.dcache.writebacks::total 2483627 # number of writebacks (Count)
|
|
system.cpu.dcache.demandMshrHits::cpu.data 1044 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.dcache.demandMshrHits::total 1044 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.dcache.overallMshrHits::cpu.data 1044 # number of overall MSHR hits (Count)
|
|
system.cpu.dcache.overallMshrHits::total 1044 # number of overall MSHR hits (Count)
|
|
system.cpu.dcache.demandMshrMisses::cpu.data 2484845 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.dcache.demandMshrMisses::total 2484845 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.dcache.overallMshrMisses::cpu.data 2484845 # number of overall MSHR misses (Count)
|
|
system.cpu.dcache.overallMshrMisses::total 2484845 # number of overall MSHR misses (Count)
|
|
system.cpu.dcache.demandMshrMissLatency::cpu.data 204350649000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.dcache.demandMshrMissLatency::total 204350649000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.dcache.overallMshrMissLatency::cpu.data 204350649000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.dcache.overallMshrMissLatency::total 204350649000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.dcache.demandMshrMissRate::cpu.data 0.497563 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.dcache.demandMshrMissRate::total 0.497563 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.dcache.overallMshrMissRate::cpu.data 0.497563 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.dcache.overallMshrMissRate::total 0.497563 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.dcache.demandAvgMshrMissLatency::cpu.data 82238.791152 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.demandAvgMshrMissLatency::total 82238.791152 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMshrMissLatency::cpu.data 82238.791152 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.overallAvgMshrMissLatency::total 82238.791152 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.replacements 2484331 # number of replacements (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.hits::cpu.data 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.hits::total 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.misses::cpu.data 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.misses::total 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.missLatency::cpu.data 86500 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.missLatency::total 86500 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.accesses::cpu.data 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.accesses::total 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.missRate::cpu.data 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.missRate::total 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::cpu.data 86500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::total 86500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMisses::cpu.data 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMisses::total 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::cpu.data 224000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::total 224000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::cpu.data 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::total 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu.data 224000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::total 224000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.LockedRMWWriteReq.hits::cpu.data 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu.dcache.LockedRMWWriteReq.hits::total 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu.dcache.LockedRMWWriteReq.accesses::cpu.data 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.LockedRMWWriteReq.accesses::total 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.ReadReq.hits::cpu.data 14016 # number of ReadReq hits (Count)
|
|
system.cpu.dcache.ReadReq.hits::total 14016 # number of ReadReq hits (Count)
|
|
system.cpu.dcache.ReadReq.misses::cpu.data 1791 # number of ReadReq misses (Count)
|
|
system.cpu.dcache.ReadReq.misses::total 1791 # number of ReadReq misses (Count)
|
|
system.cpu.dcache.ReadReq.missLatency::cpu.data 134425000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.missLatency::total 134425000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.accesses::cpu.data 15807 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.ReadReq.accesses::total 15807 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.ReadReq.missRate::cpu.data 0.113304 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.missRate::total 0.113304 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.avgMissLatency::cpu.data 75055.834729 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.ReadReq.avgMissLatency::total 75055.834729 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.ReadReq.mshrHits::cpu.data 1044 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.dcache.ReadReq.mshrHits::total 1044 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.dcache.ReadReq.mshrMisses::cpu.data 747 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.dcache.ReadReq.mshrMisses::total 747 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.dcache.ReadReq.mshrMissLatency::cpu.data 56598500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.mshrMissLatency::total 56598500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.ReadReq.mshrMissRate::cpu.data 0.047258 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.mshrMissRate::total 0.047258 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.dcache.ReadReq.avgMshrMissLatency::cpu.data 75767.737617 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.ReadReq.avgMshrMissLatency::total 75767.737617 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.hits::cpu.data 2494128 # number of WriteReq hits (Count)
|
|
system.cpu.dcache.WriteReq.hits::total 2494128 # number of WriteReq hits (Count)
|
|
system.cpu.dcache.WriteReq.misses::cpu.data 2484098 # number of WriteReq misses (Count)
|
|
system.cpu.dcache.WriteReq.misses::total 2484098 # number of WriteReq misses (Count)
|
|
system.cpu.dcache.WriteReq.missLatency::cpu.data 206778147500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.missLatency::total 206778147500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.accesses::cpu.data 4978226 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.WriteReq.accesses::total 4978226 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu.dcache.WriteReq.missRate::cpu.data 0.498993 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.missRate::total 0.498993 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.avgMissLatency::cpu.data 83240.736678 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.avgMissLatency::total 83240.736678 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.mshrMisses::cpu.data 2484098 # number of WriteReq MSHR misses (Count)
|
|
system.cpu.dcache.WriteReq.mshrMisses::total 2484098 # number of WriteReq MSHR misses (Count)
|
|
system.cpu.dcache.WriteReq.mshrMissLatency::cpu.data 204294050500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.mshrMissLatency::total 204294050500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu.dcache.WriteReq.mshrMissRate::cpu.data 0.498993 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.mshrMissRate::total 0.498993 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu.dcache.WriteReq.avgMshrMissLatency::cpu.data 82240.737080 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.WriteReq.avgMshrMissLatency::total 82240.737080 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.dcache.tags.tagsInUse 511.907210 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.dcache.tags.totalRefs 4993016 # Total number of references to valid blocks. (Count)
|
|
system.cpu.dcache.tags.sampledRefs 2484843 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.dcache.tags.avgRefs 2.009389 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.dcache.tags.warmupTick 176500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.dcache.tags.occupancies::cpu.data 511.907210 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu.dcache.tags.avgOccs::cpu.data 0.999819 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.dcache.tags.avgOccs::total 0.999819 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.dcache.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
|
|
system.cpu.dcache.tags.ageTaskId_1024::0 119 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.dcache.tags.ageTaskId_1024::1 392 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.dcache.tags.ageTaskId_1024::4 1 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu.dcache.tags.tagAccesses 12472965 # Number of tag accesses (Count)
|
|
system.cpu.dcache.tags.dataAccesses 12472965 # Number of data accesses (Count)
|
|
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.decode.idleCycles 1292122 # Number of cycles decode is idle (Cycle)
|
|
system.cpu.decode.blockedCycles 414141548 # Number of cycles decode is blocked (Cycle)
|
|
system.cpu.decode.runCycles 505953 # Number of cycles decode is running (Cycle)
|
|
system.cpu.decode.unblockCycles 3438123 # Number of cycles decode is unblocking (Cycle)
|
|
system.cpu.decode.squashCycles 16987 # Number of cycles decode is squashing (Cycle)
|
|
system.cpu.decode.branchResolved 2772792 # Number of times decode resolved a branch (Count)
|
|
system.cpu.decode.branchMispred 269 # Number of times decode detected a branch misprediction (Count)
|
|
system.cpu.decode.decodedInsts 30645232 # Number of instructions handled by decode (Count)
|
|
system.cpu.decode.squashedInsts 1175 # Number of squashed instructions handled by decode (Count)
|
|
system.cpu.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.dtb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.executeStats0.numInsts 30453326 # Number of executed instructions (Count)
|
|
system.cpu.executeStats0.numNop 0 # Number of nop insts executed (Count)
|
|
system.cpu.executeStats0.numBranches 2779847 # Number of branches executed (Count)
|
|
system.cpu.executeStats0.numLoadInsts 2766354 # Number of load instructions executed (Count)
|
|
system.cpu.executeStats0.numStoreInsts 5503369 # Number of stores executed (Count)
|
|
system.cpu.executeStats0.instRate 0.072605 # Inst execution rate ((Count/Cycle))
|
|
system.cpu.executeStats0.numCCRegReads 13888132 # Number of times the CC registers were read (Count)
|
|
system.cpu.executeStats0.numCCRegWrites 16559439 # Number of times the CC registers were written (Count)
|
|
system.cpu.executeStats0.numFpRegReads 2132 # Number of times the floating registers were read (Count)
|
|
system.cpu.executeStats0.numFpRegWrites 1088 # Number of times the floating registers were written (Count)
|
|
system.cpu.executeStats0.numIntRegReads 49750204 # Number of times the integer registers were read (Count)
|
|
system.cpu.executeStats0.numIntRegWrites 19398105 # Number of times the integer registers were written (Count)
|
|
system.cpu.executeStats0.numMemRefs 8269723 # Number of memory refs (Count)
|
|
system.cpu.executeStats0.numMiscRegReads 13828722 # Number of times the Misc registers were read (Count)
|
|
system.cpu.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
|
|
system.cpu.fetch.predictedBranches 2843087 # Number of branches that fetch has predicted taken (Count)
|
|
system.cpu.fetch.cycles 419337815 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
|
|
system.cpu.fetch.squashCycles 34504 # Number of cycles fetch has spent squashing (Cycle)
|
|
system.cpu.fetch.miscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
|
|
system.cpu.fetch.pendingTrapStallCycles 152 # Number of stall cycles due to pending traps (Cycle)
|
|
system.cpu.fetch.cacheLines 19545 # Number of cache lines fetched (Count)
|
|
system.cpu.fetch.icacheSquashes 419 # Number of outstanding Icache misses that were squashed (Count)
|
|
system.cpu.fetch.nisnDist::samples 419394733 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::mean 0.074962 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::stdev 0.686743 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::0 413043215 98.49% 98.49% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::1 655796 0.16% 98.64% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::2 655114 0.16% 98.80% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::3 1538015 0.37% 99.16% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::4 316752 0.08% 99.24% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::5 311854 0.07% 99.31% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::6 313975 0.07% 99.39% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::7 331787 0.08% 99.47% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::8 2228225 0.53% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetch.nisnDist::total 419394733 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu.fetchStats0.numInsts 22835393 # Number of instructions fetched (thread level) (Count)
|
|
system.cpu.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
|
|
system.cpu.fetchStats0.fetchRate 0.054443 # Number of inst fetches per cycle ((Count/Cycle))
|
|
system.cpu.fetchStats0.numBranches 2864431 # Number of branches fetched (Count)
|
|
system.cpu.fetchStats0.branchRate 0.006829 # Number of branch fetches per cycle (Ratio)
|
|
system.cpu.fetchStats0.icacheStallCycles 39487 # ICache total stall cycles (Cycle)
|
|
system.cpu.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
|
|
system.cpu.icache.demandHits::cpu.inst 18791 # number of demand (read+write) hits (Count)
|
|
system.cpu.icache.demandHits::total 18791 # number of demand (read+write) hits (Count)
|
|
system.cpu.icache.overallHits::cpu.inst 18791 # number of overall hits (Count)
|
|
system.cpu.icache.overallHits::total 18791 # number of overall hits (Count)
|
|
system.cpu.icache.demandMisses::cpu.inst 754 # number of demand (read+write) misses (Count)
|
|
system.cpu.icache.demandMisses::total 754 # number of demand (read+write) misses (Count)
|
|
system.cpu.icache.overallMisses::cpu.inst 754 # number of overall misses (Count)
|
|
system.cpu.icache.overallMisses::total 754 # number of overall misses (Count)
|
|
system.cpu.icache.demandMissLatency::cpu.inst 55271000 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.icache.demandMissLatency::total 55271000 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu.icache.overallMissLatency::cpu.inst 55271000 # number of overall miss ticks (Tick)
|
|
system.cpu.icache.overallMissLatency::total 55271000 # number of overall miss ticks (Tick)
|
|
system.cpu.icache.demandAccesses::cpu.inst 19545 # number of demand (read+write) accesses (Count)
|
|
system.cpu.icache.demandAccesses::total 19545 # number of demand (read+write) accesses (Count)
|
|
system.cpu.icache.overallAccesses::cpu.inst 19545 # number of overall (read+write) accesses (Count)
|
|
system.cpu.icache.overallAccesses::total 19545 # number of overall (read+write) accesses (Count)
|
|
system.cpu.icache.demandMissRate::cpu.inst 0.038578 # miss rate for demand accesses (Ratio)
|
|
system.cpu.icache.demandMissRate::total 0.038578 # miss rate for demand accesses (Ratio)
|
|
system.cpu.icache.overallMissRate::cpu.inst 0.038578 # miss rate for overall accesses (Ratio)
|
|
system.cpu.icache.overallMissRate::total 0.038578 # miss rate for overall accesses (Ratio)
|
|
system.cpu.icache.demandAvgMissLatency::cpu.inst 73303.713528 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.icache.demandAvgMissLatency::total 73303.713528 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu.icache.overallAvgMissLatency::cpu.inst 73303.713528 # average overall miss latency ((Tick/Count))
|
|
system.cpu.icache.overallAvgMissLatency::total 73303.713528 # average overall miss latency ((Tick/Count))
|
|
system.cpu.icache.blockedCycles::no_mshrs 259 # number of cycles access was blocked (Cycle)
|
|
system.cpu.icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.icache.blockedCauses::no_mshrs 5 # number of times access was blocked (Count)
|
|
system.cpu.icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.icache.avgBlocked::no_mshrs 51.800000 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.icache.writebacks::writebacks 169 # number of writebacks (Count)
|
|
system.cpu.icache.writebacks::total 169 # number of writebacks (Count)
|
|
system.cpu.icache.demandMshrHits::cpu.inst 176 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.icache.demandMshrHits::total 176 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu.icache.overallMshrHits::cpu.inst 176 # number of overall MSHR hits (Count)
|
|
system.cpu.icache.overallMshrHits::total 176 # number of overall MSHR hits (Count)
|
|
system.cpu.icache.demandMshrMisses::cpu.inst 578 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.icache.demandMshrMisses::total 578 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu.icache.overallMshrMisses::cpu.inst 578 # number of overall MSHR misses (Count)
|
|
system.cpu.icache.overallMshrMisses::total 578 # number of overall MSHR misses (Count)
|
|
system.cpu.icache.demandMshrMissLatency::cpu.inst 45191500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.icache.demandMshrMissLatency::total 45191500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu.icache.overallMshrMissLatency::cpu.inst 45191500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.icache.overallMshrMissLatency::total 45191500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu.icache.demandMshrMissRate::cpu.inst 0.029573 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.icache.demandMshrMissRate::total 0.029573 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu.icache.overallMshrMissRate::cpu.inst 0.029573 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.icache.overallMshrMissRate::total 0.029573 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu.icache.demandAvgMshrMissLatency::cpu.inst 78185.986159 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.demandAvgMshrMissLatency::total 78185.986159 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.overallAvgMshrMissLatency::cpu.inst 78185.986159 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.overallAvgMshrMissLatency::total 78185.986159 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.replacements 169 # number of replacements (Count)
|
|
system.cpu.icache.ReadReq.hits::cpu.inst 18791 # number of ReadReq hits (Count)
|
|
system.cpu.icache.ReadReq.hits::total 18791 # number of ReadReq hits (Count)
|
|
system.cpu.icache.ReadReq.misses::cpu.inst 754 # number of ReadReq misses (Count)
|
|
system.cpu.icache.ReadReq.misses::total 754 # number of ReadReq misses (Count)
|
|
system.cpu.icache.ReadReq.missLatency::cpu.inst 55271000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.missLatency::total 55271000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.accesses::cpu.inst 19545 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.icache.ReadReq.accesses::total 19545 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu.icache.ReadReq.missRate::cpu.inst 0.038578 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.missRate::total 0.038578 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.avgMissLatency::cpu.inst 73303.713528 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.icache.ReadReq.avgMissLatency::total 73303.713528 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu.icache.ReadReq.mshrHits::cpu.inst 176 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.icache.ReadReq.mshrHits::total 176 # number of ReadReq MSHR hits (Count)
|
|
system.cpu.icache.ReadReq.mshrMisses::cpu.inst 578 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.icache.ReadReq.mshrMisses::total 578 # number of ReadReq MSHR misses (Count)
|
|
system.cpu.icache.ReadReq.mshrMissLatency::cpu.inst 45191500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.mshrMissLatency::total 45191500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu.icache.ReadReq.mshrMissRate::cpu.inst 0.029573 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.mshrMissRate::total 0.029573 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu.icache.ReadReq.avgMshrMissLatency::cpu.inst 78185.986159 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.ReadReq.avgMshrMissLatency::total 78185.986159 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.icache.tags.tagsInUse 406.959236 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.icache.tags.totalRefs 19369 # Total number of references to valid blocks. (Count)
|
|
system.cpu.icache.tags.sampledRefs 578 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.icache.tags.avgRefs 33.510381 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.icache.tags.warmupTick 87500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.icache.tags.occupancies::cpu.inst 406.959236 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu.icache.tags.avgOccs::cpu.inst 0.794842 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.icache.tags.avgOccs::total 0.794842 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu.icache.tags.occupanciesTaskId::1024 407 # Occupied blocks per task id (Count)
|
|
system.cpu.icache.tags.ageTaskId_1024::4 407 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu.icache.tags.ratioOccsTaskId::1024 0.794922 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu.icache.tags.tagAccesses 39668 # Number of tag accesses (Count)
|
|
system.cpu.icache.tags.dataAccesses 39668 # Number of data accesses (Count)
|
|
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
|
|
system.cpu.iew.squashCycles 16987 # Number of cycles IEW is squashing (Cycle)
|
|
system.cpu.iew.blockCycles 400658 # Number of cycles IEW is blocking (Cycle)
|
|
system.cpu.iew.unblockCycles 226698791 # Number of cycles IEW is unblocking (Cycle)
|
|
system.cpu.iew.dispatchedInsts 30460663 # Number of instructions dispatched to IQ (Count)
|
|
system.cpu.iew.dispSquashedInsts 67 # Number of squashed instructions skipped by dispatch (Count)
|
|
system.cpu.iew.dispLoadInsts 2767147 # Number of dispatched load instructions (Count)
|
|
system.cpu.iew.dispStoreInsts 5503938 # Number of dispatched store instructions (Count)
|
|
system.cpu.iew.dispNonSpecInsts 35 # Number of dispatched non-speculative instructions (Count)
|
|
system.cpu.iew.iqFullEvents 1627 # Number of times the IQ has become full, causing a stall (Count)
|
|
system.cpu.iew.lsqFullEvents 226713542 # Number of times the LSQ has become full, causing a stall (Count)
|
|
system.cpu.iew.memOrderViolationEvents 61 # Number of memory order violations (Count)
|
|
system.cpu.iew.predictedTakenIncorrect 73 # Number of branches that were predicted taken incorrectly (Count)
|
|
system.cpu.iew.predictedNotTakenIncorrect 527 # Number of branches that were predicted not taken incorrectly (Count)
|
|
system.cpu.iew.branchMispredicts 600 # Number of branch mispredicts detected at execute (Count)
|
|
system.cpu.iew.instsToCommit 30453042 # Cumulative count of insts sent to commit (Count)
|
|
system.cpu.iew.writebackCount 30190637 # Cumulative count of insts written-back (Count)
|
|
system.cpu.iew.producerInst 12047304 # Number of instructions producing a value (Count)
|
|
system.cpu.iew.consumerInst 19244877 # Number of instructions consuming a value (Count)
|
|
system.cpu.iew.wbRate 0.071979 # Insts written-back per cycle ((Count/Cycle))
|
|
system.cpu.iew.wbFanout 0.626001 # Average fanout of values written-back ((Count/Count))
|
|
system.cpu.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
|
|
system.cpu.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu.itb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.lsq0.forwLoads 2750445 # Number of loads that had data forwarded from stores (Count)
|
|
system.cpu.lsq0.squashedLoads 264353 # Number of loads squashed (Count)
|
|
system.cpu.lsq0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed (Count)
|
|
system.cpu.lsq0.memOrderViolation 61 # Number of memory ordering violations (Count)
|
|
system.cpu.lsq0.squashedStores 525667 # Number of stores squashed (Count)
|
|
system.cpu.lsq0.rescheduledLoads 1 # Number of loads that were rescheduled (Count)
|
|
system.cpu.lsq0.blockedByCache 9 # Number of times an access to memory failed due to the cache being blocked (Count)
|
|
system.cpu.lsq0.loadToUse::samples 2502793 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::mean 2.104961 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::stdev 4.105687 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::0-9 2501141 99.93% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::10-19 4 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::20-29 20 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::30-39 4 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::40-49 1 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::100-109 1 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::110-119 8 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::120-129 28 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::130-139 46 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::140-149 1344 0.05% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::150-159 27 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::160-169 23 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::170-179 77 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::180-189 3 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::190-199 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::200-209 35 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::210-219 7 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::220-229 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::overflows 21 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::max_value 704 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.lsq0.loadToUse::total 2502793 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu.mmu.dtb.rdAccesses 2766340 # TLB accesses on read requests (Count)
|
|
system.cpu.mmu.dtb.wrAccesses 5503369 # TLB accesses on write requests (Count)
|
|
system.cpu.mmu.dtb.rdMisses 94 # TLB misses on read requests (Count)
|
|
system.cpu.mmu.dtb.wrMisses 300974 # TLB misses on write requests (Count)
|
|
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
|
|
system.cpu.mmu.itb.wrAccesses 19572 # TLB accesses on write requests (Count)
|
|
system.cpu.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
|
|
system.cpu.mmu.itb.wrMisses 70 # TLB misses on write requests (Count)
|
|
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.power_state.pwrStateResidencyTicks::ON 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu.rename.squashCycles 16987 # Number of cycles rename is squashing (Cycle)
|
|
system.cpu.rename.idleCycles 2275176 # Number of cycles rename is idle (Cycle)
|
|
system.cpu.rename.blockCycles 227103106 # Number of cycles rename is blocking (Cycle)
|
|
system.cpu.rename.serializeStallCycles 1088 # count of cycles rename stalled for serializing inst (Cycle)
|
|
system.cpu.rename.runCycles 2944272 # Number of cycles rename is running (Cycle)
|
|
system.cpu.rename.unblockCycles 187054104 # Number of cycles rename is unblocking (Cycle)
|
|
system.cpu.rename.renamedInsts 30512529 # Number of instructions processed by rename (Count)
|
|
system.cpu.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full (Count)
|
|
system.cpu.rename.IQFullEvents 10649 # Number of times rename has blocked due to IQ full (Count)
|
|
system.cpu.rename.SQFullEvents 186354255 # Number of times rename has blocked due to SQ full (Count)
|
|
system.cpu.rename.renamedOperands 63786211 # Number of destination operands rename has renamed (Count)
|
|
system.cpu.rename.lookups 124732703 # Number of register rename lookups that rename has made (Count)
|
|
system.cpu.rename.intLookups 49881839 # Number of integer rename lookups (Count)
|
|
system.cpu.rename.fpLookups 2327 # Number of floating rename lookups (Count)
|
|
system.cpu.rename.committedMaps 57521754 # Number of HB maps that are committed (Count)
|
|
system.cpu.rename.undoneMaps 6264442 # Number of HB maps that are undone due to squashing (Count)
|
|
system.cpu.rename.serializing 45 # count of serializing insts renamed (Count)
|
|
system.cpu.rename.tempSerializing 45 # count of temporary serializing insts renamed (Count)
|
|
system.cpu.rename.skidInsts 18601665 # count of insts added to the skid buffer (Count)
|
|
system.cpu.rob.reads 449142449 # The number of ROB reads (Count)
|
|
system.cpu.rob.writes 61005710 # The number of ROB writes (Count)
|
|
system.cpu.thread_0.numInsts 20000000 # Number of Instructions committed (Count)
|
|
system.cpu.thread_0.numOps 27556226 # Number of Ops committed (Count)
|
|
system.cpu.thread_0.numMemRefs 0 # Number of Memory References (Count)
|
|
system.cpu.workload.numSyscalls 14 # Number of system calls (Count)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks (Tick)
|
|
system.cpu_voltage_domain.voltage 1 # Voltage in Volts (Volt)
|
|
system.l2.demandHits::cpu.inst 11 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu.data 26 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::total 37 # number of demand (read+write) hits (Count)
|
|
system.l2.overallHits::cpu.inst 11 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu.data 26 # number of overall hits (Count)
|
|
system.l2.overallHits::total 37 # number of overall hits (Count)
|
|
system.l2.demandMisses::cpu.inst 565 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu.data 2484818 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::total 2485383 # number of demand (read+write) misses (Count)
|
|
system.l2.overallMisses::cpu.inst 565 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu.data 2484818 # number of overall misses (Count)
|
|
system.l2.overallMisses::total 2485383 # number of overall misses (Count)
|
|
system.l2.demandMissLatency::cpu.inst 44200500 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu.data 200623147000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::total 200667347500 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu.inst 44200500 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu.data 200623147000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::total 200667347500 # number of overall miss ticks (Tick)
|
|
system.l2.demandAccesses::cpu.inst 576 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu.data 2484844 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::total 2485420 # number of demand (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu.inst 576 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu.data 2484844 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::total 2485420 # number of overall (read+write) accesses (Count)
|
|
system.l2.demandMissRate::cpu.inst 0.980903 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu.data 0.999990 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::total 0.999985 # miss rate for demand accesses (Ratio)
|
|
system.l2.overallMissRate::cpu.inst 0.980903 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu.data 0.999990 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::total 0.999985 # miss rate for overall accesses (Ratio)
|
|
system.l2.demandAvgMissLatency::cpu.inst 78230.973451 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu.data 80739.574086 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::total 80739.003807 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu.inst 78230.973451 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu.data 80739.574086 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::total 80739.003807 # average overall miss latency ((Tick/Count))
|
|
system.l2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.l2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.l2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.l2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.l2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.l2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.l2.writebacks::writebacks 2467729 # number of writebacks (Count)
|
|
system.l2.writebacks::total 2467729 # number of writebacks (Count)
|
|
system.l2.demandMshrMisses::cpu.inst 565 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu.data 2484818 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::total 2485383 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu.inst 565 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu.data 2484818 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::total 2485383 # number of overall MSHR misses (Count)
|
|
system.l2.demandMshrMissLatency::cpu.inst 38550500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu.data 175774977000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::total 175813527500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu.inst 38550500 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu.data 175774977000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::total 175813527500 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissRate::cpu.inst 0.980903 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu.data 0.999990 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::total 0.999985 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu.inst 0.980903 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu.data 0.999990 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::total 0.999985 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.demandAvgMshrMissLatency::cpu.inst 68230.973451 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu.data 70739.578110 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::total 70739.007831 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu.inst 68230.973451 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu.data 70739.578110 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::total 70739.007831 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.replacements 2469000 # number of replacements (Count)
|
|
system.l2.ReadCleanReq.hits::cpu.inst 11 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.hits::total 11 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.misses::cpu.inst 565 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.misses::total 565 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.missLatency::cpu.inst 44200500 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.missLatency::total 44200500 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.accesses::cpu.inst 576 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.accesses::total 576 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.missRate::cpu.inst 0.980903 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.missRate::total 0.980903 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.avgMissLatency::cpu.inst 78230.973451 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMissLatency::total 78230.973451 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.mshrMisses::cpu.inst 565 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMisses::total 565 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMissLatency::cpu.inst 38550500 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissLatency::total 38550500 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissRate::cpu.inst 0.980903 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.mshrMissRate::total 0.980903 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::cpu.inst 68230.973451 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::total 68230.973451 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.hits::cpu.data 7 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.hits::total 7 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.misses::cpu.data 2484090 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.misses::total 2484090 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.missLatency::cpu.data 200567892000 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.missLatency::total 200567892000 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.accesses::cpu.data 2484097 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.accesses::total 2484097 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.missRate::cpu.data 0.999997 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.missRate::total 0.999997 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.avgMissLatency::cpu.data 80740.992476 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMissLatency::total 80740.992476 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.mshrMisses::cpu.data 2484090 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMisses::total 2484090 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMissLatency::cpu.data 175727002000 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissLatency::total 175727002000 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissRate::cpu.data 0.999997 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.mshrMissRate::total 0.999997 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.avgMshrMissLatency::cpu.data 70740.996502 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMshrMissLatency::total 70740.996502 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.hits::cpu.data 19 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.hits::total 19 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.misses::cpu.data 728 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.misses::total 728 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.missLatency::cpu.data 55255000 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.missLatency::total 55255000 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.accesses::cpu.data 747 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.accesses::total 747 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.missRate::cpu.data 0.974565 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.missRate::total 0.974565 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.avgMissLatency::cpu.data 75899.725275 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMissLatency::total 75899.725275 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.mshrMisses::cpu.data 728 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMisses::total 728 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMissLatency::cpu.data 47975000 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissLatency::total 47975000 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissRate::cpu.data 0.974565 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.mshrMissRate::total 0.974565 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::cpu.data 65899.725275 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::total 65899.725275 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.UpgradeReq.hits::cpu.data 2 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.hits::total 2 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.UpgradeReq.accesses::total 2 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.WritebackClean.hits::writebacks 169 # number of WritebackClean hits (Count)
|
|
system.l2.WritebackClean.hits::total 169 # number of WritebackClean hits (Count)
|
|
system.l2.WritebackClean.accesses::writebacks 169 # number of WritebackClean accesses(hits+misses) (Count)
|
|
system.l2.WritebackClean.accesses::total 169 # number of WritebackClean accesses(hits+misses) (Count)
|
|
system.l2.WritebackDirty.hits::writebacks 2483627 # number of WritebackDirty hits (Count)
|
|
system.l2.WritebackDirty.hits::total 2483627 # number of WritebackDirty hits (Count)
|
|
system.l2.WritebackDirty.accesses::writebacks 2483627 # number of WritebackDirty accesses(hits+misses) (Count)
|
|
system.l2.WritebackDirty.accesses::total 2483627 # number of WritebackDirty accesses(hits+misses) (Count)
|
|
system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.l2.tags.tagsInUse 16334.589564 # Average ticks per tags in use ((Tick/Count))
|
|
system.l2.tags.totalRefs 4969921 # Total number of references to valid blocks. (Count)
|
|
system.l2.tags.sampledRefs 2485384 # Sample count of references to valid blocks. (Count)
|
|
system.l2.tags.avgRefs 1.999659 # Average number of references to valid blocks. ((Count/Count))
|
|
system.l2.tags.warmupTick 77000 # The tick when the warmup percentage was hit. (Tick)
|
|
system.l2.tags.occupancies::writebacks 0.012184 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu.inst 3.080418 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu.data 16331.496963 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.avgOccs::writebacks 0.000001 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu.inst 0.000188 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu.data 0.996795 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::total 0.996984 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.occupanciesTaskId::1024 16384 # Occupied blocks per task id (Count)
|
|
system.l2.tags.ageTaskId_1024::0 119 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::1 1068 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::2 10684 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::3 4513 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.l2.tags.tagAccesses 42244760 # Number of tag accesses (Count)
|
|
system.l2.tags.dataAccesses 42244760 # Number of data accesses (Count)
|
|
system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.mem_ctrls.avgPriority_writebacks::samples 2467729.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu.inst::samples 565.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu.data::samples 2484817.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (Second)
|
|
system.mem_ctrls.priorityMaxLatency 0.000624604750 # per QoS priority maximum request to response latency (Second)
|
|
system.mem_ctrls.numReadWriteTurnArounds 154231 # Number of turnarounds from READ to WRITE (Count)
|
|
system.mem_ctrls.numWriteReadTurnArounds 154231 # Number of turnarounds from WRITE to READ (Count)
|
|
system.mem_ctrls.numStayReadState 7335152 # Number of times bus staying in READ state (Count)
|
|
system.mem_ctrls.numStayWriteState 2314778 # Number of times bus staying in WRITE state (Count)
|
|
system.mem_ctrls.readReqs 2485382 # Number of read requests accepted (Count)
|
|
system.mem_ctrls.writeReqs 2467729 # Number of write requests accepted (Count)
|
|
system.mem_ctrls.readBursts 2485382 # Number of controller read bursts, including those serviced by the write queue (Count)
|
|
system.mem_ctrls.writeBursts 2467729 # Number of controller write bursts, including those merged in the write queue (Count)
|
|
system.mem_ctrls.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
|
|
system.mem_ctrls.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
|
|
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
|
|
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing ((Count/Tick))
|
|
system.mem_ctrls.avgWrQLen 26.09 # Average write queue length when enqueuing ((Count/Tick))
|
|
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry (Count)
|
|
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry (Count)
|
|
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::6 2485382 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::6 2467729 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.rdQLenPdf::0 2485065 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::1 233 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::2 68 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::3 12 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::4 3 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::17 152661 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::18 154230 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::19 154232 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::20 154232 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::21 154232 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::22 154233 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::23 154233 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::24 154231 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::25 155804 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::26 154231 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::27 154231 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::28 154232 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::29 154231 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::30 154231 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::31 154231 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::32 154231 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdPerTurnAround::samples 154231 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::mean 16.114627 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::gmean 16.001309 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::stdev 43.219908 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::0-1023 154230 100.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::total 154231 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.wrPerTurnAround::samples 154231 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::mean 16.000058 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::gmean 16.000053 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::stdev 0.013231 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::16 154228 100.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::19 3 0.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::total 154231 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
|
|
system.mem_ctrls.bytesReadSys 159064448 # Total read bytes from the system interface side (Byte)
|
|
system.mem_ctrls.bytesWrittenSys 157934656 # Total written bytes from the system interface side (Byte)
|
|
system.mem_ctrls.avgRdBWSys 758467869.08388591 # Average system read bandwidth in Byte/s ((Byte/Second))
|
|
system.mem_ctrls.avgWrBWSys 753080675.76996565 # Average system write bandwidth in Byte/s ((Byte/Second))
|
|
system.mem_ctrls.totGap 209718092500 # Total gap between requests (Tick)
|
|
system.mem_ctrls.avgGap 42340.68 # Average gap between requests ((Tick/Count))
|
|
system.mem_ctrls.requestorReadBytes::cpu.inst 36160 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu.data 159028288 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorWriteBytes::writebacks 157933120 # Per-requestor bytes write to memory (Byte)
|
|
system.mem_ctrls.requestorReadRate::cpu.inst 172421.923886306235 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu.data 758295447.159999608994 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorWriteRate::writebacks 753073351.652844786644 # Per-requestor bytes write to memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadAccesses::cpu.inst 565 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu.data 2484817 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorWriteAccesses::writebacks 2467729 # Per-requestor write serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu.inst 15317750 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu.data 74495230250 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorWriteTotalLat::writebacks 5140754482500 # Per-requestor write total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadAvgLat::cpu.inst 27111.06 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu.data 29980.17 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorWriteAvgLat::writebacks 2083192.47 # Per-requestor write average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.dram.bytesRead::cpu.inst 36160 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu.data 159028288 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::total 159064448 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::cpu.inst 36160 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::total 36160 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesWritten::writebacks 157934656 # Number of bytes written to this memory (Byte)
|
|
system.mem_ctrls.dram.bytesWritten::total 157934656 # Number of bytes written to this memory (Byte)
|
|
system.mem_ctrls.dram.numReads::cpu.inst 565 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu.data 2484817 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::total 2485382 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numWrites::writebacks 2467729 # Number of write requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numWrites::total 2467729 # Number of write requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.bwRead::cpu.inst 172422 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu.data 758295447 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::total 758467869 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::cpu.inst 172422 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::total 172422 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwWrite::writebacks 753080676 # Write bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwWrite::total 753080676 # Write bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::writebacks 753080676 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu.inst 172422 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu.data 758295447 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::total 1511548545 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.readBursts 2485382 # Number of DRAM read bursts (Count)
|
|
system.mem_ctrls.dram.writeBursts 2467705 # Number of DRAM write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::0 155451 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::1 155459 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::2 155326 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::3 155297 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::4 155382 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::5 155395 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::6 155285 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::7 155264 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::8 155314 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::9 155232 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::10 155173 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::11 155239 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::12 155292 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::13 155398 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::14 155473 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::15 155402 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::0 154240 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::1 154240 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::2 154240 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::3 154249 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::4 154245 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::5 154298 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::6 154242 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::7 154240 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::8 154261 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::9 154151 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::10 154133 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::11 154206 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::12 154240 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::13 154240 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::14 154240 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::15 154240 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.totQLat 27909635500 # Total ticks spent queuing (Tick)
|
|
system.mem_ctrls.dram.totBusLat 12426910000 # Total ticks spent in databus transfers (Tick)
|
|
system.mem_ctrls.dram.totMemAccLat 74510548000 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
|
|
system.mem_ctrls.dram.avgQLat 11229.52 # Average queueing delay per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.avgBusLat 5000.00 # Average bus latency per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.avgMemAccLat 29979.52 # Average memory access latency per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.readRowHits 2287301 # Number of row buffer hits during reads (Count)
|
|
system.mem_ctrls.dram.writeRowHits 2293449 # Number of row buffer hits during writes (Count)
|
|
system.mem_ctrls.dram.readRowHitRate 92.03 # Row buffer hit rate for reads (Ratio)
|
|
system.mem_ctrls.dram.writeRowHitRate 92.94 # Row buffer hit rate for writes (Ratio)
|
|
system.mem_ctrls.dram.bytesPerActivate::samples 372335 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::mean 851.375240 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::gmean 751.017701 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::stdev 293.875046 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::0-127 6276 1.69% 1.69% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::128-255 20484 5.50% 7.19% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::256-383 20678 5.55% 12.74% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::384-511 13392 3.60% 16.34% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::512-639 7305 1.96% 18.30% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::640-767 23877 6.41% 24.71% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::768-895 13894 3.73% 28.44% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::896-1023 18193 4.89% 33.33% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::1024-1151 248236 66.67% 100.00% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::total 372335 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesRead 159064448 # Total bytes read (Byte)
|
|
system.mem_ctrls.dram.bytesWritten 157933120 # Total bytes written (Byte)
|
|
system.mem_ctrls.dram.avgRdBW 758.467869 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
|
|
system.mem_ctrls.dram.avgWrBW 753.073352 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
|
|
system.mem_ctrls.dram.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
|
|
system.mem_ctrls.dram.busUtil 11.81 # Data bus utilization in percentage (Ratio)
|
|
system.mem_ctrls.dram.busUtilRead 5.93 # Data bus utilization in percentage for reads (Ratio)
|
|
system.mem_ctrls.dram.busUtilWrite 5.88 # Data bus utilization in percentage for writes (Ratio)
|
|
system.mem_ctrls.dram.pageHitRate 92.48 # Row buffer hit rate, read and write combined (Ratio)
|
|
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.mem_ctrls.dram.rank0.actEnergy 1329475140 # Energy for activate commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.preEnergy 706632795 # Energy for precharge commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.readEnergy 8874013260 # Energy for read commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.writeEnergy 6441448680 # Energy for write commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.refreshEnergy 16554713760.000002 # Energy for refresh commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.actBackEnergy 50316812130 # Energy for active background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.preBackEnergy 38159701920 # Energy for precharge background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.totalEnergy 122382797685 # Total energy per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.averagePower 583.558557 # Core power per rank (mW) (Watt)
|
|
system.mem_ctrls.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE 97546686500 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::REF 7002840000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::ACT 105168583500 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.actEnergy 1329011040 # Energy for activate commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.preEnergy 706378530 # Energy for precharge commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.readEnergy 8871614220 # Energy for read commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.writeEnergy 6439971420 # Energy for write commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.refreshEnergy 16554713760.000002 # Energy for refresh commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.actBackEnergy 50302836870 # Energy for active background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.preBackEnergy 38171470560 # Energy for precharge background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.totalEnergy 122375996400 # Total energy per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.averagePower 583.526127 # Core power per rank (mW) (Watt)
|
|
system.mem_ctrls.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE 97577845500 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::REF 7002840000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::ACT 105137424500 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.membus.transDist::ReadResp 1293 # Transaction distribution (Count)
|
|
system.membus.transDist::WritebackDirty 2467729 # Transaction distribution (Count)
|
|
system.membus.transDist::CleanEvict 861 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadExReq 2484089 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadExResp 2484089 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadSharedReq 1293 # Transaction distribution (Count)
|
|
system.membus.pktCount_system.l2.mem_side_port::system.mem_ctrls.port 7439354 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktCount_system.l2.mem_side_port::total 7439354 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktCount::total 7439354 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktSize_system.l2.mem_side_port::system.mem_ctrls.port 316999104 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.pktSize_system.l2.mem_side_port::total 316999104 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.pktSize::total 316999104 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.snoops 0 # Total snoops (Count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (Byte)
|
|
system.membus.snoopFanout::samples 2485382 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::0 2485382 100.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::total 2485382 # Request fanout histogram (Count)
|
|
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.membus.reqLayer2.occupancy 14825273000 # Layer occupancy (ticks) (Tick)
|
|
system.membus.reqLayer2.utilization 0.1 # Layer utilization (Ratio)
|
|
system.membus.respLayer1.occupancy 13071445500 # Layer occupancy (ticks) (Tick)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (Ratio)
|
|
system.membus.snoop_filter.totRequests 4953972 # Total number of requests made to the snoop filter. (Count)
|
|
system.membus.snoop_filter.hitSingleRequests 2468590 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
|
|
system.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.tol2bus.transDist::ReadResp 1325 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::WritebackDirty 4951356 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::WritebackClean 169 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::CleanEvict 1975 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::UpgradeReq 2 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::UpgradeResp 2 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadExReq 2484097 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadExResp 2484096 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadCleanReq 578 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadSharedReq 747 # Transaction distribution (Count)
|
|
system.tol2bus.pktCount_system.cpu.icache.mem_side_port::system.l2.cpu_side_port 1323 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port 7454022 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount::total 7455345 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktSize_system.cpu.icache.mem_side_port::system.l2.cpu_side_port 47680 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port 317982080 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize::total 318029760 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.snoops 2469002 # Total snoops (Count)
|
|
system.tol2bus.snoopTraffic 157934784 # Total snoop traffic (Byte)
|
|
system.tol2bus.snoopFanout::samples 4954424 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::mean 0.000084 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::stdev 0.009174 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::0 4954007 99.99% 99.99% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::1 417 0.01% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::max_value 1 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::total 4954424 # Request fanout histogram (Count)
|
|
system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 209718110000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.tol2bus.reqLayer0.occupancy 4968758000 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer0.occupancy 867000 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer1.occupancy 3727265500 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.snoop_filter.totRequests 4969924 # Total number of requests made to the snoop filter. (Count)
|
|
system.tol2bus.snoop_filter.hitSingleRequests 2484500 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.hitMultiRequests 5 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.totSnoops 412 # Total number of snoops made to the snoop filter. (Count)
|
|
system.tol2bus.snoop_filter.hitSingleSnoops 412 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.voltage_domain.voltage 1 # Voltage in Volts (Volt)
|
|
system.workload.inst.arm 0 # number of arm instructions executed (Count)
|
|
system.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
|
|
|
|
---------- End Simulation Statistics ----------
|