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gem5-ilp-experiments/pipelineSimulation/o3-trace/stats.txt
Carlos Gutierrez cd69096346 initial commit
2025-09-21 01:17:26 -04:00

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---------- Begin Simulation Statistics ----------
simSeconds 0.002246 # Number of seconds simulated (Second)
simTicks 2245535000 # Number of ticks simulated (Tick)
finalTick 2245535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 944.08 # Real time elapsed on the host (Second)
hostTickRate 2378534 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 671236 # Number of bytes of host memory used (Byte)
simInsts 368504 # Number of instructions simulated (Count)
simOps 562917 # Number of ops (including micro ops) simulated (Count)
hostInstRate 390 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 596 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
system.clk_domain.clock 500 # Clock period in ticks (Tick)
system.cpu.numCycles 4491071 # Number of cpu cycles simulated (Cycle)
system.cpu.cpi 12.187306 # CPI: cycles per instruction (core level) ((Cycle/Count))
system.cpu.ipc 0.082053 # IPC: instructions per cycle (core level) ((Count/Cycle))
system.cpu.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
system.cpu.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
system.cpu.instsAdded 667766 # Number of instructions added to the IQ (excludes non-spec) (Count)
system.cpu.nonSpecInstsAdded 115 # Number of non-speculative instructions added to the IQ (Count)
system.cpu.instsIssued 660981 # Number of instructions issued (Count)
system.cpu.squashedInstsIssued 99 # Number of squashed instructions issued (Count)
system.cpu.squashedInstsExamined 104964 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
system.cpu.squashedOperandsExamined 68953 # Number of squashed operands that are examined and possibly removed from graph (Count)
system.cpu.squashedNonSpecRemoved 73 # Number of squashed non-spec instructions that were removed (Count)
system.cpu.numIssuedDist::samples 4452555 # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::mean 0.148450 # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::stdev 0.755171 # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::0 4233735 95.09% 95.09% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::1 57642 1.29% 96.38% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::2 23447 0.53% 96.91% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::3 64613 1.45% 98.36% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::4 38311 0.86% 99.22% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::5 13162 0.30% 99.51% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::6 10603 0.24% 99.75% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::7 8402 0.19% 99.94% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::8 2640 0.06% 100.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
system.cpu.numIssuedDist::total 4452555 # Number of insts issued each cycle (Count)
system.cpu.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IntAlu 8649 98.50% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IntMult 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IntDiv 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatAdd 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatCmp 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatCvt 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMult 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMultAcc 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatDiv 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMisc 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatSqrt 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAdd 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAddAcc 0 0.00% 98.50% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAlu 26 0.30% 98.79% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdCmp 0 0.00% 98.79% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdCvt 1 0.01% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMisc 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMult 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMultAcc 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdMatMultAcc 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShift 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShiftAcc 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdDiv 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSqrt 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatAdd 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatAlu 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatCmp 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatCvt 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatDiv 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMisc 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMult 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMultAcc 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatMatMultAcc 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatSqrt 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdReduceAdd 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdReduceAlu 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdReduceCmp 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatReduceAdd 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdFloatReduceCmp 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAes 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdAesMix 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha1Hash 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha1Hash2 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha256Hash 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdSha256Hash2 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShaSigma2 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdShaSigma3 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::SimdPredAlu 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::Matrix 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MatrixMov 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MatrixOP 0 0.00% 98.80% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MemRead 56 0.64% 99.44% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::MemWrite 30 0.34% 99.78% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMemRead 3 0.03% 99.82% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::FloatMemWrite 16 0.18% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIntegerArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorFloatArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorFloatConvert 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIntegerReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorFloatReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorMisc 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorIntegerExtension 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statFuBusy::VectorConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
system.cpu.statIssuedInstType_0::No_OpClass 475 0.07% 0.07% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IntAlu 515020 77.92% 77.99% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IntMult 47 0.01% 78.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IntDiv 73 0.01% 78.01% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatAdd 168 0.03% 78.03% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatCmp 0 0.00% 78.03% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatCvt 0 0.00% 78.03% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMult 0 0.00% 78.03% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMultAcc 0 0.00% 78.03% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatDiv 0 0.00% 78.03% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMisc 0 0.00% 78.03% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatSqrt 0 0.00% 78.03% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAdd 10 0.00% 78.03% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAddAcc 0 0.00% 78.03% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAlu 297 0.04% 78.08% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdCmp 4 0.00% 78.08% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdCvt 84 0.01% 78.09% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMisc 255 0.04% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMult 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMultAcc 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShift 7 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShiftAcc 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdDiv 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSqrt 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatAdd 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatAlu 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatCmp 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatCvt 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatDiv 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMisc 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMult 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdReduceAdd 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdReduceAlu 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdReduceCmp 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAes 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdAesMix 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha1Hash 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha256Hash 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShaSigma2 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdShaSigma3 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::SimdPredAlu 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::Matrix 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MatrixMov 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MatrixOP 0 0.00% 78.13% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MemRead 57980 8.77% 86.90% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::MemWrite 85809 12.98% 99.89% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMemRead 169 0.03% 99.91% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::FloatMemWrite 583 0.09% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
system.cpu.statIssuedInstType_0::total 660981 # Number of instructions issued per FU type, per thread (Count)
system.cpu.issueRate 0.147177 # Inst issue rate ((Count/Cycle))
system.cpu.fuBusy 8781 # FU busy when requested (Count)
system.cpu.fuBusyRate 0.013285 # FU busy rate (busy events/executed inst) ((Count/Count))
system.cpu.intInstQueueReads 5779846 # Number of integer instruction queue reads (Count)
system.cpu.intInstQueueWrites 770733 # Number of integer instruction queue writes (Count)
system.cpu.intInstQueueWakeupAccesses 650107 # Number of integer instruction queue wakeup accesses (Count)
system.cpu.fpInstQueueReads 3551 # Number of floating instruction queue reads (Count)
system.cpu.fpInstQueueWrites 2141 # Number of floating instruction queue writes (Count)
system.cpu.fpInstQueueWakeupAccesses 1713 # Number of floating instruction queue wakeup accesses (Count)
system.cpu.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
system.cpu.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
system.cpu.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
system.cpu.intAluAccesses 667490 # Number of integer alu accesses (Count)
system.cpu.fpAluAccesses 1797 # Number of floating point alu accesses (Count)
system.cpu.vecAluAccesses 0 # Number of vector alu accesses (Count)
system.cpu.numSquashedInsts 1009 # Number of squashed instructions skipped in execute (Count)
system.cpu.numSwp 0 # Number of swp insts executed (Count)
system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
system.cpu.idleCycles 38516 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
system.cpu.MemDepUnit__0.insertedLoads 58827 # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__0.insertedStores 86921 # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__0.conflictingLoads 30315 # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__0.conflictingStores 7344 # Number of conflicting stores. (Count)
system.cpu.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
system.cpu.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
system.cpu.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
system.cpu.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
system.cpu.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
system.cpu.branchPred.lookups 76389 # Number of BP lookups (Count)
system.cpu.branchPred.condPredicted 65121 # Number of conditional branches predicted (Count)
system.cpu.branchPred.condIncorrect 817 # Number of conditional branches incorrect (Count)
system.cpu.branchPred.BTBLookups 50826 # Number of BTB lookups (Count)
system.cpu.branchPred.BTBUpdates 710 # Number of BTB updates (Count)
system.cpu.branchPred.BTBHits 49960 # Number of BTB hits (Count)
system.cpu.branchPred.BTBHitRatio 0.982961 # BTB Hit Ratio (Ratio)
system.cpu.branchPred.RASUsed 2599 # Number of times the RAS was used to get a target. (Count)
system.cpu.branchPred.RASIncorrect 9 # Number of incorrect RAS predictions. (Count)
system.cpu.branchPred.indirectLookups 2392 # Number of indirect predictor lookups. (Count)
system.cpu.branchPred.indirectHits 2180 # Number of indirect target hits. (Count)
system.cpu.branchPred.indirectMisses 212 # Number of indirect misses. (Count)
system.cpu.branchPred.indirectMispredicted 66 # Number of mispredicted indirect branches. (Count)
system.cpu.commit.commitSquashedInsts 100929 # The number of squashed insts skipped by commit (Count)
system.cpu.commit.commitNonSpecStalls 42 # The number of times commit has been forced to stall to communicate backwards (Count)
system.cpu.commit.branchMispredicts 592 # The number of times a branch was mispredicted (Count)
system.cpu.commit.numCommittedDist::samples 4439494 # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::mean 0.126798 # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::stdev 0.771027 # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::0 4273681 96.27% 96.27% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::1 45303 1.02% 97.29% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::2 7992 0.18% 97.47% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::3 52721 1.19% 98.65% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::4 22196 0.50% 99.15% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::5 14746 0.33% 99.49% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::6 310 0.01% 99.49% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::7 1267 0.03% 99.52% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::8 21278 0.48% 100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
system.cpu.commit.numCommittedDist::total 4439494 # Number of insts commited each cycle (Count)
system.cpu.commit.amos 0 # Number of atomic instructions committed (Count)
system.cpu.commit.membars 28 # Number of memory barriers committed (Count)
system.cpu.commit.functionCalls 2307 # Number of function calls committed. (Count)
system.cpu.commit.committedInstType_0::No_OpClass 248 0.04% 0.04% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntAlu 442604 78.63% 78.67% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntMult 41 0.01% 78.68% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IntDiv 56 0.01% 78.69% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatAdd 146 0.03% 78.71% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatCmp 0 0.00% 78.71% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatCvt 0 0.00% 78.71% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMult 0 0.00% 78.71% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMultAcc 0 0.00% 78.71% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatDiv 0 0.00% 78.71% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMisc 0 0.00% 78.71% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatSqrt 0 0.00% 78.71% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAdd 10 0.00% 78.72% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAddAcc 0 0.00% 78.72% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAlu 237 0.04% 78.76% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdCmp 4 0.00% 78.76% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdCvt 76 0.01% 78.77% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMisc 235 0.04% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMult 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMultAcc 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShift 3 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShiftAcc 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdDiv 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSqrt 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatAdd 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatAlu 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatCmp 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatCvt 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatDiv 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMisc 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMult 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdReduceAdd 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdReduceAlu 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdReduceCmp 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAes 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdAesMix 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha1Hash 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha256Hash 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShaSigma2 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdShaSigma3 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::SimdPredAlu 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::Matrix 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MatrixMov 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MatrixOP 0 0.00% 78.81% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MemRead 48733 8.66% 87.47% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::MemWrite 69885 12.41% 99.89% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMemRead 125 0.02% 99.91% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::FloatMemWrite 514 0.09% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
system.cpu.commit.committedInstType_0::total 562917 # Class of committed instruction (Count)
system.cpu.commit.commitEligibleSamples 21278 # number cycles where commit BW limit reached (Cycle)
system.cpu.commitStats0.numInsts 368504 # Number of instructions committed (thread level) (Count)
system.cpu.commitStats0.numOps 562917 # Number of ops (including micro ops) committed (thread level) (Count)
system.cpu.commitStats0.numInstsNotNOP 368504 # Number of instructions committed excluding NOPs or prefetches (Count)
system.cpu.commitStats0.numOpsNotNOP 562917 # Number of Ops (including micro ops) Simulated (Count)
system.cpu.commitStats0.cpi 12.187306 # CPI: cycles per instruction (thread level) ((Cycle/Count))
system.cpu.commitStats0.ipc 0.082053 # IPC: instructions per cycle (thread level) ((Count/Cycle))
system.cpu.commitStats0.numMemRefs 119257 # Number of memory references committed (Count)
system.cpu.commitStats0.numFpInsts 1513 # Number of float instructions (Count)
system.cpu.commitStats0.numIntInsts 561781 # Number of integer instructions (Count)
system.cpu.commitStats0.numLoadInsts 48858 # Number of load instructions (Count)
system.cpu.commitStats0.numStoreInsts 70399 # Number of store instructions (Count)
system.cpu.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
system.cpu.commitStats0.committedInstType::No_OpClass 248 0.04% 0.04% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IntAlu 442604 78.63% 78.67% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IntMult 41 0.01% 78.68% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IntDiv 56 0.01% 78.69% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatAdd 146 0.03% 78.71% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatCmp 0 0.00% 78.71% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatCvt 0 0.00% 78.71% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMult 0 0.00% 78.71% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMultAcc 0 0.00% 78.71% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatDiv 0 0.00% 78.71% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMisc 0 0.00% 78.71% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatSqrt 0 0.00% 78.71% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAdd 10 0.00% 78.72% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAddAcc 0 0.00% 78.72% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAlu 237 0.04% 78.76% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdCmp 4 0.00% 78.76% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdCvt 76 0.01% 78.77% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMisc 235 0.04% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMult 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMultAcc 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShift 3 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdDiv 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSqrt 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMult 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAes 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdAesMix 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::SimdPredAlu 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::Matrix 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MatrixMov 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MatrixOP 0 0.00% 78.81% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MemRead 48733 8.66% 87.47% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::MemWrite 69885 12.41% 99.89% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMemRead 125 0.02% 99.91% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::FloatMemWrite 514 0.09% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
system.cpu.commitStats0.committedInstType::total 562917 # Class of committed instruction. (Count)
system.cpu.commitStats0.committedControl::IsControl 62738 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsDirectControl 58278 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsIndirectControl 4460 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsCondControl 52720 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsUncondControl 10018 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsCall 2307 # Class of control type instructions committed (Count)
system.cpu.commitStats0.committedControl::IsReturn 2304 # Class of control type instructions committed (Count)
system.cpu.dcache.demandHits::cpu.data 54395 # number of demand (read+write) hits (Count)
system.cpu.dcache.demandHits::total 54395 # number of demand (read+write) hits (Count)
system.cpu.dcache.overallHits::cpu.data 54395 # number of overall hits (Count)
system.cpu.dcache.overallHits::total 54395 # number of overall hits (Count)
system.cpu.dcache.demandMisses::cpu.data 31921 # number of demand (read+write) misses (Count)
system.cpu.dcache.demandMisses::total 31921 # number of demand (read+write) misses (Count)
system.cpu.dcache.overallMisses::cpu.data 31921 # number of overall misses (Count)
system.cpu.dcache.overallMisses::total 31921 # number of overall misses (Count)
system.cpu.dcache.demandMissLatency::cpu.data 2238157000 # number of demand (read+write) miss ticks (Tick)
system.cpu.dcache.demandMissLatency::total 2238157000 # number of demand (read+write) miss ticks (Tick)
system.cpu.dcache.overallMissLatency::cpu.data 2238157000 # number of overall miss ticks (Tick)
system.cpu.dcache.overallMissLatency::total 2238157000 # number of overall miss ticks (Tick)
system.cpu.dcache.demandAccesses::cpu.data 86316 # number of demand (read+write) accesses (Count)
system.cpu.dcache.demandAccesses::total 86316 # number of demand (read+write) accesses (Count)
system.cpu.dcache.overallAccesses::cpu.data 86316 # number of overall (read+write) accesses (Count)
system.cpu.dcache.overallAccesses::total 86316 # number of overall (read+write) accesses (Count)
system.cpu.dcache.demandMissRate::cpu.data 0.369816 # miss rate for demand accesses (Ratio)
system.cpu.dcache.demandMissRate::total 0.369816 # miss rate for demand accesses (Ratio)
system.cpu.dcache.overallMissRate::cpu.data 0.369816 # miss rate for overall accesses (Ratio)
system.cpu.dcache.overallMissRate::total 0.369816 # miss rate for overall accesses (Ratio)
system.cpu.dcache.demandAvgMissLatency::cpu.data 70115.503900 # average overall miss latency in ticks ((Tick/Count))
system.cpu.dcache.demandAvgMissLatency::total 70115.503900 # average overall miss latency in ticks ((Tick/Count))
system.cpu.dcache.overallAvgMissLatency::cpu.data 70115.503900 # average overall miss latency ((Tick/Count))
system.cpu.dcache.overallAvgMissLatency::total 70115.503900 # average overall miss latency ((Tick/Count))
system.cpu.dcache.blockedCycles::no_mshrs 371 # number of cycles access was blocked (Cycle)
system.cpu.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
system.cpu.dcache.blockedCauses::no_mshrs 7 # number of times access was blocked (Count)
system.cpu.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
system.cpu.dcache.avgBlocked::no_mshrs 53 # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dcache.writebacks::writebacks 29158 # number of writebacks (Count)
system.cpu.dcache.writebacks::total 29158 # number of writebacks (Count)
system.cpu.dcache.demandMshrHits::cpu.data 1032 # number of demand (read+write) MSHR hits (Count)
system.cpu.dcache.demandMshrHits::total 1032 # number of demand (read+write) MSHR hits (Count)
system.cpu.dcache.overallMshrHits::cpu.data 1032 # number of overall MSHR hits (Count)
system.cpu.dcache.overallMshrHits::total 1032 # number of overall MSHR hits (Count)
system.cpu.dcache.demandMshrMisses::cpu.data 30889 # number of demand (read+write) MSHR misses (Count)
system.cpu.dcache.demandMshrMisses::total 30889 # number of demand (read+write) MSHR misses (Count)
system.cpu.dcache.overallMshrMisses::cpu.data 30889 # number of overall MSHR misses (Count)
system.cpu.dcache.overallMshrMisses::total 30889 # number of overall MSHR misses (Count)
system.cpu.dcache.demandMshrMissLatency::cpu.data 2136363500 # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.dcache.demandMshrMissLatency::total 2136363500 # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.dcache.overallMshrMissLatency::cpu.data 2136363500 # number of overall MSHR miss ticks (Tick)
system.cpu.dcache.overallMshrMissLatency::total 2136363500 # number of overall MSHR miss ticks (Tick)
system.cpu.dcache.demandMshrMissRate::cpu.data 0.357859 # mshr miss ratio for demand accesses (Ratio)
system.cpu.dcache.demandMshrMissRate::total 0.357859 # mshr miss ratio for demand accesses (Ratio)
system.cpu.dcache.overallMshrMissRate::cpu.data 0.357859 # mshr miss ratio for overall accesses (Ratio)
system.cpu.dcache.overallMshrMissRate::total 0.357859 # mshr miss ratio for overall accesses (Ratio)
system.cpu.dcache.demandAvgMshrMissLatency::cpu.data 69162.598336 # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.demandAvgMshrMissLatency::total 69162.598336 # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.overallAvgMshrMissLatency::cpu.data 69162.598336 # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.overallAvgMshrMissLatency::total 69162.598336 # average overall mshr miss latency ((Tick/Count))
system.cpu.dcache.replacements 29863 # number of replacements (Count)
system.cpu.dcache.LockedRMWReadReq.hits::cpu.data 13 # number of LockedRMWReadReq hits (Count)
system.cpu.dcache.LockedRMWReadReq.hits::total 13 # number of LockedRMWReadReq hits (Count)
system.cpu.dcache.LockedRMWReadReq.misses::cpu.data 1 # number of LockedRMWReadReq misses (Count)
system.cpu.dcache.LockedRMWReadReq.misses::total 1 # number of LockedRMWReadReq misses (Count)
system.cpu.dcache.LockedRMWReadReq.missLatency::cpu.data 91000 # number of LockedRMWReadReq miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.missLatency::total 91000 # number of LockedRMWReadReq miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.accesses::cpu.data 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
system.cpu.dcache.LockedRMWReadReq.accesses::total 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
system.cpu.dcache.LockedRMWReadReq.missRate::cpu.data 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.missRate::total 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::cpu.data 91000 # average LockedRMWReadReq miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWReadReq.avgMissLatency::total 91000 # average LockedRMWReadReq miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWReadReq.mshrMisses::cpu.data 1 # number of LockedRMWReadReq MSHR misses (Count)
system.cpu.dcache.LockedRMWReadReq.mshrMisses::total 1 # number of LockedRMWReadReq MSHR misses (Count)
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::cpu.data 233000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.mshrMissLatency::total 233000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::cpu.data 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.mshrMissRate::total 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu.data 233000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWReadReq.avgMshrMissLatency::total 233000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.LockedRMWWriteReq.hits::cpu.data 14 # number of LockedRMWWriteReq hits (Count)
system.cpu.dcache.LockedRMWWriteReq.hits::total 14 # number of LockedRMWWriteReq hits (Count)
system.cpu.dcache.LockedRMWWriteReq.accesses::cpu.data 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
system.cpu.dcache.LockedRMWWriteReq.accesses::total 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.hits::cpu.data 14199 # number of ReadReq hits (Count)
system.cpu.dcache.ReadReq.hits::total 14199 # number of ReadReq hits (Count)
system.cpu.dcache.ReadReq.misses::cpu.data 1763 # number of ReadReq misses (Count)
system.cpu.dcache.ReadReq.misses::total 1763 # number of ReadReq misses (Count)
system.cpu.dcache.ReadReq.missLatency::cpu.data 123851000 # number of ReadReq miss ticks (Tick)
system.cpu.dcache.ReadReq.missLatency::total 123851000 # number of ReadReq miss ticks (Tick)
system.cpu.dcache.ReadReq.accesses::cpu.data 15962 # number of ReadReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.accesses::total 15962 # number of ReadReq accesses(hits+misses) (Count)
system.cpu.dcache.ReadReq.missRate::cpu.data 0.110450 # miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.missRate::total 0.110450 # miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.avgMissLatency::cpu.data 70250.141804 # average ReadReq miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.avgMissLatency::total 70250.141804 # average ReadReq miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.mshrHits::cpu.data 1031 # number of ReadReq MSHR hits (Count)
system.cpu.dcache.ReadReq.mshrHits::total 1031 # number of ReadReq MSHR hits (Count)
system.cpu.dcache.ReadReq.mshrMisses::cpu.data 732 # number of ReadReq MSHR misses (Count)
system.cpu.dcache.ReadReq.mshrMisses::total 732 # number of ReadReq MSHR misses (Count)
system.cpu.dcache.ReadReq.mshrMissLatency::cpu.data 52220000 # number of ReadReq MSHR miss ticks (Tick)
system.cpu.dcache.ReadReq.mshrMissLatency::total 52220000 # number of ReadReq MSHR miss ticks (Tick)
system.cpu.dcache.ReadReq.mshrMissRate::cpu.data 0.045859 # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.mshrMissRate::total 0.045859 # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.dcache.ReadReq.avgMshrMissLatency::cpu.data 71338.797814 # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.ReadReq.avgMshrMissLatency::total 71338.797814 # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.hits::cpu.data 40196 # number of WriteReq hits (Count)
system.cpu.dcache.WriteReq.hits::total 40196 # number of WriteReq hits (Count)
system.cpu.dcache.WriteReq.misses::cpu.data 30158 # number of WriteReq misses (Count)
system.cpu.dcache.WriteReq.misses::total 30158 # number of WriteReq misses (Count)
system.cpu.dcache.WriteReq.missLatency::cpu.data 2114306000 # number of WriteReq miss ticks (Tick)
system.cpu.dcache.WriteReq.missLatency::total 2114306000 # number of WriteReq miss ticks (Tick)
system.cpu.dcache.WriteReq.accesses::cpu.data 70354 # number of WriteReq accesses(hits+misses) (Count)
system.cpu.dcache.WriteReq.accesses::total 70354 # number of WriteReq accesses(hits+misses) (Count)
system.cpu.dcache.WriteReq.missRate::cpu.data 0.428661 # miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.missRate::total 0.428661 # miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.avgMissLatency::cpu.data 70107.633132 # average WriteReq miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.avgMissLatency::total 70107.633132 # average WriteReq miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.mshrHits::cpu.data 1 # number of WriteReq MSHR hits (Count)
system.cpu.dcache.WriteReq.mshrHits::total 1 # number of WriteReq MSHR hits (Count)
system.cpu.dcache.WriteReq.mshrMisses::cpu.data 30157 # number of WriteReq MSHR misses (Count)
system.cpu.dcache.WriteReq.mshrMisses::total 30157 # number of WriteReq MSHR misses (Count)
system.cpu.dcache.WriteReq.mshrMissLatency::cpu.data 2084143500 # number of WriteReq MSHR miss ticks (Tick)
system.cpu.dcache.WriteReq.mshrMissLatency::total 2084143500 # number of WriteReq MSHR miss ticks (Tick)
system.cpu.dcache.WriteReq.mshrMissRate::cpu.data 0.428647 # mshr miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.mshrMissRate::total 0.428647 # mshr miss rate for WriteReq accesses (Ratio)
system.cpu.dcache.WriteReq.avgMshrMissLatency::cpu.data 69109.775508 # average WriteReq mshr miss latency ((Tick/Count))
system.cpu.dcache.WriteReq.avgMshrMissLatency::total 69109.775508 # average WriteReq mshr miss latency ((Tick/Count))
system.cpu.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.dcache.tags.tagsInUse 994.590904 # Average ticks per tags in use ((Tick/Count))
system.cpu.dcache.tags.totalRefs 85311 # Total number of references to valid blocks. (Count)
system.cpu.dcache.tags.sampledRefs 30887 # Sample count of references to valid blocks. (Count)
system.cpu.dcache.tags.avgRefs 2.762036 # Average number of references to valid blocks. ((Count/Count))
system.cpu.dcache.tags.warmupTick 165500 # The tick when the warmup percentage was hit. (Tick)
system.cpu.dcache.tags.occupancies::cpu.data 994.590904 # Average occupied blocks per tick, per requestor ((Count/Tick))
system.cpu.dcache.tags.avgOccs::cpu.data 0.971280 # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.dcache.tags.avgOccs::total 0.971280 # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.dcache.tags.occupanciesTaskId::1024 1024 # Occupied blocks per task id (Count)
system.cpu.dcache.tags.ageTaskId_1024::0 141 # Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ageTaskId_1024::1 882 # Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ageTaskId_1024::3 1 # Occupied blocks per task id, per block age (Count)
system.cpu.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
system.cpu.dcache.tags.tagAccesses 203575 # Number of tag accesses (Count)
system.cpu.dcache.tags.dataAccesses 203575 # Number of data accesses (Count)
system.cpu.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.decode.idleCycles 48250 # Number of cycles decode is idle (Cycle)
system.cpu.decode.blockedCycles 4310466 # Number of cycles decode is blocked (Cycle)
system.cpu.decode.runCycles 44679 # Number of cycles decode is running (Cycle)
system.cpu.decode.unblockCycles 48053 # Number of cycles decode is unblocking (Cycle)
system.cpu.decode.squashCycles 1107 # Number of cycles decode is squashing (Cycle)
system.cpu.decode.branchResolved 48207 # Number of times decode resolved a branch (Count)
system.cpu.decode.branchMispred 272 # Number of times decode detected a branch misprediction (Count)
system.cpu.decode.decodedInsts 677276 # Number of instructions handled by decode (Count)
system.cpu.decode.squashedInsts 1228 # Number of squashed instructions handled by decode (Count)
system.cpu.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
system.cpu.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
system.cpu.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
system.cpu.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
system.cpu.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.dtb_walker_cache.replacements 0 # number of replacements (Count)
system.cpu.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
system.cpu.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
system.cpu.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
system.cpu.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
system.cpu.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
system.cpu.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
system.cpu.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
system.cpu.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.executeStats0.numInsts 659972 # Number of executed instructions (Count)
system.cpu.executeStats0.numNop 0 # Number of nop insts executed (Count)
system.cpu.executeStats0.numBranches 71318 # Number of branches executed (Count)
system.cpu.executeStats0.numLoadInsts 57916 # Number of load instructions executed (Count)
system.cpu.executeStats0.numStoreInsts 86298 # Number of stores executed (Count)
system.cpu.executeStats0.instRate 0.146952 # Inst execution rate ((Count/Cycle))
system.cpu.executeStats0.numCCRegReads 345502 # Number of times the CC registers were read (Count)
system.cpu.executeStats0.numCCRegWrites 308084 # Number of times the CC registers were written (Count)
system.cpu.executeStats0.numFpRegReads 2102 # Number of times the floating registers were read (Count)
system.cpu.executeStats0.numFpRegWrites 1067 # Number of times the floating registers were written (Count)
system.cpu.executeStats0.numIntRegReads 996692 # Number of times the integer registers were read (Count)
system.cpu.executeStats0.numIntRegWrites 438830 # Number of times the integer registers were written (Count)
system.cpu.executeStats0.numMemRefs 144214 # Number of memory refs (Count)
system.cpu.executeStats0.numMiscRegReads 286377 # Number of times the Misc registers were read (Count)
system.cpu.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
system.cpu.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
system.cpu.fetch.predictedBranches 54739 # Number of branches that fetch has predicted taken (Count)
system.cpu.fetch.cycles 4412341 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
system.cpu.fetch.squashCycles 2750 # Number of cycles fetch has spent squashing (Cycle)
system.cpu.fetch.miscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
system.cpu.fetch.pendingTrapStallCycles 273 # Number of stall cycles due to pending traps (Cycle)
system.cpu.fetch.cacheLines 19716 # Number of cache lines fetched (Count)
system.cpu.fetch.icacheSquashes 434 # Number of outstanding Icache misses that were squashed (Count)
system.cpu.fetch.nisnDist::samples 4452555 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::mean 0.158559 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::stdev 1.016254 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::0 4322560 97.08% 97.08% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::1 10484 0.24% 97.32% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::2 9806 0.22% 97.54% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::3 25718 0.58% 98.11% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::4 8831 0.20% 98.31% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::5 5147 0.12% 98.43% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::6 7254 0.16% 98.59% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::7 7879 0.18% 98.77% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::8 54876 1.23% 100.00% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetch.nisnDist::total 4452555 # Number of instructions fetched each cycle (Total) (Count)
system.cpu.fetchStats0.numInsts 466777 # Number of instructions fetched (thread level) (Count)
system.cpu.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
system.cpu.fetchStats0.fetchRate 0.103934 # Number of inst fetches per cycle ((Count/Cycle))
system.cpu.fetchStats0.numBranches 76389 # Number of branches fetched (Count)
system.cpu.fetchStats0.branchRate 0.017009 # Number of branch fetches per cycle (Ratio)
system.cpu.fetchStats0.icacheStallCycles 38517 # ICache total stall cycles (Cycle)
system.cpu.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
system.cpu.icache.demandHits::cpu.inst 18944 # number of demand (read+write) hits (Count)
system.cpu.icache.demandHits::total 18944 # number of demand (read+write) hits (Count)
system.cpu.icache.overallHits::cpu.inst 18944 # number of overall hits (Count)
system.cpu.icache.overallHits::total 18944 # number of overall hits (Count)
system.cpu.icache.demandMisses::cpu.inst 772 # number of demand (read+write) misses (Count)
system.cpu.icache.demandMisses::total 772 # number of demand (read+write) misses (Count)
system.cpu.icache.overallMisses::cpu.inst 772 # number of overall misses (Count)
system.cpu.icache.overallMisses::total 772 # number of overall misses (Count)
system.cpu.icache.demandMissLatency::cpu.inst 52028000 # number of demand (read+write) miss ticks (Tick)
system.cpu.icache.demandMissLatency::total 52028000 # number of demand (read+write) miss ticks (Tick)
system.cpu.icache.overallMissLatency::cpu.inst 52028000 # number of overall miss ticks (Tick)
system.cpu.icache.overallMissLatency::total 52028000 # number of overall miss ticks (Tick)
system.cpu.icache.demandAccesses::cpu.inst 19716 # number of demand (read+write) accesses (Count)
system.cpu.icache.demandAccesses::total 19716 # number of demand (read+write) accesses (Count)
system.cpu.icache.overallAccesses::cpu.inst 19716 # number of overall (read+write) accesses (Count)
system.cpu.icache.overallAccesses::total 19716 # number of overall (read+write) accesses (Count)
system.cpu.icache.demandMissRate::cpu.inst 0.039156 # miss rate for demand accesses (Ratio)
system.cpu.icache.demandMissRate::total 0.039156 # miss rate for demand accesses (Ratio)
system.cpu.icache.overallMissRate::cpu.inst 0.039156 # miss rate for overall accesses (Ratio)
system.cpu.icache.overallMissRate::total 0.039156 # miss rate for overall accesses (Ratio)
system.cpu.icache.demandAvgMissLatency::cpu.inst 67393.782383 # average overall miss latency in ticks ((Tick/Count))
system.cpu.icache.demandAvgMissLatency::total 67393.782383 # average overall miss latency in ticks ((Tick/Count))
system.cpu.icache.overallAvgMissLatency::cpu.inst 67393.782383 # average overall miss latency ((Tick/Count))
system.cpu.icache.overallAvgMissLatency::total 67393.782383 # average overall miss latency ((Tick/Count))
system.cpu.icache.blockedCycles::no_mshrs 276 # number of cycles access was blocked (Cycle)
system.cpu.icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
system.cpu.icache.blockedCauses::no_mshrs 6 # number of times access was blocked (Count)
system.cpu.icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
system.cpu.icache.avgBlocked::no_mshrs 46 # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.icache.writebacks::writebacks 176 # number of writebacks (Count)
system.cpu.icache.writebacks::total 176 # number of writebacks (Count)
system.cpu.icache.demandMshrHits::cpu.inst 186 # number of demand (read+write) MSHR hits (Count)
system.cpu.icache.demandMshrHits::total 186 # number of demand (read+write) MSHR hits (Count)
system.cpu.icache.overallMshrHits::cpu.inst 186 # number of overall MSHR hits (Count)
system.cpu.icache.overallMshrHits::total 186 # number of overall MSHR hits (Count)
system.cpu.icache.demandMshrMisses::cpu.inst 586 # number of demand (read+write) MSHR misses (Count)
system.cpu.icache.demandMshrMisses::total 586 # number of demand (read+write) MSHR misses (Count)
system.cpu.icache.overallMshrMisses::cpu.inst 586 # number of overall MSHR misses (Count)
system.cpu.icache.overallMshrMisses::total 586 # number of overall MSHR misses (Count)
system.cpu.icache.demandMshrMissLatency::cpu.inst 41774500 # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.icache.demandMshrMissLatency::total 41774500 # number of demand (read+write) MSHR miss ticks (Tick)
system.cpu.icache.overallMshrMissLatency::cpu.inst 41774500 # number of overall MSHR miss ticks (Tick)
system.cpu.icache.overallMshrMissLatency::total 41774500 # number of overall MSHR miss ticks (Tick)
system.cpu.icache.demandMshrMissRate::cpu.inst 0.029722 # mshr miss ratio for demand accesses (Ratio)
system.cpu.icache.demandMshrMissRate::total 0.029722 # mshr miss ratio for demand accesses (Ratio)
system.cpu.icache.overallMshrMissRate::cpu.inst 0.029722 # mshr miss ratio for overall accesses (Ratio)
system.cpu.icache.overallMshrMissRate::total 0.029722 # mshr miss ratio for overall accesses (Ratio)
system.cpu.icache.demandAvgMshrMissLatency::cpu.inst 71287.542662 # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.demandAvgMshrMissLatency::total 71287.542662 # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.overallAvgMshrMissLatency::cpu.inst 71287.542662 # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.overallAvgMshrMissLatency::total 71287.542662 # average overall mshr miss latency ((Tick/Count))
system.cpu.icache.replacements 176 # number of replacements (Count)
system.cpu.icache.ReadReq.hits::cpu.inst 18944 # number of ReadReq hits (Count)
system.cpu.icache.ReadReq.hits::total 18944 # number of ReadReq hits (Count)
system.cpu.icache.ReadReq.misses::cpu.inst 772 # number of ReadReq misses (Count)
system.cpu.icache.ReadReq.misses::total 772 # number of ReadReq misses (Count)
system.cpu.icache.ReadReq.missLatency::cpu.inst 52028000 # number of ReadReq miss ticks (Tick)
system.cpu.icache.ReadReq.missLatency::total 52028000 # number of ReadReq miss ticks (Tick)
system.cpu.icache.ReadReq.accesses::cpu.inst 19716 # number of ReadReq accesses(hits+misses) (Count)
system.cpu.icache.ReadReq.accesses::total 19716 # number of ReadReq accesses(hits+misses) (Count)
system.cpu.icache.ReadReq.missRate::cpu.inst 0.039156 # miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.missRate::total 0.039156 # miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.avgMissLatency::cpu.inst 67393.782383 # average ReadReq miss latency ((Tick/Count))
system.cpu.icache.ReadReq.avgMissLatency::total 67393.782383 # average ReadReq miss latency ((Tick/Count))
system.cpu.icache.ReadReq.mshrHits::cpu.inst 186 # number of ReadReq MSHR hits (Count)
system.cpu.icache.ReadReq.mshrHits::total 186 # number of ReadReq MSHR hits (Count)
system.cpu.icache.ReadReq.mshrMisses::cpu.inst 586 # number of ReadReq MSHR misses (Count)
system.cpu.icache.ReadReq.mshrMisses::total 586 # number of ReadReq MSHR misses (Count)
system.cpu.icache.ReadReq.mshrMissLatency::cpu.inst 41774500 # number of ReadReq MSHR miss ticks (Tick)
system.cpu.icache.ReadReq.mshrMissLatency::total 41774500 # number of ReadReq MSHR miss ticks (Tick)
system.cpu.icache.ReadReq.mshrMissRate::cpu.inst 0.029722 # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.mshrMissRate::total 0.029722 # mshr miss rate for ReadReq accesses (Ratio)
system.cpu.icache.ReadReq.avgMshrMissLatency::cpu.inst 71287.542662 # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.icache.ReadReq.avgMshrMissLatency::total 71287.542662 # average ReadReq mshr miss latency ((Tick/Count))
system.cpu.icache.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.icache.tags.tagsInUse 404.365127 # Average ticks per tags in use ((Tick/Count))
system.cpu.icache.tags.totalRefs 19530 # Total number of references to valid blocks. (Count)
system.cpu.icache.tags.sampledRefs 586 # Sample count of references to valid blocks. (Count)
system.cpu.icache.tags.avgRefs 33.327645 # Average number of references to valid blocks. ((Count/Count))
system.cpu.icache.tags.warmupTick 82000 # The tick when the warmup percentage was hit. (Tick)
system.cpu.icache.tags.occupancies::cpu.inst 404.365127 # Average occupied blocks per tick, per requestor ((Count/Tick))
system.cpu.icache.tags.avgOccs::cpu.inst 0.789776 # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.icache.tags.avgOccs::total 0.789776 # Average percentage of cache occupancy ((Ratio/Tick))
system.cpu.icache.tags.occupanciesTaskId::1024 408 # Occupied blocks per task id (Count)
system.cpu.icache.tags.ageTaskId_1024::3 408 # Occupied blocks per task id, per block age (Count)
system.cpu.icache.tags.ratioOccsTaskId::1024 0.796875 # Ratio of occupied blocks and all blocks, per task id (Ratio)
system.cpu.icache.tags.tagAccesses 40018 # Number of tag accesses (Count)
system.cpu.icache.tags.dataAccesses 40018 # Number of data accesses (Count)
system.cpu.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
system.cpu.iew.squashCycles 1107 # Number of cycles IEW is squashing (Cycle)
system.cpu.iew.blockCycles 74879 # Number of cycles IEW is blocking (Cycle)
system.cpu.iew.unblockCycles 2464238 # Number of cycles IEW is unblocking (Cycle)
system.cpu.iew.dispatchedInsts 667881 # Number of instructions dispatched to IQ (Count)
system.cpu.iew.dispSquashedInsts 76 # Number of squashed instructions skipped by dispatch (Count)
system.cpu.iew.dispLoadInsts 58827 # Number of dispatched load instructions (Count)
system.cpu.iew.dispStoreInsts 86921 # Number of dispatched store instructions (Count)
system.cpu.iew.dispNonSpecInsts 39 # Number of dispatched non-speculative instructions (Count)
system.cpu.iew.iqFullEvents 1627 # Number of times the IQ has become full, causing a stall (Count)
system.cpu.iew.lsqFullEvents 2463063 # Number of times the LSQ has become full, causing a stall (Count)
system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations (Count)
system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly (Count)
system.cpu.iew.predictedNotTakenIncorrect 613 # Number of branches that were predicted not taken incorrectly (Count)
system.cpu.iew.branchMispredicts 669 # Number of branch mispredicts detected at execute (Count)
system.cpu.iew.instsToCommit 659652 # Cumulative count of insts sent to commit (Count)
system.cpu.iew.writebackCount 651820 # Cumulative count of insts written-back (Count)
system.cpu.iew.producerInst 358110 # Number of instructions producing a value (Count)
system.cpu.iew.consumerInst 579836 # Number of instructions consuming a value (Count)
system.cpu.iew.wbRate 0.145137 # Insts written-back per cycle ((Count/Cycle))
system.cpu.iew.wbFanout 0.617606 # Average fanout of values written-back ((Count/Count))
system.cpu.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
system.cpu.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
system.cpu.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
system.cpu.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
system.cpu.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
system.cpu.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
system.cpu.itb_walker_cache.replacements 0 # number of replacements (Count)
system.cpu.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
system.cpu.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
system.cpu.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
system.cpu.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
system.cpu.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
system.cpu.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
system.cpu.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
system.cpu.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.lsq0.forwLoads 41845 # Number of loads that had data forwarded from stores (Count)
system.cpu.lsq0.squashedLoads 9969 # Number of loads squashed (Count)
system.cpu.lsq0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed (Count)
system.cpu.lsq0.memOrderViolation 32 # Number of memory ordering violations (Count)
system.cpu.lsq0.squashedStores 16522 # Number of stores squashed (Count)
system.cpu.lsq0.rescheduledLoads 1 # Number of loads that were rescheduled (Count)
system.cpu.lsq0.blockedByCache 6 # Number of times an access to memory failed due to the cache being blocked (Count)
system.cpu.lsq0.loadToUse::samples 48858 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::mean 6.949363 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::stdev 26.599327 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::0-9 47244 96.70% 96.70% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::20-29 2 0.00% 96.70% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::90-99 2 0.00% 96.70% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::100-109 12 0.02% 96.73% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::110-119 34 0.07% 96.80% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::120-129 191 0.39% 97.19% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::130-139 1183 2.42% 99.61% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::140-149 27 0.06% 99.67% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::150-159 30 0.06% 99.73% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::160-169 67 0.14% 99.86% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::170-179 2 0.00% 99.87% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::180-189 3 0.01% 99.88% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::190-199 32 0.07% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::200-209 8 0.02% 99.96% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::280-289 1 0.00% 99.96% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::overflows 20 0.04% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::max_value 681 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.lsq0.loadToUse::total 48858 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
system.cpu.mmu.dtb.rdAccesses 57908 # TLB accesses on read requests (Count)
system.cpu.mmu.dtb.wrAccesses 86298 # TLB accesses on write requests (Count)
system.cpu.mmu.dtb.rdMisses 107 # TLB misses on read requests (Count)
system.cpu.mmu.dtb.wrMisses 8006 # TLB misses on write requests (Count)
system.cpu.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
system.cpu.mmu.itb.wrAccesses 19766 # TLB accesses on write requests (Count)
system.cpu.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
system.cpu.mmu.itb.wrMisses 93 # TLB misses on write requests (Count)
system.cpu.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.power_state.pwrStateResidencyTicks::ON 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.cpu.rename.squashCycles 1107 # Number of cycles rename is squashing (Cycle)
system.cpu.rename.idleCycles 63284 # Number of cycles rename is idle (Cycle)
system.cpu.rename.blockCycles 2542863 # Number of cycles rename is blocking (Cycle)
system.cpu.rename.serializeStallCycles 1288 # count of cycles rename stalled for serializing inst (Cycle)
system.cpu.rename.runCycles 76864 # Number of cycles rename is running (Cycle)
system.cpu.rename.unblockCycles 1767149 # Number of cycles rename is unblocking (Cycle)
system.cpu.rename.renamedInsts 672043 # Number of instructions processed by rename (Count)
system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full (Count)
system.cpu.rename.IQFullEvents 10562 # Number of times rename has blocked due to IQ full (Count)
system.cpu.rename.SQFullEvents 1745772 # Number of times rename has blocked due to SQ full (Count)
system.cpu.rename.renamedOperands 1300071 # Number of destination operands rename has renamed (Count)
system.cpu.rename.lookups 2565017 # Number of register rename lookups that rename has made (Count)
system.cpu.rename.intLookups 1017661 # Number of integer rename lookups (Count)
system.cpu.rename.fpLookups 2262 # Number of floating rename lookups (Count)
system.cpu.rename.committedMaps 1081187 # Number of HB maps that are committed (Count)
system.cpu.rename.undoneMaps 218872 # Number of HB maps that are undone due to squashing (Count)
system.cpu.rename.serializing 45 # count of serializing insts renamed (Count)
system.cpu.rename.tempSerializing 45 # count of temporary serializing insts renamed (Count)
system.cpu.rename.skidInsts 264335 # count of insts added to the skid buffer (Count)
system.cpu.rob.reads 5075731 # The number of ROB reads (Count)
system.cpu.rob.writes 1340768 # The number of ROB writes (Count)
system.cpu.thread_0.numInsts 368504 # Number of Instructions committed (Count)
system.cpu.thread_0.numOps 562917 # Number of Ops committed (Count)
system.cpu.thread_0.numMemRefs 0 # Number of Memory References (Count)
system.cpu.workload.numSyscalls 14 # Number of system calls (Count)
system.cpu_clk_domain.clock 500 # Clock period in ticks (Tick)
system.cpu_voltage_domain.voltage 1 # Voltage in Volts (Volt)
system.l2.demandHits::cpu.inst 15 # number of demand (read+write) hits (Count)
system.l2.demandHits::cpu.data 4 # number of demand (read+write) hits (Count)
system.l2.demandHits::total 19 # number of demand (read+write) hits (Count)
system.l2.overallHits::cpu.inst 15 # number of overall hits (Count)
system.l2.overallHits::cpu.data 4 # number of overall hits (Count)
system.l2.overallHits::total 19 # number of overall hits (Count)
system.l2.demandMisses::cpu.inst 569 # number of demand (read+write) misses (Count)
system.l2.demandMisses::cpu.data 30884 # number of demand (read+write) misses (Count)
system.l2.demandMisses::total 31453 # number of demand (read+write) misses (Count)
system.l2.overallMisses::cpu.inst 569 # number of overall misses (Count)
system.l2.overallMisses::cpu.data 30884 # number of overall misses (Count)
system.l2.overallMisses::total 31453 # number of overall misses (Count)
system.l2.demandMissLatency::cpu.inst 40730000 # number of demand (read+write) miss ticks (Tick)
system.l2.demandMissLatency::cpu.data 2090042500 # number of demand (read+write) miss ticks (Tick)
system.l2.demandMissLatency::total 2130772500 # number of demand (read+write) miss ticks (Tick)
system.l2.overallMissLatency::cpu.inst 40730000 # number of overall miss ticks (Tick)
system.l2.overallMissLatency::cpu.data 2090042500 # number of overall miss ticks (Tick)
system.l2.overallMissLatency::total 2130772500 # number of overall miss ticks (Tick)
system.l2.demandAccesses::cpu.inst 584 # number of demand (read+write) accesses (Count)
system.l2.demandAccesses::cpu.data 30888 # number of demand (read+write) accesses (Count)
system.l2.demandAccesses::total 31472 # number of demand (read+write) accesses (Count)
system.l2.overallAccesses::cpu.inst 584 # number of overall (read+write) accesses (Count)
system.l2.overallAccesses::cpu.data 30888 # number of overall (read+write) accesses (Count)
system.l2.overallAccesses::total 31472 # number of overall (read+write) accesses (Count)
system.l2.demandMissRate::cpu.inst 0.974315 # miss rate for demand accesses (Ratio)
system.l2.demandMissRate::cpu.data 0.999870 # miss rate for demand accesses (Ratio)
system.l2.demandMissRate::total 0.999396 # miss rate for demand accesses (Ratio)
system.l2.overallMissRate::cpu.inst 0.974315 # miss rate for overall accesses (Ratio)
system.l2.overallMissRate::cpu.data 0.999870 # miss rate for overall accesses (Ratio)
system.l2.overallMissRate::total 0.999396 # miss rate for overall accesses (Ratio)
system.l2.demandAvgMissLatency::cpu.inst 71581.722320 # average overall miss latency in ticks ((Tick/Count))
system.l2.demandAvgMissLatency::cpu.data 67673.957389 # average overall miss latency in ticks ((Tick/Count))
system.l2.demandAvgMissLatency::total 67744.650749 # average overall miss latency in ticks ((Tick/Count))
system.l2.overallAvgMissLatency::cpu.inst 71581.722320 # average overall miss latency ((Tick/Count))
system.l2.overallAvgMissLatency::cpu.data 67673.957389 # average overall miss latency ((Tick/Count))
system.l2.overallAvgMissLatency::total 67744.650749 # average overall miss latency ((Tick/Count))
system.l2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
system.l2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
system.l2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
system.l2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
system.l2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
system.l2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
system.l2.demandMshrMisses::cpu.inst 569 # number of demand (read+write) MSHR misses (Count)
system.l2.demandMshrMisses::cpu.data 30884 # number of demand (read+write) MSHR misses (Count)
system.l2.demandMshrMisses::total 31453 # number of demand (read+write) MSHR misses (Count)
system.l2.overallMshrMisses::cpu.inst 569 # number of overall MSHR misses (Count)
system.l2.overallMshrMisses::cpu.data 30884 # number of overall MSHR misses (Count)
system.l2.overallMshrMisses::total 31453 # number of overall MSHR misses (Count)
system.l2.demandMshrMissLatency::cpu.inst 35040000 # number of demand (read+write) MSHR miss ticks (Tick)
system.l2.demandMshrMissLatency::cpu.data 1781212500 # number of demand (read+write) MSHR miss ticks (Tick)
system.l2.demandMshrMissLatency::total 1816252500 # number of demand (read+write) MSHR miss ticks (Tick)
system.l2.overallMshrMissLatency::cpu.inst 35040000 # number of overall MSHR miss ticks (Tick)
system.l2.overallMshrMissLatency::cpu.data 1781212500 # number of overall MSHR miss ticks (Tick)
system.l2.overallMshrMissLatency::total 1816252500 # number of overall MSHR miss ticks (Tick)
system.l2.demandMshrMissRate::cpu.inst 0.974315 # mshr miss ratio for demand accesses (Ratio)
system.l2.demandMshrMissRate::cpu.data 0.999870 # mshr miss ratio for demand accesses (Ratio)
system.l2.demandMshrMissRate::total 0.999396 # mshr miss ratio for demand accesses (Ratio)
system.l2.overallMshrMissRate::cpu.inst 0.974315 # mshr miss ratio for overall accesses (Ratio)
system.l2.overallMshrMissRate::cpu.data 0.999870 # mshr miss ratio for overall accesses (Ratio)
system.l2.overallMshrMissRate::total 0.999396 # mshr miss ratio for overall accesses (Ratio)
system.l2.demandAvgMshrMissLatency::cpu.inst 61581.722320 # average overall mshr miss latency ((Tick/Count))
system.l2.demandAvgMshrMissLatency::cpu.data 57674.281181 # average overall mshr miss latency ((Tick/Count))
system.l2.demandAvgMshrMissLatency::total 57744.968683 # average overall mshr miss latency ((Tick/Count))
system.l2.overallAvgMshrMissLatency::cpu.inst 61581.722320 # average overall mshr miss latency ((Tick/Count))
system.l2.overallAvgMshrMissLatency::cpu.data 57674.281181 # average overall mshr miss latency ((Tick/Count))
system.l2.overallAvgMshrMissLatency::total 57744.968683 # average overall mshr miss latency ((Tick/Count))
system.l2.replacements 467 # number of replacements (Count)
system.l2.ReadCleanReq.hits::cpu.inst 15 # number of ReadCleanReq hits (Count)
system.l2.ReadCleanReq.hits::total 15 # number of ReadCleanReq hits (Count)
system.l2.ReadCleanReq.misses::cpu.inst 569 # number of ReadCleanReq misses (Count)
system.l2.ReadCleanReq.misses::total 569 # number of ReadCleanReq misses (Count)
system.l2.ReadCleanReq.missLatency::cpu.inst 40730000 # number of ReadCleanReq miss ticks (Tick)
system.l2.ReadCleanReq.missLatency::total 40730000 # number of ReadCleanReq miss ticks (Tick)
system.l2.ReadCleanReq.accesses::cpu.inst 584 # number of ReadCleanReq accesses(hits+misses) (Count)
system.l2.ReadCleanReq.accesses::total 584 # number of ReadCleanReq accesses(hits+misses) (Count)
system.l2.ReadCleanReq.missRate::cpu.inst 0.974315 # miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.missRate::total 0.974315 # miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.avgMissLatency::cpu.inst 71581.722320 # average ReadCleanReq miss latency ((Tick/Count))
system.l2.ReadCleanReq.avgMissLatency::total 71581.722320 # average ReadCleanReq miss latency ((Tick/Count))
system.l2.ReadCleanReq.mshrMisses::cpu.inst 569 # number of ReadCleanReq MSHR misses (Count)
system.l2.ReadCleanReq.mshrMisses::total 569 # number of ReadCleanReq MSHR misses (Count)
system.l2.ReadCleanReq.mshrMissLatency::cpu.inst 35040000 # number of ReadCleanReq MSHR miss ticks (Tick)
system.l2.ReadCleanReq.mshrMissLatency::total 35040000 # number of ReadCleanReq MSHR miss ticks (Tick)
system.l2.ReadCleanReq.mshrMissRate::cpu.inst 0.974315 # mshr miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.mshrMissRate::total 0.974315 # mshr miss rate for ReadCleanReq accesses (Ratio)
system.l2.ReadCleanReq.avgMshrMissLatency::cpu.inst 61581.722320 # average ReadCleanReq mshr miss latency ((Tick/Count))
system.l2.ReadCleanReq.avgMshrMissLatency::total 61581.722320 # average ReadCleanReq mshr miss latency ((Tick/Count))
system.l2.ReadExReq.hits::cpu.data 2 # number of ReadExReq hits (Count)
system.l2.ReadExReq.hits::total 2 # number of ReadExReq hits (Count)
system.l2.ReadExReq.misses::cpu.data 30154 # number of ReadExReq misses (Count)
system.l2.ReadExReq.misses::total 30154 # number of ReadExReq misses (Count)
system.l2.ReadExReq.missLatency::cpu.data 2038954000 # number of ReadExReq miss ticks (Tick)
system.l2.ReadExReq.missLatency::total 2038954000 # number of ReadExReq miss ticks (Tick)
system.l2.ReadExReq.accesses::cpu.data 30156 # number of ReadExReq accesses(hits+misses) (Count)
system.l2.ReadExReq.accesses::total 30156 # number of ReadExReq accesses(hits+misses) (Count)
system.l2.ReadExReq.missRate::cpu.data 0.999934 # miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.missRate::total 0.999934 # miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.avgMissLatency::cpu.data 67618.027459 # average ReadExReq miss latency ((Tick/Count))
system.l2.ReadExReq.avgMissLatency::total 67618.027459 # average ReadExReq miss latency ((Tick/Count))
system.l2.ReadExReq.mshrMisses::cpu.data 30154 # number of ReadExReq MSHR misses (Count)
system.l2.ReadExReq.mshrMisses::total 30154 # number of ReadExReq MSHR misses (Count)
system.l2.ReadExReq.mshrMissLatency::cpu.data 1737424000 # number of ReadExReq MSHR miss ticks (Tick)
system.l2.ReadExReq.mshrMissLatency::total 1737424000 # number of ReadExReq MSHR miss ticks (Tick)
system.l2.ReadExReq.mshrMissRate::cpu.data 0.999934 # mshr miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.mshrMissRate::total 0.999934 # mshr miss rate for ReadExReq accesses (Ratio)
system.l2.ReadExReq.avgMshrMissLatency::cpu.data 57618.359090 # average ReadExReq mshr miss latency ((Tick/Count))
system.l2.ReadExReq.avgMshrMissLatency::total 57618.359090 # average ReadExReq mshr miss latency ((Tick/Count))
system.l2.ReadSharedReq.hits::cpu.data 2 # number of ReadSharedReq hits (Count)
system.l2.ReadSharedReq.hits::total 2 # number of ReadSharedReq hits (Count)
system.l2.ReadSharedReq.misses::cpu.data 730 # number of ReadSharedReq misses (Count)
system.l2.ReadSharedReq.misses::total 730 # number of ReadSharedReq misses (Count)
system.l2.ReadSharedReq.missLatency::cpu.data 51088500 # number of ReadSharedReq miss ticks (Tick)
system.l2.ReadSharedReq.missLatency::total 51088500 # number of ReadSharedReq miss ticks (Tick)
system.l2.ReadSharedReq.accesses::cpu.data 732 # number of ReadSharedReq accesses(hits+misses) (Count)
system.l2.ReadSharedReq.accesses::total 732 # number of ReadSharedReq accesses(hits+misses) (Count)
system.l2.ReadSharedReq.missRate::cpu.data 0.997268 # miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.missRate::total 0.997268 # miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.avgMissLatency::cpu.data 69984.246575 # average ReadSharedReq miss latency ((Tick/Count))
system.l2.ReadSharedReq.avgMissLatency::total 69984.246575 # average ReadSharedReq miss latency ((Tick/Count))
system.l2.ReadSharedReq.mshrMisses::cpu.data 730 # number of ReadSharedReq MSHR misses (Count)
system.l2.ReadSharedReq.mshrMisses::total 730 # number of ReadSharedReq MSHR misses (Count)
system.l2.ReadSharedReq.mshrMissLatency::cpu.data 43788500 # number of ReadSharedReq MSHR miss ticks (Tick)
system.l2.ReadSharedReq.mshrMissLatency::total 43788500 # number of ReadSharedReq MSHR miss ticks (Tick)
system.l2.ReadSharedReq.mshrMissRate::cpu.data 0.997268 # mshr miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.mshrMissRate::total 0.997268 # mshr miss rate for ReadSharedReq accesses (Ratio)
system.l2.ReadSharedReq.avgMshrMissLatency::cpu.data 59984.246575 # average ReadSharedReq mshr miss latency ((Tick/Count))
system.l2.ReadSharedReq.avgMshrMissLatency::total 59984.246575 # average ReadSharedReq mshr miss latency ((Tick/Count))
system.l2.UpgradeReq.hits::cpu.data 2 # number of UpgradeReq hits (Count)
system.l2.UpgradeReq.hits::total 2 # number of UpgradeReq hits (Count)
system.l2.UpgradeReq.accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) (Count)
system.l2.UpgradeReq.accesses::total 2 # number of UpgradeReq accesses(hits+misses) (Count)
system.l2.WritebackClean.hits::writebacks 176 # number of WritebackClean hits (Count)
system.l2.WritebackClean.hits::total 176 # number of WritebackClean hits (Count)
system.l2.WritebackClean.accesses::writebacks 176 # number of WritebackClean accesses(hits+misses) (Count)
system.l2.WritebackClean.accesses::total 176 # number of WritebackClean accesses(hits+misses) (Count)
system.l2.WritebackDirty.hits::writebacks 29158 # number of WritebackDirty hits (Count)
system.l2.WritebackDirty.hits::total 29158 # number of WritebackDirty hits (Count)
system.l2.WritebackDirty.accesses::writebacks 29158 # number of WritebackDirty accesses(hits+misses) (Count)
system.l2.WritebackDirty.accesses::total 29158 # number of WritebackDirty accesses(hits+misses) (Count)
system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.l2.tags.tagsInUse 15723.487822 # Average ticks per tags in use ((Tick/Count))
system.l2.tags.totalRefs 61512 # Total number of references to valid blocks. (Count)
system.l2.tags.sampledRefs 31452 # Sample count of references to valid blocks. (Count)
system.l2.tags.avgRefs 1.955742 # Average number of references to valid blocks. ((Count/Count))
system.l2.tags.warmupTick 71500 # The tick when the warmup percentage was hit. (Tick)
system.l2.tags.occupancies::cpu.inst 546.070987 # Average occupied blocks per tick, per requestor ((Count/Tick))
system.l2.tags.occupancies::cpu.data 15177.416834 # Average occupied blocks per tick, per requestor ((Count/Tick))
system.l2.tags.avgOccs::cpu.inst 0.016665 # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.avgOccs::cpu.data 0.463178 # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.avgOccs::total 0.479843 # Average percentage of cache occupancy ((Ratio/Tick))
system.l2.tags.occupanciesTaskId::1024 30985 # Occupied blocks per task id (Count)
system.l2.tags.ageTaskId_1024::0 140 # Occupied blocks per task id, per block age (Count)
system.l2.tags.ageTaskId_1024::1 1259 # Occupied blocks per task id, per block age (Count)
system.l2.tags.ageTaskId_1024::2 12598 # Occupied blocks per task id, per block age (Count)
system.l2.tags.ageTaskId_1024::3 16988 # Occupied blocks per task id, per block age (Count)
system.l2.tags.ratioOccsTaskId::1024 0.945587 # Ratio of occupied blocks and all blocks, per task id (Ratio)
system.l2.tags.tagAccesses 523556 # Number of tag accesses (Count)
system.l2.tags.dataAccesses 523556 # Number of data accesses (Count)
system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.mem_ctrls.avgPriority_cpu.inst::samples 569.00 # Average QoS priority value for accepted requests (Count)
system.mem_ctrls.avgPriority_cpu.data::samples 30884.00 # Average QoS priority value for accepted requests (Count)
system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (Second)
system.mem_ctrls.priorityMaxLatency 0.000000568500 # per QoS priority maximum request to response latency (Second)
system.mem_ctrls.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
system.mem_ctrls.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
system.mem_ctrls.numStayReadState 63452 # Number of times bus staying in READ state (Count)
system.mem_ctrls.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
system.mem_ctrls.readReqs 31453 # Number of read requests accepted (Count)
system.mem_ctrls.writeReqs 0 # Number of write requests accepted (Count)
system.mem_ctrls.readBursts 31453 # Number of controller read bursts, including those serviced by the write queue (Count)
system.mem_ctrls.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
system.mem_ctrls.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
system.mem_ctrls.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
system.mem_ctrls.avgRdQLen 1.01 # Average read queue length when enqueuing ((Count/Tick))
system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry (Count)
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry (Count)
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) (Count)
system.mem_ctrls.readPktSize::6 31453 # Read request sizes (log2) (Count)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) (Count)
system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) (Count)
system.mem_ctrls.rdQLenPdf::0 31139 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::1 233 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::2 65 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::3 14 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
system.mem_ctrls.bytesReadSys 2012992 # Total read bytes from the system interface side (Byte)
system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
system.mem_ctrls.avgRdBWSys 896442050.55810761 # Average system read bandwidth in Byte/s ((Byte/Second))
system.mem_ctrls.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
system.mem_ctrls.totGap 2245498500 # Total gap between requests (Tick)
system.mem_ctrls.avgGap 71392.19 # Average gap between requests ((Tick/Count))
system.mem_ctrls.requestorReadBytes::cpu.inst 36416 # Per-requestor bytes read from memory (Byte)
system.mem_ctrls.requestorReadBytes::cpu.data 1976576 # Per-requestor bytes read from memory (Byte)
system.mem_ctrls.requestorReadRate::cpu.inst 16217070.764873405918 # Per-requestor bytes read from memory rate ((Byte/Second))
system.mem_ctrls.requestorReadRate::cpu.data 880224979.793234229088 # Per-requestor bytes read from memory rate ((Byte/Second))
system.mem_ctrls.requestorReadAccesses::cpu.inst 569 # Per-requestor read serviced memory accesses (Count)
system.mem_ctrls.requestorReadAccesses::cpu.data 30884 # Per-requestor read serviced memory accesses (Count)
system.mem_ctrls.requestorReadTotalLat::cpu.inst 14714500 # Per-requestor read total memory access latency (Tick)
system.mem_ctrls.requestorReadTotalLat::cpu.data 677676250 # Per-requestor read total memory access latency (Tick)
system.mem_ctrls.requestorReadAvgLat::cpu.inst 25860.28 # Per-requestor read average memory access latency ((Tick/Count))
system.mem_ctrls.requestorReadAvgLat::cpu.data 21942.63 # Per-requestor read average memory access latency ((Tick/Count))
system.mem_ctrls.dram.bytesRead::cpu.inst 36416 # Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesRead::cpu.data 1976576 # Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesRead::total 2012992 # Number of bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesInstRead::cpu.inst 36416 # Number of instructions bytes read from this memory (Byte)
system.mem_ctrls.dram.bytesInstRead::total 36416 # Number of instructions bytes read from this memory (Byte)
system.mem_ctrls.dram.numReads::cpu.inst 569 # Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numReads::cpu.data 30884 # Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.numReads::total 31453 # Number of read requests responded to by this memory (Count)
system.mem_ctrls.dram.bwRead::cpu.inst 16217071 # Total read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwRead::cpu.data 880224980 # Total read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwRead::total 896442051 # Total read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwInstRead::cpu.inst 16217071 # Instruction read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwInstRead::total 16217071 # Instruction read bandwidth from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::cpu.inst 16217071 # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::cpu.data 880224980 # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.bwTotal::total 896442051 # Total bandwidth to/from this memory ((Byte/Second))
system.mem_ctrls.dram.readBursts 31453 # Number of DRAM read bursts (Count)
system.mem_ctrls.dram.writeBursts 0 # Number of DRAM write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::0 2107 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::1 2116 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::2 1982 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::3 1954 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::4 2041 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::5 2051 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::6 1817 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::7 1792 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::8 1842 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::9 1837 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::10 1829 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::11 1895 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::12 1949 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::13 2054 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::14 2129 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankRdBursts::15 2058 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
system.mem_ctrls.dram.totQLat 102647000 # Total ticks spent queuing (Tick)
system.mem_ctrls.dram.totBusLat 157265000 # Total ticks spent in databus transfers (Tick)
system.mem_ctrls.dram.totMemAccLat 692390750 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
system.mem_ctrls.dram.avgQLat 3263.50 # Average queueing delay per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.avgBusLat 5000.00 # Average bus latency per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.avgMemAccLat 22013.50 # Average memory access latency per DRAM burst ((Tick/Count))
system.mem_ctrls.dram.readRowHits 29129 # Number of row buffer hits during reads (Count)
system.mem_ctrls.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
system.mem_ctrls.dram.readRowHitRate 92.61 # Row buffer hit rate for reads (Ratio)
system.mem_ctrls.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
system.mem_ctrls.dram.bytesPerActivate::samples 2322 # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::mean 866.673557 # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::gmean 751.577488 # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::stdev 296.758610 # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::0-127 88 3.79% 3.79% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::128-255 105 4.52% 8.31% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::256-383 81 3.49% 11.80% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::384-511 71 3.06% 14.86% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::512-639 73 3.14% 18.00% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::640-767 65 2.80% 20.80% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::768-895 107 4.61% 25.41% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::896-1023 60 2.58% 27.99% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::1024-1151 1672 72.01% 100.00% # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesPerActivate::total 2322 # Bytes accessed per row activation (Byte)
system.mem_ctrls.dram.bytesRead 2012992 # Total bytes read (Byte)
system.mem_ctrls.dram.bytesWritten 0 # Total bytes written (Byte)
system.mem_ctrls.dram.avgRdBW 896.442051 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
system.mem_ctrls.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
system.mem_ctrls.dram.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
system.mem_ctrls.dram.busUtil 7.00 # Data bus utilization in percentage (Ratio)
system.mem_ctrls.dram.busUtilRead 7.00 # Data bus utilization in percentage for reads (Ratio)
system.mem_ctrls.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
system.mem_ctrls.dram.pageHitRate 92.61 # Row buffer hit rate, read and write combined (Ratio)
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.mem_ctrls.dram.rank0.actEnergy 8460900 # Energy for activate commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.preEnergy 4489485 # Energy for precharge commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.readEnergy 113240400 # Energy for read commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.refreshEnergy 177016320.000000 # Energy for refresh commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.actBackEnergy 545762460 # Energy for active background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.preBackEnergy 402696000 # Energy for precharge background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.totalEnergy 1251665565 # Total energy per rank (pJ) (Joule)
system.mem_ctrls.dram.rank0.averagePower 557.401940 # Core power per rank (mW) (Watt)
system.mem_ctrls.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE 1034836750 # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::REF 74880000 # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::ACT 1135818250 # Time in different power states (Tick)
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.actEnergy 8132460 # Energy for activate commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.preEnergy 4322505 # Energy for precharge commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.readEnergy 111334020 # Energy for read commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.refreshEnergy 177016320.000000 # Energy for refresh commands per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.actBackEnergy 539091750 # Energy for active background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.preBackEnergy 408313440 # Energy for precharge background per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.totalEnergy 1248210495 # Total energy per rank (pJ) (Joule)
system.mem_ctrls.dram.rank1.averagePower 555.863300 # Core power per rank (mW) (Watt)
system.mem_ctrls.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE 1049698750 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::REF 74880000 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::ACT 1120956250 # Time in different power states (Tick)
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.membus.transDist::ReadResp 1299 # Transaction distribution (Count)
system.membus.transDist::CleanEvict 152 # Transaction distribution (Count)
system.membus.transDist::ReadExReq 30154 # Transaction distribution (Count)
system.membus.transDist::ReadExResp 30153 # Transaction distribution (Count)
system.membus.transDist::ReadSharedReq 1299 # Transaction distribution (Count)
system.membus.pktCount_system.l2.mem_side_port::system.mem_ctrls.port 63057 # Packet count per connected requestor and responder (Count)
system.membus.pktCount_system.l2.mem_side_port::total 63057 # Packet count per connected requestor and responder (Count)
system.membus.pktCount::total 63057 # Packet count per connected requestor and responder (Count)
system.membus.pktSize_system.l2.mem_side_port::system.mem_ctrls.port 2012928 # Cumulative packet size per connected requestor and responder (Byte)
system.membus.pktSize_system.l2.mem_side_port::total 2012928 # Cumulative packet size per connected requestor and responder (Byte)
system.membus.pktSize::total 2012928 # Cumulative packet size per connected requestor and responder (Byte)
system.membus.snoops 0 # Total snoops (Count)
system.membus.snoopTraffic 0 # Total snoop traffic (Byte)
system.membus.snoopFanout::samples 31453 # Request fanout histogram (Count)
system.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
system.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
system.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
system.membus.snoopFanout::0 31453 100.00% 100.00% # Request fanout histogram (Count)
system.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
system.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
system.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
system.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
system.membus.snoopFanout::total 31453 # Request fanout histogram (Count)
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.membus.reqLayer2.occupancy 15802500 # Layer occupancy (ticks) (Tick)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (Ratio)
system.membus.respLayer1.occupancy 85964500 # Layer occupancy (ticks) (Tick)
system.membus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
system.membus.snoop_filter.totRequests 31605 # Total number of requests made to the snoop filter. (Count)
system.membus.snoop_filter.hitSingleRequests 152 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
system.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
system.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
system.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.tol2bus.transDist::ReadResp 1318 # Transaction distribution (Count)
system.tol2bus.transDist::WritebackDirty 29158 # Transaction distribution (Count)
system.tol2bus.transDist::WritebackClean 176 # Transaction distribution (Count)
system.tol2bus.transDist::CleanEvict 1172 # Transaction distribution (Count)
system.tol2bus.transDist::UpgradeReq 2 # Transaction distribution (Count)
system.tol2bus.transDist::UpgradeResp 2 # Transaction distribution (Count)
system.tol2bus.transDist::ReadExReq 30156 # Transaction distribution (Count)
system.tol2bus.transDist::ReadExResp 30155 # Transaction distribution (Count)
system.tol2bus.transDist::ReadCleanReq 586 # Transaction distribution (Count)
system.tol2bus.transDist::ReadSharedReq 732 # Transaction distribution (Count)
system.tol2bus.pktCount_system.cpu.icache.mem_side_port::system.l2.cpu_side_port 1346 # Packet count per connected requestor and responder (Count)
system.tol2bus.pktCount_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port 91642 # Packet count per connected requestor and responder (Count)
system.tol2bus.pktCount::total 92988 # Packet count per connected requestor and responder (Count)
system.tol2bus.pktSize_system.cpu.icache.mem_side_port::system.l2.cpu_side_port 48640 # Cumulative packet size per connected requestor and responder (Byte)
system.tol2bus.pktSize_system.cpu.dcache.mem_side_port::system.l2.cpu_side_port 3842880 # Cumulative packet size per connected requestor and responder (Byte)
system.tol2bus.pktSize::total 3891520 # Cumulative packet size per connected requestor and responder (Byte)
system.tol2bus.snoops 469 # Total snoops (Count)
system.tol2bus.snoopTraffic 128 # Total snoop traffic (Byte)
system.tol2bus.snoopFanout::samples 31943 # Request fanout histogram (Count)
system.tol2bus.snoopFanout::mean 0.009987 # Request fanout histogram (Count)
system.tol2bus.snoopFanout::stdev 0.099434 # Request fanout histogram (Count)
system.tol2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::0 31624 99.00% 99.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::1 319 1.00% 100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
system.tol2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
system.tol2bus.snoopFanout::max_value 1 # Request fanout histogram (Count)
system.tol2bus.snoopFanout::total 31943 # Request fanout histogram (Count)
system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 2245535000 # Cumulative time (in ticks) in various power states (Tick)
system.tol2bus.reqLayer0.occupancy 60091500 # Layer occupancy (ticks) (Tick)
system.tol2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
system.tol2bus.respLayer0.occupancy 879000 # Layer occupancy (ticks) (Tick)
system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
system.tol2bus.respLayer1.occupancy 46331500 # Layer occupancy (ticks) (Tick)
system.tol2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
system.tol2bus.snoop_filter.totRequests 61515 # Total number of requests made to the snoop filter. (Count)
system.tol2bus.snoop_filter.hitSingleRequests 30039 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
system.tol2bus.snoop_filter.hitMultiRequests 4 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.tol2bus.snoop_filter.totSnoops 315 # Total number of snoops made to the snoop filter. (Count)
system.tol2bus.snoop_filter.hitSingleSnoops 315 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
system.tol2bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
system.voltage_domain.voltage 1 # Voltage in Volts (Volt)
system.workload.inst.arm 0 # number of arm instructions executed (Count)
system.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
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