Adding scripts, commands, and logging scaffolding

scripts/hetero_big_little.py

@@ -1,32 +1,95 @@
-# Simple heterogeneous big.LITTLE configuration for SmartEdgeAI
-import m5
+# scripts/hetero_big_little.py
+# Minimal SmartEdgeAI heterogeneous ARM system
+# Supports --cmd, --mem, --l2, --dvfs, and --drowsy
+# Generates valid stats.txt for all workloads
+
+import argparse, m5
 from m5.objects import *
 
-system = System()
-system.clk_domain = SrcClockDomain(clock="1GHz", voltage_domain=VoltageDomain())
-system.mem_mode = "timing"
-system.mem_ranges = [AddrRange("512MB")]
+# -------------------------------
+# Argument parsing
+# -------------------------------
+ap = argparse.ArgumentParser()
+ap.add_argument("--cmd", required=True)
+ap.add_argument("--mem", default="16GB")
+ap.add_argument("--l2", default="1MB")
+ap.add_argument("--dvfs", choices=["high","low"], default="high")
+ap.add_argument("--drowsy", type=int, choices=[0,1], default=0)
+args = ap.parse_args()
 
-# two LITTLE + one BIG
-system.cpu = [TimingSimpleCPU(cpu_id=i) for i in range(3)]
+# -------------------------------
+# Clock & Voltage (DVFS)
+# -------------------------------
+v = VoltageDomain(voltage="1.0V" if args.dvfs == "high" else "0.8V")
+clk = "2GHz" if args.dvfs == "high" else "1GHz"
+
+system = System(
+    clk_domain=SrcClockDomain(clock=clk, voltage_domain=v),
+    mem_mode="timing",
+    mem_ranges=[AddrRange(args.mem)]
+)
+
+# -------------------------------
+# CPU cluster: 1 big + 2 little
+# -------------------------------
+big = O3CPU(cpu_id=0)
+little1 = TimingSimpleCPU(cpu_id=1)
+little2 = TimingSimpleCPU(cpu_id=2)
+system.cpu = [big, little1, little2]
+
+# -------------------------------
+# Cache hierarchy
+# -------------------------------
+class L1I(Cache): size = "32kB"
+class L1D(Cache): size = "32kB"
+class L2(Cache):  size = args.l2
+
+system.l2bus = L2XBar()
+for c in system.cpu:
+    c.icache = L1I()
+    c.dcache = L1D()
+    c.icache.cpu_side = c.icache_port
+    c.dcache.cpu_side = c.dcache_port
+    c.icache.mem_side = system.l2bus.slave
+    c.dcache.mem_side = system.l2bus.slave
+
+system.l2 = L2()
 system.membus = SystemXBar()
+system.l2.cpu_side = system.l2bus.master
+system.l2.mem_side = system.membus.slave
 
-for cpu in system.cpu:
-    cpu.icache_port = system.membus.slave
-    cpu.dcache_port = system.membus.slave
+# -------------------------------
+# Drowsy cache behavior
+# -------------------------------
+if args.drowsy:
+    system.l2.tag_latency = 24
+    system.l2.data_latency = 24
 
-system.system_port = system.membus.slave
+# -------------------------------
+# Memory controller
+# -------------------------------
 system.mem_ctrl = DDR3_1600_8x8()
 system.mem_ctrl.range = system.mem_ranges[0]
 system.mem_ctrl.port = system.membus.master
+system.system_port = system.membus.slave
 
-system.workload = SEWorkload.init_compatible("hello")
-for cpu in system.cpu:
-    cpu.workload = system.workload
-    cpu.createThreads()
+# -------------------------------
+# Workload setup
+# -------------------------------
+proc = Process()
+proc.executable = args.cmd
+proc.cmd = [args.cmd]
+system.workload = SEWorkload.init_compatible(args.cmd)
+for c in system.cpu:
+    c.workload = proc
+    c.createThreads()
 
+# -------------------------------
+# Instantiate and simulate
+# -------------------------------
 root = Root(full_system=False, system=system)
 m5.instantiate()
-print("=== SmartEdgeAI big.LITTLE configuration loaded ===")
+print("[SmartEdgeAI] Starting simulation...")
 exit_event = m5.simulate()
-print("Exit:", exit_event.getCause())
+print(f"[SmartEdgeAI] Exiting @ tick {m5.curTick()} because {exit_event.getCause()}")
+

scripts/hetero_big_little.py.bak

@@ -0,0 +1,32 @@
+# Simple heterogeneous big.LITTLE configuration for SmartEdgeAI
+import m5
+from m5.objects import *
+
+system = System()
+system.clk_domain = SrcClockDomain(clock="1GHz", voltage_domain=VoltageDomain())
+system.mem_mode = "timing"
+system.mem_ranges = [AddrRange("512MB")]
+
+# two LITTLE + one BIG
+system.cpu = [TimingSimpleCPU(cpu_id=i) for i in range(3)]
+system.membus = SystemXBar()
+
+for cpu in system.cpu:
+    cpu.icache_port = system.membus.slave
+    cpu.dcache_port = system.membus.slave
+
+system.system_port = system.membus.slave
+system.mem_ctrl = DDR3_1600_8x8()
+system.mem_ctrl.range = system.mem_ranges[0]
+system.mem_ctrl.port = system.membus.master
+
+system.workload = SEWorkload.init_compatible("hello")
+for cpu in system.cpu:
+    cpu.workload = system.workload
+    cpu.createThreads()
+
+root = Root(full_system=False, system=system)
+m5.instantiate()
+print("=== SmartEdgeAI big.LITTLE configuration loaded ===")
+exit_event = m5.simulate()
+print("Exit:", exit_event.getCause())