updating
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@@ -45,43 +45,16 @@ elif args.core == "hybrid":
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# -------------------------------
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# Cache hierarchy
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# -------------------------------
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class L1I(Cache):
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size = "32kB"
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assoc = 2
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tag_latency = 1
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data_latency = 1
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response_latency = 1
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mshrs = 4
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tgts_per_mshr = 20
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class L1D(Cache):
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size = "32kB"
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assoc = 2
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tag_latency = 1
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data_latency = 1
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response_latency = 1
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mshrs = 4
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tgts_per_mshr = 20
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class L2(Cache):
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size = args.l2
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assoc = 8
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tag_latency = 10
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data_latency = 10
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response_latency = 1
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mshrs = 20
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tgts_per_mshr = 12
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system.l2bus = L2XBar()
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for c in system.cpu:
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c.icache = L1I()
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c.dcache = L1D()
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c.icache = Cache(size="32kB", assoc=2)
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c.dcache = Cache(size="32kB", assoc=2)
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c.icache.cpu_side = c.icache_port
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c.dcache.cpu_side = c.dcache_port
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c.icache.mem_side = system.l2bus.slave
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c.dcache.mem_side = system.l2bus.slave
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system.l2 = L2()
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system.l2 = Cache(size=args.l2, assoc=8)
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system.membus = SystemXBar()
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system.l2.cpu_side = system.l2bus.master
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system.l2.mem_side = system.membus.slave
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