Adding scripts, commands, and logging scaffolding
This commit is contained in:
Carlos Gutierrez
553
m5out_control/config.ini
Normal file
553
m5out_control/config.ini
Normal file
@@ -0,0 +1,553 @@
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[root]
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type=Root
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children=system
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eventq_index=0
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full_system=false
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sim_quantum=0
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler mem_ctrls membus redirect_paths0 redirect_paths1 redirect_paths2 voltage_domain workload
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auto_unlink_shared_backstore=false
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cache_line_size=64
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eventq_index=0
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exit_on_work_items=false
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init_param=0
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m5ops_base=0
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mem_mode=atomic
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mem_ranges=0:536870912
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memories=system.mem_ctrls.dram
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mmap_using_noreserve=false
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multi_thread=false
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num_work_ids=16
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readfile=
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redirect_paths=system.redirect_paths0 system.redirect_paths1 system.redirect_paths2
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shadow_rom_ranges=
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shared_backstore=
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symbolfile=
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thermal_components=
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thermal_model=Null
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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workload=system.workload
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system_port=system.membus.cpu_side_ports[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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domain_id=-1
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eventq_index=0
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init_perf_level=0
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voltage_domain=system.voltage_domain
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[system.cpu]
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type=BaseAtomicSimpleCPU
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children=decoder interrupts isa mmu power_state tracer workload
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branchPred=Null
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checker=Null
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clk_domain=system.cpu_clk_domain
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cpu_id=0
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decoder=system.cpu.decoder
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do_checkpoint_insts=true
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do_statistics_insts=true
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eventq_index=0
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function_trace=false
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function_trace_start=0
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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max_insts_all_threads=0
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max_insts_any_thread=0
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mmu=system.cpu.mmu
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numThreads=1
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power_gating_on_idle=false
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power_model=
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power_state=system.cpu.power_state
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progress_interval=0
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pwr_gating_latency=300
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simpoint_start_insts=
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simulate_data_stalls=false
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simulate_inst_stalls=false
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socket_id=0
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switched_out=false
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syscallRetryLatency=10000
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system=system
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tracer=system.cpu.tracer
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width=1
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workload=system.cpu.workload
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dcache_port=system.membus.cpu_side_ports[2]
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icache_port=system.membus.cpu_side_ports[1]
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[system.cpu.decoder]
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type=ArmDecoder
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dvm_enabled=false
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eventq_index=0
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isa=system.cpu.isa
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[system.cpu.interrupts]
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type=ArmInterrupts
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eventq_index=0
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[system.cpu.isa]
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type=ArmISA
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children=release_se
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decoderFlavor=Generic
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eventq_index=0
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fpsid=1090793632
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id_aa64afr0_el1=0
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id_aa64afr1_el1=0
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id_aa64dfr0_el1=15790086
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id_aa64dfr1_el1=0
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id_aa64isar0_el1=268435456
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id_aa64isar1_el1=16846864
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id_aa64mmfr0_el1=15728642
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id_aa64mmfr1_el1=1052704
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id_aa64mmfr2_el1=65552
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id_isar0=34607377
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id_isar1=34677009
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id_isar2=555950401
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id_isar3=17899825
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id_isar4=268501314
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id_isar5=285212672
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id_isar6=1
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id_mmfr0=270536963
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id_mmfr1=0
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id_mmfr2=19070976
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id_mmfr3=34611729
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id_mmfr4=0
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impdef_nop=false
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midr=0
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pmu=Null
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release_se=system.cpu.isa.release_se
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sme_vl_se=1
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sve_vl_se=1
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system=system
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[system.cpu.isa.release_se]
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type=ArmRelease
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eventq_index=0
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extensions=CRYPTO FEAT_LSE FEAT_RDM FEAT_F32MM FEAT_F64MM FEAT_SVE FEAT_I8MM FEAT_DOTPROD FEAT_FCMA FEAT_JSCVT FEAT_PAuth FEAT_FLAGM FEAT_FLAGM2 FEAT_SME TME
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[system.cpu.mmu]
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type=ArmMMU
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children=dtb dtb_walker itb itb_walker l2_shared stage2_dtb stage2_dtb_walker stage2_itb stage2_itb_walker
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dtb=system.cpu.mmu.dtb
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dtb_walker=system.cpu.mmu.dtb_walker
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eventq_index=0
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itb=system.cpu.mmu.itb
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itb_walker=system.cpu.mmu.itb_walker
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release_se=system.cpu.isa.release_se
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stage2_dtb=system.cpu.mmu.stage2_dtb
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stage2_dtb_walker=system.cpu.mmu.stage2_dtb_walker
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stage2_itb=system.cpu.mmu.stage2_itb
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stage2_itb_walker=system.cpu.mmu.stage2_itb_walker
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sys=system
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[system.cpu.mmu.dtb]
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type=ArmTLB
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entry_type=data
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eventq_index=0
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is_stage2=false
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next_level=system.cpu.mmu.l2_shared
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partial_levels=
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size=64
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sys=system
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[system.cpu.mmu.dtb_walker]
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type=ArmTableWalker
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children=power_state
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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is_stage2=false
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num_squash_per_cycle=2
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power_model=
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power_state=system.cpu.mmu.dtb_walker.power_state
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sys=system
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port=system.membus.cpu_side_ports[4]
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[system.cpu.mmu.dtb_walker.power_state]
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type=PowerState
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clk_gate_bins=20
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clk_gate_max=1000000000000
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clk_gate_min=1000
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default_state=UNDEFINED
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eventq_index=0
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leaders=
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possible_states=
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[system.cpu.mmu.itb]
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type=ArmTLB
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entry_type=instruction
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eventq_index=0
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is_stage2=false
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next_level=system.cpu.mmu.l2_shared
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partial_levels=
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size=64
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sys=system
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[system.cpu.mmu.itb_walker]
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type=ArmTableWalker
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children=power_state
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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is_stage2=false
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num_squash_per_cycle=2
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power_model=
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power_state=system.cpu.mmu.itb_walker.power_state
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sys=system
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port=system.membus.cpu_side_ports[3]
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[system.cpu.mmu.itb_walker.power_state]
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type=PowerState
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clk_gate_bins=20
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clk_gate_max=1000000000000
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clk_gate_min=1000
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default_state=UNDEFINED
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eventq_index=0
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leaders=
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possible_states=
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[system.cpu.mmu.l2_shared]
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type=ArmTLB
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entry_type=unified
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eventq_index=0
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is_stage2=false
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next_level=Null
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partial_levels=L2
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size=1280
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sys=system
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[system.cpu.mmu.stage2_dtb]
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type=ArmTLB
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entry_type=data
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eventq_index=0
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is_stage2=true
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next_level=Null
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partial_levels=
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size=32
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sys=system
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[system.cpu.mmu.stage2_dtb_walker]
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type=ArmTableWalker
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children=power_state
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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is_stage2=true
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num_squash_per_cycle=2
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power_model=
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power_state=system.cpu.mmu.stage2_dtb_walker.power_state
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sys=system
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port=system.membus.cpu_side_ports[6]
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[system.cpu.mmu.stage2_dtb_walker.power_state]
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type=PowerState
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clk_gate_bins=20
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clk_gate_max=1000000000000
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clk_gate_min=1000
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default_state=UNDEFINED
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eventq_index=0
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leaders=
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possible_states=
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[system.cpu.mmu.stage2_itb]
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type=ArmTLB
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entry_type=instruction
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eventq_index=0
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is_stage2=true
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next_level=Null
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partial_levels=
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size=32
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sys=system
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[system.cpu.mmu.stage2_itb_walker]
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type=ArmTableWalker
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children=power_state
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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is_stage2=true
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num_squash_per_cycle=2
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power_model=
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power_state=system.cpu.mmu.stage2_itb_walker.power_state
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sys=system
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port=system.membus.cpu_side_ports[5]
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[system.cpu.mmu.stage2_itb_walker.power_state]
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type=PowerState
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clk_gate_bins=20
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clk_gate_max=1000000000000
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clk_gate_min=1000
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default_state=UNDEFINED
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eventq_index=0
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leaders=
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possible_states=
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[system.cpu.power_state]
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type=PowerState
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clk_gate_bins=20
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clk_gate_max=1000000000000
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clk_gate_min=1000
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default_state=UNDEFINED
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eventq_index=0
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leaders=
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possible_states=ON CLK_GATED OFF
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[system.cpu.tracer]
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type=ExeTracer
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eventq_index=0
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[system.cpu.workload]
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type=Process
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cmd=/home/carlos/projects/gem5/gem5-run/tinyml_kws
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cwd=/home/carlos/projects/gem5/iot
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drivers=
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egid=100
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env=
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errout=cerr
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euid=100
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eventq_index=0
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executable=/home/carlos/projects/gem5/gem5-run/tinyml_kws
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gid=1000
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input=cin
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kvmInSE=false
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maxStackSize=67108864
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output=cout
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pgid=100
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pid=100
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ppid=0
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release=5.1.0
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simpoint=0
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system=system
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uid=100
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useArchPT=false
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[system.cpu_clk_domain]
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type=SrcClockDomain
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clock=500
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domain_id=-1
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eventq_index=0
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init_perf_level=0
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voltage_domain=system.cpu_voltage_domain
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[system.cpu_voltage_domain]
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type=VoltageDomain
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eventq_index=0
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voltage=1.0
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[system.dvfs_handler]
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type=DVFSHandler
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domains=
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enable=false
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eventq_index=0
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sys_clk_domain=system.clk_domain
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transition_latency=100000000
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[system.mem_ctrls]
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type=MemCtrl
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children=dram power_state
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clk_domain=system.clk_domain
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command_window=10000
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disable_sanity_check=false
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dram=system.mem_ctrls.dram
|
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eventq_index=0
|
||||
mem_sched_policy=frfcfs
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||||
min_reads_per_switch=16
|
||||
min_writes_per_switch=16
|
||||
power_model=
|
||||
power_state=system.mem_ctrls.power_state
|
||||
qos_policy=Null
|
||||
qos_priorities=1
|
||||
qos_priority_escalation=false
|
||||
qos_q_policy=fifo
|
||||
qos_requestors=
|
||||
qos_syncro_scheduler=false
|
||||
qos_turnaround_policy=Null
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
system=system
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.mem_side_ports[0]
|
||||
|
||||
[system.mem_ctrls.dram]
|
||||
type=DRAMInterface
|
||||
children=power_state
|
||||
IDD0=0.055
|
||||
IDD02=0.0
|
||||
IDD2N=0.032
|
||||
IDD2N2=0.0
|
||||
IDD2P0=0.0
|
||||
IDD2P02=0.0
|
||||
IDD2P1=0.032
|
||||
IDD2P12=0.0
|
||||
IDD3N=0.038
|
||||
IDD3N2=0.0
|
||||
IDD3P0=0.0
|
||||
IDD3P02=0.0
|
||||
IDD3P1=0.038
|
||||
IDD3P12=0.0
|
||||
IDD4R=0.157
|
||||
IDD4R2=0.0
|
||||
IDD4W=0.125
|
||||
IDD4W2=0.0
|
||||
IDD5=0.23500000000000001
|
||||
IDD52=0.0
|
||||
IDD6=0.02
|
||||
IDD62=0.0
|
||||
VDD=1.5
|
||||
VDD2=0.0
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
beats_per_clock=2
|
||||
burst_length=8
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
data_clock_sync=false
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
enable_dram_powerdown=false
|
||||
eventq_index=0
|
||||
image_file=
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
power_model=
|
||||
power_state=system.mem_ctrls.dram.power_state
|
||||
range=0:536870912
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
tAAD=1250
|
||||
tBURST=5000
|
||||
tBURST_MAX=5000
|
||||
tBURST_MIN=5000
|
||||
tCCD_L=0
|
||||
tCCD_L_WR=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tCWL=13750
|
||||
tPPD=0
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tRCD_WR=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tWTR_L=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
two_cycle_activate=false
|
||||
write_buffer_size=64
|
||||
writeable=true
|
||||
|
||||
[system.mem_ctrls.dram.power_state]
|
||||
type=PowerState
|
||||
clk_gate_bins=20
|
||||
clk_gate_max=1000000000000
|
||||
clk_gate_min=1000
|
||||
default_state=UNDEFINED
|
||||
eventq_index=0
|
||||
leaders=
|
||||
possible_states=
|
||||
|
||||
[system.mem_ctrls.power_state]
|
||||
type=PowerState
|
||||
clk_gate_bins=20
|
||||
clk_gate_max=1000000000000
|
||||
clk_gate_min=1000
|
||||
default_state=UNDEFINED
|
||||
eventq_index=0
|
||||
leaders=
|
||||
possible_states=
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=power_state snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
header_latency=1
|
||||
max_outstanding_snoops=512
|
||||
max_routing_table_size=512
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
power_state=system.membus.power_state
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
cpu_side_ports=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.mmu.itb_walker.port system.cpu.mmu.dtb_walker.port system.cpu.mmu.stage2_itb_walker.port system.cpu.mmu.stage2_dtb_walker.port
|
||||
mem_side_ports=system.mem_ctrls.port
|
||||
|
||||
[system.membus.power_state]
|
||||
type=PowerState
|
||||
clk_gate_bins=20
|
||||
clk_gate_max=1000000000000
|
||||
clk_gate_min=1000
|
||||
default_state=UNDEFINED
|
||||
eventq_index=0
|
||||
leaders=
|
||||
possible_states=
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.redirect_paths0]
|
||||
type=RedirectPath
|
||||
app_path=/proc
|
||||
eventq_index=0
|
||||
host_paths=/home/carlos/projects/gem5/iot/m5out_control/fs/proc
|
||||
|
||||
[system.redirect_paths1]
|
||||
type=RedirectPath
|
||||
app_path=/sys
|
||||
eventq_index=0
|
||||
host_paths=/home/carlos/projects/gem5/iot/m5out_control/fs/sys
|
||||
|
||||
[system.redirect_paths2]
|
||||
type=RedirectPath
|
||||
app_path=/tmp
|
||||
eventq_index=0
|
||||
host_paths=/home/carlos/projects/gem5/iot/m5out_control/fs/tmp
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.workload]
|
||||
type=ArmEmuLinux
|
||||
eventq_index=0
|
||||
remote_gdb_port=#7000
|
||||
wait_for_remote_gdb=false
|
||||
|
||||
Reference in New Issue
Block a user