This commit is contained in:
Carlos Gutierrez
2025-10-05 00:31:30 -04:00
parent 798cd14f41
commit 7ccc68fd36

View File

@@ -16,7 +16,8 @@ args = ap.parse_args()
# Create system
system = System()
system.clk_domain = SrcClockDomain(clock="2GHz" if args.dvfs == "high" else "1GHz")
system.clk_domain = SrcClockDomain(clock="2GHz" if args.dvfs == "high" else "1GHz",
voltage_domain=VoltageDomain())
system.mem_mode = "timing"
system.mem_ranges = [AddrRange(args.mem)]