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This commit is contained in:
Carlos Gutierrez
2025-10-05 00:25:51 -04:00
parent 756998ec2b
commit b1d73cdb6b
2 changed files with 7 additions and 7 deletions
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2
scripts/env.sh
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@@ -6,7 +6,7 @@ SRC="$ROOT/gem5src/gem5"
IOT="$ROOT/iot"
DATA="$ROOT/gem5-data" # persistent (symlink to /mnt/storage/…)
RUN="$ROOT/gem5-run" # workloads
CFG="$ROOT/gem5src/gem5/configs/example/arm/starter_se.py"
CFG="$(dirname "$0")/hetero_big_little.py"
# --- build target (ARM by default) ---
# Updated path based on tree.log analysis: ../gem5src/gem5/build/ARM/gem5.opt

12
scripts/hetero_big_little.py
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@@ -55,13 +55,13 @@ for c in system.cpu:
c.dcache = L1D()
c.icache.cpu_side = c.icache_port
c.dcache.cpu_side = c.dcache_port
c.icache.mem_side = system.l2bus.slave
c.dcache.mem_side = system.l2bus.slave
c.icache.mem_side = system.l2bus.cpu_side_ports
c.dcache.mem_side = system.l2bus.cpu_side_ports
system.l2 = L2()
system.membus = SystemXBar()
system.l2.cpu_side = system.l2bus.master
system.l2.mem_side = system.membus.slave
system.l2.cpu_side = system.l2bus.mem_side_ports
system.l2.mem_side = system.membus.cpu_side_ports
# -------------------------------
# Drowsy cache behavior
@@ -75,8 +75,8 @@ if args.drowsy:
# -------------------------------
system.mem_ctrl = DDR3_1600_8x8()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
system.system_port = system.membus.slave
system.mem_ctrl.port = system.membus.mem_side_ports
system.system_port = system.membus.cpu_side_ports
# -------------------------------
# Workload setup