757 lines
29 KiB
JSON
757 lines
29 KiB
JSON
{
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|
"type": "Root",
|
|
"cxx_class": "gem5::Root",
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|
"name": null,
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|
"path": "root",
|
|
"eventq_index": 0,
|
|
"full_system": false,
|
|
"sim_quantum": 0,
|
|
"time_sync_enable": false,
|
|
"time_sync_period": 100000000000,
|
|
"time_sync_spin_threshold": 100000000,
|
|
"system": {
|
|
"type": "System",
|
|
"cxx_class": "gem5::System",
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|
"name": "system",
|
|
"path": "system",
|
|
"auto_unlink_shared_backstore": false,
|
|
"cache_line_size": 64,
|
|
"eventq_index": 0,
|
|
"exit_on_work_items": false,
|
|
"init_param": 0,
|
|
"m5ops_base": 0,
|
|
"mem_mode": "atomic",
|
|
"mem_ranges": [
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|
"0:536870912"
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|
],
|
|
"memories": [
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|
"system.mem_ctrls.dram"
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|
],
|
|
"mmap_using_noreserve": false,
|
|
"multi_thread": false,
|
|
"num_work_ids": 16,
|
|
"readfile": "",
|
|
"redirect_paths": [
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|
{
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|
"type": "RedirectPath",
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"cxx_class": "gem5::RedirectPath",
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"name": "redirect_paths0",
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|
"path": "system.redirect_paths0",
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"app_path": "/proc",
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"eventq_index": 0,
|
|
"host_paths": [
|
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"/home/carlos/projects/gem5/iot/m5out_control/fs/proc"
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]
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},
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|
{
|
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"type": "RedirectPath",
|
|
"cxx_class": "gem5::RedirectPath",
|
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"name": "redirect_paths1",
|
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"path": "system.redirect_paths1",
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"app_path": "/sys",
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"eventq_index": 0,
|
|
"host_paths": [
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"/home/carlos/projects/gem5/iot/m5out_control/fs/sys"
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]
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},
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{
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"type": "RedirectPath",
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"cxx_class": "gem5::RedirectPath",
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"name": "redirect_paths2",
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"path": "system.redirect_paths2",
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"app_path": "/tmp",
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|
"eventq_index": 0,
|
|
"host_paths": [
|
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"/home/carlos/projects/gem5/iot/m5out_control/fs/tmp"
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]
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|
}
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|
],
|
|
"shadow_rom_ranges": [],
|
|
"shared_backstore": "",
|
|
"symbolfile": "",
|
|
"thermal_components": [],
|
|
"thermal_model": null,
|
|
"work_begin_ckpt_count": 0,
|
|
"work_begin_cpu_id_exit": -1,
|
|
"work_begin_exit_count": 0,
|
|
"work_cpus_ckpt_count": 0,
|
|
"work_end_ckpt_count": 0,
|
|
"work_end_exit_count": 0,
|
|
"work_item_id": -1,
|
|
"workload": {
|
|
"type": "ArmEmuLinux",
|
|
"cxx_class": "gem5::ArmISA::EmuLinux",
|
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"name": "workload",
|
|
"path": "system.workload",
|
|
"eventq_index": 0,
|
|
"remote_gdb_port": "#7000",
|
|
"wait_for_remote_gdb": false
|
|
},
|
|
"clk_domain": {
|
|
"type": "SrcClockDomain",
|
|
"cxx_class": "gem5::SrcClockDomain",
|
|
"name": "clk_domain",
|
|
"path": "system.clk_domain",
|
|
"clock": [
|
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1000
|
|
],
|
|
"domain_id": -1,
|
|
"eventq_index": 0,
|
|
"init_perf_level": 0,
|
|
"voltage_domain": "system.voltage_domain"
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|
},
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"cpu": [
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{
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"type": "BaseAtomicSimpleCPU",
|
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"cxx_class": "gem5::AtomicSimpleCPU",
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"name": "cpu",
|
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"path": "system.cpu",
|
|
"branchPred": null,
|
|
"checker": null,
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
"cpu_id": 0,
|
|
"decoder": [
|
|
{
|
|
"type": "ArmDecoder",
|
|
"cxx_class": "gem5::ArmISA::Decoder",
|
|
"name": "decoder",
|
|
"path": "system.cpu.decoder",
|
|
"dvm_enabled": false,
|
|
"eventq_index": 0,
|
|
"isa": "system.cpu.isa"
|
|
}
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|
],
|
|
"do_checkpoint_insts": true,
|
|
"do_statistics_insts": true,
|
|
"eventq_index": 0,
|
|
"function_trace": false,
|
|
"function_trace_start": 0,
|
|
"interrupts": [
|
|
{
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|
"type": "ArmInterrupts",
|
|
"cxx_class": "gem5::ArmISA::Interrupts",
|
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"name": "interrupts",
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|
"path": "system.cpu.interrupts",
|
|
"eventq_index": 0
|
|
}
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],
|
|
"isa": [
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{
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"type": "ArmISA",
|
|
"cxx_class": "gem5::ArmISA::ISA",
|
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"name": "isa",
|
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"path": "system.cpu.isa",
|
|
"decoderFlavor": "Generic",
|
|
"eventq_index": 0,
|
|
"fpsid": 1090793632,
|
|
"id_aa64afr0_el1": 0,
|
|
"id_aa64afr1_el1": 0,
|
|
"id_aa64dfr0_el1": 15790086,
|
|
"id_aa64dfr1_el1": 0,
|
|
"id_aa64isar0_el1": 268435456,
|
|
"id_aa64isar1_el1": 16846864,
|
|
"id_aa64mmfr0_el1": 15728642,
|
|
"id_aa64mmfr1_el1": 1052704,
|
|
"id_aa64mmfr2_el1": 65552,
|
|
"id_isar0": 34607377,
|
|
"id_isar1": 34677009,
|
|
"id_isar2": 555950401,
|
|
"id_isar3": 17899825,
|
|
"id_isar4": 268501314,
|
|
"id_isar5": 285212672,
|
|
"id_isar6": 1,
|
|
"id_mmfr0": 270536963,
|
|
"id_mmfr1": 0,
|
|
"id_mmfr2": 19070976,
|
|
"id_mmfr3": 34611729,
|
|
"id_mmfr4": 0,
|
|
"impdef_nop": false,
|
|
"midr": 0,
|
|
"pmu": null,
|
|
"release_se": {
|
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"type": "ArmRelease",
|
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"cxx_class": "gem5::ArmRelease",
|
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"name": "release_se",
|
|
"path": "system.cpu.isa.release_se",
|
|
"eventq_index": 0,
|
|
"extensions": [
|
|
"CRYPTO",
|
|
"FEAT_LSE",
|
|
"FEAT_RDM",
|
|
"FEAT_F32MM",
|
|
"FEAT_F64MM",
|
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"FEAT_SVE",
|
|
"FEAT_I8MM",
|
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"FEAT_DOTPROD",
|
|
"FEAT_FCMA",
|
|
"FEAT_JSCVT",
|
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"FEAT_PAuth",
|
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"FEAT_FLAGM",
|
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"FEAT_FLAGM2",
|
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"FEAT_SME",
|
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"TME"
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]
|
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},
|
|
"sme_vl_se": 1,
|
|
"sve_vl_se": 1,
|
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"system": "system"
|
|
}
|
|
],
|
|
"max_insts_all_threads": 0,
|
|
"max_insts_any_thread": 0,
|
|
"mmu": {
|
|
"type": "ArmMMU",
|
|
"cxx_class": "gem5::ArmISA::MMU",
|
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"name": "mmu",
|
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"path": "system.cpu.mmu",
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"dtb": {
|
|
"type": "ArmTLB",
|
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"cxx_class": "gem5::ArmISA::TLB",
|
|
"name": "dtb",
|
|
"path": "system.cpu.mmu.dtb",
|
|
"entry_type": "data",
|
|
"eventq_index": 0,
|
|
"is_stage2": false,
|
|
"next_level": "system.cpu.mmu.l2_shared",
|
|
"partial_levels": [],
|
|
"size": 64,
|
|
"sys": "system"
|
|
},
|
|
"dtb_walker": {
|
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"type": "ArmTableWalker",
|
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"cxx_class": "gem5::ArmISA::TableWalker",
|
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"name": "dtb_walker",
|
|
"path": "system.cpu.mmu.dtb_walker",
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
"eventq_index": 0,
|
|
"is_stage2": false,
|
|
"num_squash_per_cycle": 2,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "system.cpu.mmu.dtb_walker.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
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|
},
|
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"sys": "system",
|
|
"port": {
|
|
"role": "GEM5 REQUESTOR",
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"peer": "system.membus.cpu_side_ports[4]",
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|
"is_source": "True"
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|
}
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|
},
|
|
"eventq_index": 0,
|
|
"itb": {
|
|
"type": "ArmTLB",
|
|
"cxx_class": "gem5::ArmISA::TLB",
|
|
"name": "itb",
|
|
"path": "system.cpu.mmu.itb",
|
|
"entry_type": "instruction",
|
|
"eventq_index": 0,
|
|
"is_stage2": false,
|
|
"next_level": "system.cpu.mmu.l2_shared",
|
|
"partial_levels": [],
|
|
"size": 64,
|
|
"sys": "system"
|
|
},
|
|
"itb_walker": {
|
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"type": "ArmTableWalker",
|
|
"cxx_class": "gem5::ArmISA::TableWalker",
|
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"name": "itb_walker",
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"path": "system.cpu.mmu.itb_walker",
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
"eventq_index": 0,
|
|
"is_stage2": false,
|
|
"num_squash_per_cycle": 2,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "system.cpu.mmu.itb_walker.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"sys": "system",
|
|
"port": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": "system.membus.cpu_side_ports[3]",
|
|
"is_source": "True"
|
|
}
|
|
},
|
|
"release_se": "system.cpu.isa.release_se",
|
|
"stage2_dtb": {
|
|
"type": "ArmTLB",
|
|
"cxx_class": "gem5::ArmISA::TLB",
|
|
"name": "stage2_dtb",
|
|
"path": "system.cpu.mmu.stage2_dtb",
|
|
"entry_type": "data",
|
|
"eventq_index": 0,
|
|
"is_stage2": true,
|
|
"next_level": null,
|
|
"partial_levels": [],
|
|
"size": 32,
|
|
"sys": "system"
|
|
},
|
|
"stage2_dtb_walker": {
|
|
"type": "ArmTableWalker",
|
|
"cxx_class": "gem5::ArmISA::TableWalker",
|
|
"name": "stage2_dtb_walker",
|
|
"path": "system.cpu.mmu.stage2_dtb_walker",
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
"eventq_index": 0,
|
|
"is_stage2": true,
|
|
"num_squash_per_cycle": 2,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "system.cpu.mmu.stage2_dtb_walker.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"sys": "system",
|
|
"port": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": "system.membus.cpu_side_ports[6]",
|
|
"is_source": "True"
|
|
}
|
|
},
|
|
"stage2_itb": {
|
|
"type": "ArmTLB",
|
|
"cxx_class": "gem5::ArmISA::TLB",
|
|
"name": "stage2_itb",
|
|
"path": "system.cpu.mmu.stage2_itb",
|
|
"entry_type": "instruction",
|
|
"eventq_index": 0,
|
|
"is_stage2": true,
|
|
"next_level": null,
|
|
"partial_levels": [],
|
|
"size": 32,
|
|
"sys": "system"
|
|
},
|
|
"stage2_itb_walker": {
|
|
"type": "ArmTableWalker",
|
|
"cxx_class": "gem5::ArmISA::TableWalker",
|
|
"name": "stage2_itb_walker",
|
|
"path": "system.cpu.mmu.stage2_itb_walker",
|
|
"clk_domain": "system.cpu_clk_domain",
|
|
"eventq_index": 0,
|
|
"is_stage2": true,
|
|
"num_squash_per_cycle": 2,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "system.cpu.mmu.stage2_itb_walker.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"sys": "system",
|
|
"port": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": "system.membus.cpu_side_ports[5]",
|
|
"is_source": "True"
|
|
}
|
|
},
|
|
"sys": "system",
|
|
"l2_shared": {
|
|
"type": "ArmTLB",
|
|
"cxx_class": "gem5::ArmISA::TLB",
|
|
"name": "l2_shared",
|
|
"path": "system.cpu.mmu.l2_shared",
|
|
"entry_type": "unified",
|
|
"eventq_index": 0,
|
|
"is_stage2": false,
|
|
"next_level": null,
|
|
"partial_levels": [
|
|
"L2"
|
|
],
|
|
"size": 1280,
|
|
"sys": "system"
|
|
}
|
|
},
|
|
"numThreads": 1,
|
|
"power_gating_on_idle": false,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "system.cpu.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": [
|
|
"ON",
|
|
"CLK_GATED",
|
|
"OFF"
|
|
]
|
|
},
|
|
"progress_interval": 0,
|
|
"pwr_gating_latency": 300,
|
|
"simpoint_start_insts": [],
|
|
"simulate_data_stalls": false,
|
|
"simulate_inst_stalls": false,
|
|
"socket_id": 0,
|
|
"switched_out": false,
|
|
"syscallRetryLatency": 10000,
|
|
"system": "system",
|
|
"tracer": {
|
|
"type": "ExeTracer",
|
|
"cxx_class": "gem5::trace::ExeTracer",
|
|
"name": "tracer",
|
|
"path": "system.cpu.tracer",
|
|
"eventq_index": 0
|
|
},
|
|
"width": 1,
|
|
"workload": [
|
|
{
|
|
"type": "Process",
|
|
"cxx_class": "gem5::Process",
|
|
"name": "workload",
|
|
"path": "system.cpu.workload",
|
|
"cmd": [
|
|
"/home/carlos/projects/gem5/gem5-run/tinyml_kws"
|
|
],
|
|
"cwd": "/home/carlos/projects/gem5/iot",
|
|
"drivers": [],
|
|
"egid": 100,
|
|
"env": [],
|
|
"errout": "cerr",
|
|
"euid": 100,
|
|
"eventq_index": 0,
|
|
"executable": "/home/carlos/projects/gem5/gem5-run/tinyml_kws",
|
|
"gid": 1000,
|
|
"input": "cin",
|
|
"kvmInSE": false,
|
|
"maxStackSize": 67108864,
|
|
"output": "cout",
|
|
"pgid": 100,
|
|
"pid": 100,
|
|
"ppid": 0,
|
|
"release": "5.1.0",
|
|
"simpoint": 0,
|
|
"system": "system",
|
|
"uid": 100,
|
|
"useArchPT": false
|
|
}
|
|
],
|
|
"dcache_port": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": "system.membus.cpu_side_ports[2]",
|
|
"is_source": "True"
|
|
},
|
|
"icache_port": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": "system.membus.cpu_side_ports[1]",
|
|
"is_source": "True"
|
|
}
|
|
}
|
|
],
|
|
"cpu_clk_domain": {
|
|
"type": "SrcClockDomain",
|
|
"cxx_class": "gem5::SrcClockDomain",
|
|
"name": "cpu_clk_domain",
|
|
"path": "system.cpu_clk_domain",
|
|
"clock": [
|
|
500
|
|
],
|
|
"domain_id": -1,
|
|
"eventq_index": 0,
|
|
"init_perf_level": 0,
|
|
"voltage_domain": "system.cpu_voltage_domain"
|
|
},
|
|
"cpu_voltage_domain": {
|
|
"type": "VoltageDomain",
|
|
"cxx_class": "gem5::VoltageDomain",
|
|
"name": "cpu_voltage_domain",
|
|
"path": "system.cpu_voltage_domain",
|
|
"eventq_index": 0,
|
|
"voltage": [
|
|
1.0
|
|
]
|
|
},
|
|
"dvfs_handler": {
|
|
"type": "DVFSHandler",
|
|
"cxx_class": "gem5::DVFSHandler",
|
|
"name": "dvfs_handler",
|
|
"path": "system.dvfs_handler",
|
|
"domains": [],
|
|
"enable": false,
|
|
"eventq_index": 0,
|
|
"sys_clk_domain": "system.clk_domain",
|
|
"transition_latency": 100000000
|
|
},
|
|
"mem_ctrls": [
|
|
{
|
|
"type": "MemCtrl",
|
|
"cxx_class": "gem5::memory::MemCtrl",
|
|
"name": "mem_ctrls",
|
|
"path": "system.mem_ctrls",
|
|
"clk_domain": "system.clk_domain",
|
|
"command_window": 10000,
|
|
"disable_sanity_check": false,
|
|
"dram": {
|
|
"type": "DRAMInterface",
|
|
"cxx_class": "gem5::memory::DRAMInterface",
|
|
"name": "dram",
|
|
"path": "system.mem_ctrls.dram",
|
|
"IDD0": 0.055,
|
|
"IDD02": 0.0,
|
|
"IDD2N": 0.032,
|
|
"IDD2N2": 0.0,
|
|
"IDD2P0": 0.0,
|
|
"IDD2P02": 0.0,
|
|
"IDD2P1": 0.032,
|
|
"IDD2P12": 0.0,
|
|
"IDD3N": 0.038,
|
|
"IDD3N2": 0.0,
|
|
"IDD3P0": 0.0,
|
|
"IDD3P02": 0.0,
|
|
"IDD3P1": 0.038,
|
|
"IDD3P12": 0.0,
|
|
"IDD4R": 0.157,
|
|
"IDD4R2": 0.0,
|
|
"IDD4W": 0.125,
|
|
"IDD4W2": 0.0,
|
|
"IDD5": 0.23500000000000001,
|
|
"IDD52": 0.0,
|
|
"IDD6": 0.02,
|
|
"IDD62": 0.0,
|
|
"VDD": 1.5,
|
|
"VDD2": 0.0,
|
|
"activation_limit": 4,
|
|
"addr_mapping": "RoRaBaCoCh",
|
|
"bank_groups_per_rank": 0,
|
|
"banks_per_rank": 8,
|
|
"beats_per_clock": 2,
|
|
"burst_length": 8,
|
|
"clk_domain": "system.clk_domain",
|
|
"conf_table_reported": true,
|
|
"data_clock_sync": false,
|
|
"device_bus_width": 8,
|
|
"device_rowbuffer_size": 1024,
|
|
"device_size": 536870912,
|
|
"devices_per_rank": 8,
|
|
"dll": true,
|
|
"enable_dram_powerdown": false,
|
|
"eventq_index": 0,
|
|
"image_file": "",
|
|
"in_addr_map": true,
|
|
"kvm_map": true,
|
|
"max_accesses_per_row": 16,
|
|
"null": false,
|
|
"page_policy": "open_adaptive",
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "system.mem_ctrls.dram.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"range": "0:536870912",
|
|
"ranks_per_channel": 2,
|
|
"read_buffer_size": 32,
|
|
"tAAD": 1250,
|
|
"tBURST": 5000,
|
|
"tBURST_MAX": 5000,
|
|
"tBURST_MIN": 5000,
|
|
"tCCD_L": 0,
|
|
"tCCD_L_WR": 0,
|
|
"tCK": 1250,
|
|
"tCL": 13750,
|
|
"tCS": 2500,
|
|
"tCWL": 13750,
|
|
"tPPD": 0,
|
|
"tRAS": 35000,
|
|
"tRCD": 13750,
|
|
"tRCD_WR": 13750,
|
|
"tREFI": 7800000,
|
|
"tRFC": 260000,
|
|
"tRP": 13750,
|
|
"tRRD": 6000,
|
|
"tRRD_L": 0,
|
|
"tRTP": 7500,
|
|
"tRTW": 2500,
|
|
"tWR": 15000,
|
|
"tWTR": 7500,
|
|
"tWTR_L": 7500,
|
|
"tXAW": 30000,
|
|
"tXP": 6000,
|
|
"tXPDLL": 0,
|
|
"tXS": 270000,
|
|
"tXSDLL": 0,
|
|
"two_cycle_activate": false,
|
|
"write_buffer_size": 64,
|
|
"writeable": true
|
|
},
|
|
"eventq_index": 0,
|
|
"mem_sched_policy": "frfcfs",
|
|
"min_reads_per_switch": 16,
|
|
"min_writes_per_switch": 16,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "system.mem_ctrls.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"qos_policy": null,
|
|
"qos_priorities": 1,
|
|
"qos_priority_escalation": false,
|
|
"qos_q_policy": "fifo",
|
|
"qos_requestors": [
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
""
|
|
],
|
|
"qos_syncro_scheduler": false,
|
|
"qos_turnaround_policy": null,
|
|
"static_backend_latency": 10000,
|
|
"static_frontend_latency": 10000,
|
|
"system": "system",
|
|
"write_high_thresh_perc": 85,
|
|
"write_low_thresh_perc": 50,
|
|
"port": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": "system.membus.mem_side_ports[0]",
|
|
"is_source": "False"
|
|
}
|
|
}
|
|
],
|
|
"membus": {
|
|
"type": "CoherentXBar",
|
|
"cxx_class": "gem5::CoherentXBar",
|
|
"name": "membus",
|
|
"path": "system.membus",
|
|
"clk_domain": "system.clk_domain",
|
|
"eventq_index": 0,
|
|
"forward_latency": 4,
|
|
"frontend_latency": 3,
|
|
"header_latency": 1,
|
|
"max_outstanding_snoops": 512,
|
|
"max_routing_table_size": 512,
|
|
"point_of_coherency": true,
|
|
"point_of_unification": true,
|
|
"power_model": [],
|
|
"power_state": {
|
|
"type": "PowerState",
|
|
"cxx_class": "gem5::PowerState",
|
|
"name": "power_state",
|
|
"path": "system.membus.power_state",
|
|
"clk_gate_bins": 20,
|
|
"clk_gate_max": 1000000000000,
|
|
"clk_gate_min": 1000,
|
|
"default_state": "UNDEFINED",
|
|
"eventq_index": 0,
|
|
"leaders": [],
|
|
"possible_states": []
|
|
},
|
|
"response_latency": 2,
|
|
"snoop_filter": {
|
|
"type": "SnoopFilter",
|
|
"cxx_class": "gem5::SnoopFilter",
|
|
"name": "snoop_filter",
|
|
"path": "system.membus.snoop_filter",
|
|
"eventq_index": 0,
|
|
"lookup_latency": 1,
|
|
"max_capacity": 8388608,
|
|
"system": "system"
|
|
},
|
|
"snoop_response_latency": 4,
|
|
"system": "system",
|
|
"use_default_range": false,
|
|
"width": 16,
|
|
"cpu_side_ports": {
|
|
"role": "GEM5 RESPONDER",
|
|
"peer": [
|
|
"system.system_port",
|
|
"system.cpu.icache_port",
|
|
"system.cpu.dcache_port",
|
|
"system.cpu.mmu.itb_walker.port",
|
|
"system.cpu.mmu.dtb_walker.port",
|
|
"system.cpu.mmu.stage2_itb_walker.port",
|
|
"system.cpu.mmu.stage2_dtb_walker.port"
|
|
],
|
|
"is_source": "False"
|
|
},
|
|
"mem_side_ports": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": [
|
|
"system.mem_ctrls.port"
|
|
],
|
|
"is_source": "True"
|
|
}
|
|
},
|
|
"voltage_domain": {
|
|
"type": "VoltageDomain",
|
|
"cxx_class": "gem5::VoltageDomain",
|
|
"name": "voltage_domain",
|
|
"path": "system.voltage_domain",
|
|
"eventq_index": 0,
|
|
"voltage": [
|
|
1.0
|
|
]
|
|
},
|
|
"system_port": {
|
|
"role": "GEM5 REQUESTOR",
|
|
"peer": "system.membus.cpu_side_ports[0]",
|
|
"is_source": "True"
|
|
}
|
|
}
|
|
} |