2428 lines
312 KiB
Plaintext
2428 lines
312 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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simSeconds 0.229172 # Number of seconds simulated (Second)
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simTicks 229172038000 # Number of ticks simulated (Tick)
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finalTick 229172038000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
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simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
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hostSeconds 623.92 # Real time elapsed on the host (Second)
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hostTickRate 367308801 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
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hostMemory 698764 # Number of bytes of host memory used (Byte)
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simInsts 39999658 # Number of instructions simulated (Count)
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simOps 55111982 # Number of ops (including micro ops) simulated (Count)
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hostInstRate 64110 # Simulator instruction rate (inst/s) ((Count/Second))
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hostOpRate 88332 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
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system.clk_domain.clock 1000 # Clock period in ticks (Tick)
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system.cpu0.numCycles 458344077 # Number of cpu cycles simulated (Cycle)
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system.cpu0.cpi 22.917204 # CPI: cycles per instruction (core level) ((Cycle/Count))
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system.cpu0.ipc 0.043635 # IPC: instructions per cycle (core level) ((Count/Cycle))
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system.cpu0.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
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system.cpu0.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
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system.cpu0.instsAdded 30460157 # Number of instructions added to the IQ (excludes non-spec) (Count)
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system.cpu0.nonSpecInstsAdded 103 # Number of non-speculative instructions added to the IQ (Count)
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system.cpu0.instsIssued 30453989 # Number of instructions issued (Count)
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system.cpu0.squashedInstsIssued 86 # Number of squashed instructions issued (Count)
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system.cpu0.squashedInstsExamined 2904031 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
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system.cpu0.squashedOperandsExamined 1083892 # Number of squashed operands that are examined and possibly removed from graph (Count)
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system.cpu0.squashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed (Count)
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system.cpu0.numIssuedDist::samples 458300589 # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::mean 0.066450 # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::stdev 0.457498 # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::0 446729677 97.48% 97.48% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::1 3246853 0.71% 98.18% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::2 1041685 0.23% 98.41% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::3 4632561 1.01% 99.42% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::4 2280893 0.50% 99.92% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::5 236045 0.05% 99.97% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::6 26400 0.01% 99.98% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::7 87914 0.02% 100.00% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::8 18561 0.00% 100.00% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
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system.cpu0.numIssuedDist::total 458300589 # Number of insts issued each cycle (Count)
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system.cpu0.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::IntAlu 24566 99.56% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::IntMult 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::IntDiv 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::FloatAdd 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::FloatCmp 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::FloatCvt 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::FloatMult 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::FloatMultAcc 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::FloatDiv 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::FloatMisc 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::FloatSqrt 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdAdd 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdAddAcc 0 0.00% 99.56% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdAlu 26 0.11% 99.66% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdCvt 1 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdMisc 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdMult 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdMultAcc 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdMatMultAcc 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdShift 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdShiftAcc 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdDiv 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdSqrt 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatAdd 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatAlu 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatCmp 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatCvt 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatDiv 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatMisc 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatMult 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatMultAcc 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatMatMultAcc 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatSqrt 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdReduceAdd 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdReduceAlu 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdReduceCmp 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatReduceAdd 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdFloatReduceCmp 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdAes 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdAesMix 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdSha1Hash 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdSha1Hash2 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdSha256Hash 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdSha256Hash2 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdShaSigma2 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdShaSigma3 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::SimdPredAlu 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::Matrix 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::MatrixMov 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::MatrixOP 0 0.00% 99.67% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::MemRead 44 0.18% 99.85% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::MemWrite 27 0.11% 99.96% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::FloatMemRead 1 0.00% 99.96% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::FloatMemWrite 10 0.04% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorIntegerArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorFloatArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorFloatConvert 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorIntegerReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorFloatReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorMisc 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorIntegerExtension 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statFuBusy::VectorConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
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system.cpu0.statIssuedInstType_0::No_OpClass 472 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::IntAlu 22182613 72.84% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::IntMult 47 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::IntDiv 83 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::FloatAdd 167 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::FloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::FloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::FloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::FloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::FloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::FloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::FloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdAdd 10 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdAddAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdAlu 305 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdCmp 4 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdCvt 84 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdMisc 257 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdShift 7 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdShiftAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdFloatAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdFloatAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdFloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdFloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdFloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdFloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdFloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
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system.cpu0.statIssuedInstType_0::SimdReduceAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
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system.cpu0.statIssuedInstType_0::SimdReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdAes 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdAesMix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdSha1Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdSha256Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdShaSigma2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdShaSigma3 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdPredAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::Matrix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::MatrixMov 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::MatrixOP 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::MemRead 2766347 9.08% 81.93% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::MemWrite 5502854 18.07% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatMemRead 164 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatMemWrite 575 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::total 30453989 # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.issueRate 0.066444 # Inst issue rate ((Count/Cycle))
|
|
system.cpu0.fuBusy 24675 # FU busy when requested (Count)
|
|
system.cpu0.fuBusyRate 0.000810 # FU busy rate (busy events/executed inst) ((Count/Count))
|
|
system.cpu0.intInstQueueReads 519229794 # Number of integer instruction queue reads (Count)
|
|
system.cpu0.intInstQueueWrites 33362216 # Number of integer instruction queue writes (Count)
|
|
system.cpu0.intInstQueueWakeupAccesses 30188667 # Number of integer instruction queue wakeup accesses (Count)
|
|
system.cpu0.fpInstQueueReads 3534 # Number of floating instruction queue reads (Count)
|
|
system.cpu0.fpInstQueueWrites 2129 # Number of floating instruction queue writes (Count)
|
|
system.cpu0.fpInstQueueWakeupAccesses 1715 # Number of floating instruction queue wakeup accesses (Count)
|
|
system.cpu0.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
|
|
system.cpu0.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
|
|
system.cpu0.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
|
|
system.cpu0.intAluAccesses 30476406 # Number of integer alu accesses (Count)
|
|
system.cpu0.fpAluAccesses 1786 # Number of floating point alu accesses (Count)
|
|
system.cpu0.vecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu0.numSquashedInsts 914 # Number of squashed instructions skipped in execute (Count)
|
|
system.cpu0.numSwp 0 # Number of swp insts executed (Count)
|
|
system.cpu0.timesIdled 366 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
|
|
system.cpu0.idleCycles 43488 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
|
|
system.cpu0.MemDepUnit__0.insertedLoads 2767100 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__0.insertedStores 5503879 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__0.conflictingLoads 1787952 # Number of conflicting loads. (Count)
|
|
system.cpu0.MemDepUnit__0.conflictingStores 230139 # Number of conflicting stores. (Count)
|
|
system.cpu0.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu0.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu0.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu0.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu0.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu0.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu0.branchPred.lookups 2864388 # Number of BP lookups (Count)
|
|
system.cpu0.branchPred.condPredicted 2853173 # Number of conditional branches predicted (Count)
|
|
system.cpu0.branchPred.condIncorrect 773 # Number of conditional branches incorrect (Count)
|
|
system.cpu0.branchPred.BTBLookups 2838747 # Number of BTB lookups (Count)
|
|
system.cpu0.branchPred.BTBUpdates 648 # Number of BTB updates (Count)
|
|
system.cpu0.branchPred.BTBHits 2838323 # Number of BTB hits (Count)
|
|
system.cpu0.branchPred.BTBHitRatio 0.999851 # BTB Hit Ratio (Ratio)
|
|
system.cpu0.branchPred.RASUsed 2584 # Number of times the RAS was used to get a target. (Count)
|
|
system.cpu0.branchPred.RASIncorrect 9 # Number of incorrect RAS predictions. (Count)
|
|
system.cpu0.branchPred.indirectLookups 2376 # Number of indirect predictor lookups. (Count)
|
|
system.cpu0.branchPred.indirectHits 2176 # Number of indirect target hits. (Count)
|
|
system.cpu0.branchPred.indirectMisses 200 # Number of indirect misses. (Count)
|
|
system.cpu0.branchPred.indirectMispredicted 63 # Number of mispredicted indirect branches. (Count)
|
|
system.cpu0.branchPred.loop_predictor.correct 2504792 # Number of times the loop predictor is the provider and the prediction is correct (Count)
|
|
system.cpu0.branchPred.loop_predictor.wrong 1865 # Number of times the loop predictor is the provider and the prediction is wrong (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProviderCorrect 1441754 # Number of times TAGE Longest Match is the provider and the prediction is correct (Count)
|
|
system.cpu0.branchPred.tage.altMatchProviderCorrect 65 # Number of times TAGE Alt Match is the provider and the prediction is correct (Count)
|
|
system.cpu0.branchPred.tage.bimodalAltMatchProviderCorrect 73 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct (Count)
|
|
system.cpu0.branchPred.tage.bimodalProviderCorrect 1064363 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProviderWrong 44 # Number of times TAGE Longest Match is the provider and the prediction is wrong (Count)
|
|
system.cpu0.branchPred.tage.altMatchProviderWrong 20 # Number of times TAGE Alt Match is the provider and the prediction is wrong (Count)
|
|
system.cpu0.branchPred.tage.bimodalAltMatchProviderWrong 32 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong (Count)
|
|
system.cpu0.branchPred.tage.bimodalProviderWrong 306 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong (Count)
|
|
system.cpu0.branchPred.tage.altMatchProviderWouldHaveHit 9 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProviderWouldHaveHit 36 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::0 0 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::1 1049656 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::2 1336 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::3 1414 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::4 387961 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::5 478 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::6 77 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::7 426 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::8 48 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::9 81 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::10 331 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::11 1 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::12 74 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::0 1052329 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::1 386809 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::2 1102 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::3 269 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::4 383 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::5 432 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::6 85 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::7 74 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::8 204 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::9 122 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::10 74 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::11 0 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::12 0 # TAGE provider for alt match (Count)
|
|
system.cpu0.commit.commitSquashedInsts 2772735 # The number of squashed insts skipped by commit (Count)
|
|
system.cpu0.commit.commitNonSpecStalls 42 # The number of times commit has been forced to stall to communicate backwards (Count)
|
|
system.cpu0.commit.branchMispredicts 540 # The number of times a branch was mispredicted (Count)
|
|
system.cpu0.commit.numCommittedDist::samples 457953585 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::mean 0.060173 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::stdev 0.438321 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::0 447661139 97.75% 97.75% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::1 3031764 0.66% 98.41% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::2 318407 0.07% 98.48% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::3 4464718 0.97% 99.46% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::4 1961193 0.43% 99.89% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::5 493421 0.11% 99.99% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::6 326 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::7 1275 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::8 21342 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::total 457953585 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.amos 0 # Number of atomic instructions committed (Count)
|
|
system.cpu0.commit.membars 28 # Number of memory barriers committed (Count)
|
|
system.cpu0.commit.functionCalls 2307 # Number of function calls committed. (Count)
|
|
system.cpu0.commit.committedInstType_0::No_OpClass 250 0.00% 0.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::IntAlu 20074104 72.85% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::IntMult 41 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::IntDiv 56 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatAdd 146 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdAdd 10 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdAlu 237 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdCmp 4 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdCvt 76 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdMisc 235 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdShift 3 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdAes 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdAesMix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::Matrix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::MatrixMov 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::MatrixOP 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::MemRead 2502668 9.08% 81.93% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::MemWrite 4977757 18.06% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatMemRead 125 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::total 27556226 # Class of committed instruction (Count)
|
|
system.cpu0.commit.commitEligibleSamples 21342 # number cycles where commit BW limit reached (Cycle)
|
|
system.cpu0.commitStats0.numInsts 20000000 # Number of instructions committed (thread level) (Count)
|
|
system.cpu0.commitStats0.numOps 27556226 # Number of ops (including micro ops) committed (thread level) (Count)
|
|
system.cpu0.commitStats0.numInstsNotNOP 20000000 # Number of instructions committed excluding NOPs or prefetches (Count)
|
|
system.cpu0.commitStats0.numOpsNotNOP 27556226 # Number of Ops (including micro ops) Simulated (Count)
|
|
system.cpu0.commitStats0.cpi 22.917204 # CPI: cycles per instruction (thread level) ((Cycle/Count))
|
|
system.cpu0.commitStats0.ipc 0.043635 # IPC: instructions per cycle (thread level) ((Count/Cycle))
|
|
system.cpu0.commitStats0.numMemRefs 7481064 # Number of memory references committed (Count)
|
|
system.cpu0.commitStats0.numFpInsts 1513 # Number of float instructions (Count)
|
|
system.cpu0.commitStats0.numIntInsts 27555088 # Number of integer instructions (Count)
|
|
system.cpu0.commitStats0.numLoadInsts 2502793 # Number of load instructions (Count)
|
|
system.cpu0.commitStats0.numStoreInsts 4978271 # Number of store instructions (Count)
|
|
system.cpu0.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
|
|
system.cpu0.commitStats0.committedInstType::No_OpClass 250 0.00% 0.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::IntAlu 20074104 72.85% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::IntMult 41 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::IntDiv 56 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatAdd 146 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdAdd 10 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdAlu 237 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdCmp 4 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdCvt 76 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdMisc 235 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdShift 3 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdAes 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::Matrix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::MatrixMov 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::MatrixOP 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::MemRead 2502668 9.08% 81.93% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::MemWrite 4977757 18.06% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatMemRead 125 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::total 27556226 # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedControl::IsControl 2516676 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsDirectControl 2512216 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsIndirectControl 4460 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsCondControl 2506658 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsUncondControl 10018 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsCall 2307 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsReturn 2304 # Class of control type instructions committed (Count)
|
|
system.cpu0.dcache.demandHits::cpu0.data 2508114 # number of demand (read+write) hits (Count)
|
|
system.cpu0.dcache.demandHits::total 2508114 # number of demand (read+write) hits (Count)
|
|
system.cpu0.dcache.overallHits::cpu0.data 2508114 # number of overall hits (Count)
|
|
system.cpu0.dcache.overallHits::total 2508114 # number of overall hits (Count)
|
|
system.cpu0.dcache.demandMisses::cpu0.data 2485885 # number of demand (read+write) misses (Count)
|
|
system.cpu0.dcache.demandMisses::total 2485885 # number of demand (read+write) misses (Count)
|
|
system.cpu0.dcache.overallMisses::cpu0.data 2485885 # number of overall misses (Count)
|
|
system.cpu0.dcache.overallMisses::total 2485885 # number of overall misses (Count)
|
|
system.cpu0.dcache.demandMissLatency::cpu0.data 226369192500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu0.dcache.demandMissLatency::total 226369192500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu0.dcache.overallMissLatency::cpu0.data 226369192500 # number of overall miss ticks (Tick)
|
|
system.cpu0.dcache.overallMissLatency::total 226369192500 # number of overall miss ticks (Tick)
|
|
system.cpu0.dcache.demandAccesses::cpu0.data 4993999 # number of demand (read+write) accesses (Count)
|
|
system.cpu0.dcache.demandAccesses::total 4993999 # number of demand (read+write) accesses (Count)
|
|
system.cpu0.dcache.overallAccesses::cpu0.data 4993999 # number of overall (read+write) accesses (Count)
|
|
system.cpu0.dcache.overallAccesses::total 4993999 # number of overall (read+write) accesses (Count)
|
|
system.cpu0.dcache.demandMissRate::cpu0.data 0.497774 # miss rate for demand accesses (Ratio)
|
|
system.cpu0.dcache.demandMissRate::total 0.497774 # miss rate for demand accesses (Ratio)
|
|
system.cpu0.dcache.overallMissRate::cpu0.data 0.497774 # miss rate for overall accesses (Ratio)
|
|
system.cpu0.dcache.overallMissRate::total 0.497774 # miss rate for overall accesses (Ratio)
|
|
system.cpu0.dcache.demandAvgMissLatency::cpu0.data 91061.811990 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu0.dcache.demandAvgMissLatency::total 91061.811990 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu0.dcache.overallAvgMissLatency::cpu0.data 91061.811990 # average overall miss latency ((Tick/Count))
|
|
system.cpu0.dcache.overallAvgMissLatency::total 91061.811990 # average overall miss latency ((Tick/Count))
|
|
system.cpu0.dcache.blockedCycles::no_mshrs 511 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.dcache.blockedCauses::no_mshrs 10 # number of times access was blocked (Count)
|
|
system.cpu0.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu0.dcache.avgBlocked::no_mshrs 51.100000 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.dcache.writebacks::writebacks 2483880 # number of writebacks (Count)
|
|
system.cpu0.dcache.writebacks::total 2483880 # number of writebacks (Count)
|
|
system.cpu0.dcache.demandMshrHits::cpu0.data 1040 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu0.dcache.demandMshrHits::total 1040 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu0.dcache.overallMshrHits::cpu0.data 1040 # number of overall MSHR hits (Count)
|
|
system.cpu0.dcache.overallMshrHits::total 1040 # number of overall MSHR hits (Count)
|
|
system.cpu0.dcache.demandMshrMisses::cpu0.data 2484845 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu0.dcache.demandMshrMisses::total 2484845 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu0.dcache.overallMshrMisses::cpu0.data 2484845 # number of overall MSHR misses (Count)
|
|
system.cpu0.dcache.overallMshrMisses::total 2484845 # number of overall MSHR misses (Count)
|
|
system.cpu0.dcache.demandMshrMissLatency::cpu0.data 223804443000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.demandMshrMissLatency::total 223804443000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.overallMshrMissLatency::cpu0.data 223804443000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.overallMshrMissLatency::total 223804443000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.demandMshrMissRate::cpu0.data 0.497566 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu0.dcache.demandMshrMissRate::total 0.497566 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu0.dcache.overallMshrMissRate::cpu0.data 0.497566 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu0.dcache.overallMshrMissRate::total 0.497566 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu0.dcache.demandAvgMshrMissLatency::cpu0.data 90067.768010 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.demandAvgMshrMissLatency::total 90067.768010 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.overallAvgMshrMissLatency::cpu0.data 90067.768010 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.overallAvgMshrMissLatency::total 90067.768010 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.replacements 2484331 # number of replacements (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.hits::cpu0.data 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.hits::total 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.misses::cpu0.data 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.misses::total 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.missLatency::cpu0.data 96500 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu0.dcache.LockedRMWReadReq.missLatency::total 96500 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu0.dcache.LockedRMWReadReq.accesses::cpu0.data 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.accesses::total 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.missRate::cpu0.data 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu0.dcache.LockedRMWReadReq.missRate::total 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu0.dcache.LockedRMWReadReq.avgMissLatency::cpu0.data 96500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.LockedRMWReadReq.avgMissLatency::total 96500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMisses::cpu0.data 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMisses::total 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMissLatency::cpu0.data 244000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMissLatency::total 244000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMissRate::cpu0.data 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMissRate::total 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu0.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu0.data 244000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.LockedRMWReadReq.avgMshrMissLatency::total 244000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.LockedRMWWriteReq.hits::cpu0.data 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu0.dcache.LockedRMWWriteReq.hits::total 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu0.dcache.LockedRMWWriteReq.accesses::cpu0.data 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.LockedRMWWriteReq.accesses::total 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.ReadReq.hits::cpu0.data 13986 # number of ReadReq hits (Count)
|
|
system.cpu0.dcache.ReadReq.hits::total 13986 # number of ReadReq hits (Count)
|
|
system.cpu0.dcache.ReadReq.misses::cpu0.data 1787 # number of ReadReq misses (Count)
|
|
system.cpu0.dcache.ReadReq.misses::total 1787 # number of ReadReq misses (Count)
|
|
system.cpu0.dcache.ReadReq.missLatency::cpu0.data 138277000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu0.dcache.ReadReq.missLatency::total 138277000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu0.dcache.ReadReq.accesses::cpu0.data 15773 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.ReadReq.accesses::total 15773 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.ReadReq.missRate::cpu0.data 0.113295 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.dcache.ReadReq.missRate::total 0.113295 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.dcache.ReadReq.avgMissLatency::cpu0.data 77379.406827 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.ReadReq.avgMissLatency::total 77379.406827 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.ReadReq.mshrHits::cpu0.data 1040 # number of ReadReq MSHR hits (Count)
|
|
system.cpu0.dcache.ReadReq.mshrHits::total 1040 # number of ReadReq MSHR hits (Count)
|
|
system.cpu0.dcache.ReadReq.mshrMisses::cpu0.data 747 # number of ReadReq MSHR misses (Count)
|
|
system.cpu0.dcache.ReadReq.mshrMisses::total 747 # number of ReadReq MSHR misses (Count)
|
|
system.cpu0.dcache.ReadReq.mshrMissLatency::cpu0.data 57624500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.ReadReq.mshrMissLatency::total 57624500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.ReadReq.mshrMissRate::cpu0.data 0.047359 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.dcache.ReadReq.mshrMissRate::total 0.047359 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.dcache.ReadReq.avgMshrMissLatency::cpu0.data 77141.231593 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.ReadReq.avgMshrMissLatency::total 77141.231593 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.WriteReq.hits::cpu0.data 2494128 # number of WriteReq hits (Count)
|
|
system.cpu0.dcache.WriteReq.hits::total 2494128 # number of WriteReq hits (Count)
|
|
system.cpu0.dcache.WriteReq.misses::cpu0.data 2484098 # number of WriteReq misses (Count)
|
|
system.cpu0.dcache.WriteReq.misses::total 2484098 # number of WriteReq misses (Count)
|
|
system.cpu0.dcache.WriteReq.missLatency::cpu0.data 226230915500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu0.dcache.WriteReq.missLatency::total 226230915500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu0.dcache.WriteReq.accesses::cpu0.data 4978226 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.WriteReq.accesses::total 4978226 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.WriteReq.missRate::cpu0.data 0.498993 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu0.dcache.WriteReq.missRate::total 0.498993 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu0.dcache.WriteReq.avgMissLatency::cpu0.data 91071.654782 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.WriteReq.avgMissLatency::total 91071.654782 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.WriteReq.mshrMisses::cpu0.data 2484098 # number of WriteReq MSHR misses (Count)
|
|
system.cpu0.dcache.WriteReq.mshrMisses::total 2484098 # number of WriteReq MSHR misses (Count)
|
|
system.cpu0.dcache.WriteReq.mshrMissLatency::cpu0.data 223746818500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.WriteReq.mshrMissLatency::total 223746818500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.WriteReq.mshrMissRate::cpu0.data 0.498993 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu0.dcache.WriteReq.mshrMissRate::total 0.498993 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu0.dcache.WriteReq.avgMshrMissLatency::cpu0.data 90071.655184 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.WriteReq.avgMshrMissLatency::total 90071.655184 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.dcache.tags.tagsInUse 511.913844 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu0.dcache.tags.totalRefs 4992986 # Total number of references to valid blocks. (Count)
|
|
system.cpu0.dcache.tags.sampledRefs 2484843 # Sample count of references to valid blocks. (Count)
|
|
system.cpu0.dcache.tags.avgRefs 2.009377 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu0.dcache.tags.warmupTick 176500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu0.dcache.tags.occupancies::cpu0.data 511.913844 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu0.dcache.tags.avgOccs::cpu0.data 0.999832 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu0.dcache.tags.avgOccs::total 0.999832 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu0.dcache.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
|
|
system.cpu0.dcache.tags.ageTaskId_1024::0 110 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu0.dcache.tags.ageTaskId_1024::1 145 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu0.dcache.tags.ageTaskId_1024::4 257 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu0.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu0.dcache.tags.tagAccesses 12472897 # Number of tag accesses (Count)
|
|
system.cpu0.dcache.tags.dataAccesses 12472897 # Number of data accesses (Count)
|
|
system.cpu0.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.decode.idleCycles 1293383 # Number of cycles decode is idle (Cycle)
|
|
system.cpu0.decode.blockedCycles 453046177 # Number of cycles decode is blocked (Cycle)
|
|
system.cpu0.decode.runCycles 505922 # Number of cycles decode is running (Cycle)
|
|
system.cpu0.decode.unblockCycles 3438111 # Number of cycles decode is unblocking (Cycle)
|
|
system.cpu0.decode.squashCycles 16996 # Number of cycles decode is squashing (Cycle)
|
|
system.cpu0.decode.branchResolved 2772786 # Number of times decode resolved a branch (Count)
|
|
system.cpu0.decode.branchMispred 271 # Number of times decode detected a branch misprediction (Count)
|
|
system.cpu0.decode.decodedInsts 30644687 # Number of instructions handled by decode (Count)
|
|
system.cpu0.decode.squashedInsts 1191 # Number of squashed instructions handled by decode (Count)
|
|
system.cpu0.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu0.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu0.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.dtb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu0.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu0.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu0.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu0.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu0.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu0.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu0.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu0.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.executeStats0.numInsts 30453075 # Number of executed instructions (Count)
|
|
system.cpu0.executeStats0.numNop 0 # Number of nop insts executed (Count)
|
|
system.cpu0.executeStats0.numBranches 2779826 # Number of branches executed (Count)
|
|
system.cpu0.executeStats0.numLoadInsts 2766326 # Number of load instructions executed (Count)
|
|
system.cpu0.executeStats0.numStoreInsts 5503345 # Number of stores executed (Count)
|
|
system.cpu0.executeStats0.instRate 0.066442 # Inst execution rate ((Count/Cycle))
|
|
system.cpu0.executeStats0.numCCRegReads 13888044 # Number of times the CC registers were read (Count)
|
|
system.cpu0.executeStats0.numCCRegWrites 16559341 # Number of times the CC registers were written (Count)
|
|
system.cpu0.executeStats0.numFpRegReads 2113 # Number of times the floating registers were read (Count)
|
|
system.cpu0.executeStats0.numFpRegWrites 1079 # Number of times the floating registers were written (Count)
|
|
system.cpu0.executeStats0.numIntRegReads 49749886 # Number of times the integer registers were read (Count)
|
|
system.cpu0.executeStats0.numIntRegWrites 19397931 # Number of times the integer registers were written (Count)
|
|
system.cpu0.executeStats0.numMemRefs 8269671 # Number of memory refs (Count)
|
|
system.cpu0.executeStats0.numMiscRegReads 13828609 # Number of times the Misc registers were read (Count)
|
|
system.cpu0.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu0.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
|
|
system.cpu0.fetch.predictedBranches 2843083 # Number of branches that fetch has predicted taken (Count)
|
|
system.cpu0.fetch.cycles 458242381 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
|
|
system.cpu0.fetch.squashCycles 34526 # Number of cycles fetch has spent squashing (Cycle)
|
|
system.cpu0.fetch.miscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
|
|
system.cpu0.fetch.pendingTrapStallCycles 216 # Number of stall cycles due to pending traps (Cycle)
|
|
system.cpu0.fetch.cacheLines 19514 # Number of cache lines fetched (Count)
|
|
system.cpu0.fetch.icacheSquashes 418 # Number of outstanding Icache misses that were squashed (Count)
|
|
system.cpu0.fetch.nisnDist::samples 458300589 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::mean 0.068597 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::stdev 0.657274 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::0 451949138 98.61% 98.61% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::1 655794 0.14% 98.76% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::2 655114 0.14% 98.90% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::3 1537999 0.34% 99.24% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::4 316753 0.07% 99.30% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::5 311855 0.07% 99.37% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::6 313980 0.07% 99.44% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::7 331788 0.07% 99.51% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::8 2228168 0.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::total 458300589 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetchStats0.numInsts 22835139 # Number of instructions fetched (thread level) (Count)
|
|
system.cpu0.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
|
|
system.cpu0.fetchStats0.fetchRate 0.049821 # Number of inst fetches per cycle ((Count/Cycle))
|
|
system.cpu0.fetchStats0.numBranches 2864388 # Number of branches fetched (Count)
|
|
system.cpu0.fetchStats0.branchRate 0.006249 # Number of branch fetches per cycle (Ratio)
|
|
system.cpu0.fetchStats0.icacheStallCycles 40690 # ICache total stall cycles (Cycle)
|
|
system.cpu0.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
|
|
system.cpu0.icache.demandHits::cpu0.inst 18762 # number of demand (read+write) hits (Count)
|
|
system.cpu0.icache.demandHits::total 18762 # number of demand (read+write) hits (Count)
|
|
system.cpu0.icache.overallHits::cpu0.inst 18762 # number of overall hits (Count)
|
|
system.cpu0.icache.overallHits::total 18762 # number of overall hits (Count)
|
|
system.cpu0.icache.demandMisses::cpu0.inst 752 # number of demand (read+write) misses (Count)
|
|
system.cpu0.icache.demandMisses::total 752 # number of demand (read+write) misses (Count)
|
|
system.cpu0.icache.overallMisses::cpu0.inst 752 # number of overall misses (Count)
|
|
system.cpu0.icache.overallMisses::total 752 # number of overall misses (Count)
|
|
system.cpu0.icache.demandMissLatency::cpu0.inst 58166500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu0.icache.demandMissLatency::total 58166500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu0.icache.overallMissLatency::cpu0.inst 58166500 # number of overall miss ticks (Tick)
|
|
system.cpu0.icache.overallMissLatency::total 58166500 # number of overall miss ticks (Tick)
|
|
system.cpu0.icache.demandAccesses::cpu0.inst 19514 # number of demand (read+write) accesses (Count)
|
|
system.cpu0.icache.demandAccesses::total 19514 # number of demand (read+write) accesses (Count)
|
|
system.cpu0.icache.overallAccesses::cpu0.inst 19514 # number of overall (read+write) accesses (Count)
|
|
system.cpu0.icache.overallAccesses::total 19514 # number of overall (read+write) accesses (Count)
|
|
system.cpu0.icache.demandMissRate::cpu0.inst 0.038536 # miss rate for demand accesses (Ratio)
|
|
system.cpu0.icache.demandMissRate::total 0.038536 # miss rate for demand accesses (Ratio)
|
|
system.cpu0.icache.overallMissRate::cpu0.inst 0.038536 # miss rate for overall accesses (Ratio)
|
|
system.cpu0.icache.overallMissRate::total 0.038536 # miss rate for overall accesses (Ratio)
|
|
system.cpu0.icache.demandAvgMissLatency::cpu0.inst 77349.069149 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu0.icache.demandAvgMissLatency::total 77349.069149 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu0.icache.overallAvgMissLatency::cpu0.inst 77349.069149 # average overall miss latency ((Tick/Count))
|
|
system.cpu0.icache.overallAvgMissLatency::total 77349.069149 # average overall miss latency ((Tick/Count))
|
|
system.cpu0.icache.blockedCycles::no_mshrs 285 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.icache.blockedCauses::no_mshrs 5 # number of times access was blocked (Count)
|
|
system.cpu0.icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu0.icache.avgBlocked::no_mshrs 57 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.icache.writebacks::writebacks 170 # number of writebacks (Count)
|
|
system.cpu0.icache.writebacks::total 170 # number of writebacks (Count)
|
|
system.cpu0.icache.demandMshrHits::cpu0.inst 173 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu0.icache.demandMshrHits::total 173 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu0.icache.overallMshrHits::cpu0.inst 173 # number of overall MSHR hits (Count)
|
|
system.cpu0.icache.overallMshrHits::total 173 # number of overall MSHR hits (Count)
|
|
system.cpu0.icache.demandMshrMisses::cpu0.inst 579 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu0.icache.demandMshrMisses::total 579 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu0.icache.overallMshrMisses::cpu0.inst 579 # number of overall MSHR misses (Count)
|
|
system.cpu0.icache.overallMshrMisses::total 579 # number of overall MSHR misses (Count)
|
|
system.cpu0.icache.demandMshrMissLatency::cpu0.inst 47739000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu0.icache.demandMshrMissLatency::total 47739000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu0.icache.overallMshrMissLatency::cpu0.inst 47739000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu0.icache.overallMshrMissLatency::total 47739000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu0.icache.demandMshrMissRate::cpu0.inst 0.029671 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu0.icache.demandMshrMissRate::total 0.029671 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu0.icache.overallMshrMissRate::cpu0.inst 0.029671 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu0.icache.overallMshrMissRate::total 0.029671 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu0.icache.demandAvgMshrMissLatency::cpu0.inst 82450.777202 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.demandAvgMshrMissLatency::total 82450.777202 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.overallAvgMshrMissLatency::cpu0.inst 82450.777202 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.overallAvgMshrMissLatency::total 82450.777202 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.replacements 170 # number of replacements (Count)
|
|
system.cpu0.icache.ReadReq.hits::cpu0.inst 18762 # number of ReadReq hits (Count)
|
|
system.cpu0.icache.ReadReq.hits::total 18762 # number of ReadReq hits (Count)
|
|
system.cpu0.icache.ReadReq.misses::cpu0.inst 752 # number of ReadReq misses (Count)
|
|
system.cpu0.icache.ReadReq.misses::total 752 # number of ReadReq misses (Count)
|
|
system.cpu0.icache.ReadReq.missLatency::cpu0.inst 58166500 # number of ReadReq miss ticks (Tick)
|
|
system.cpu0.icache.ReadReq.missLatency::total 58166500 # number of ReadReq miss ticks (Tick)
|
|
system.cpu0.icache.ReadReq.accesses::cpu0.inst 19514 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.icache.ReadReq.accesses::total 19514 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.icache.ReadReq.missRate::cpu0.inst 0.038536 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.icache.ReadReq.missRate::total 0.038536 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.icache.ReadReq.avgMissLatency::cpu0.inst 77349.069149 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu0.icache.ReadReq.avgMissLatency::total 77349.069149 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu0.icache.ReadReq.mshrHits::cpu0.inst 173 # number of ReadReq MSHR hits (Count)
|
|
system.cpu0.icache.ReadReq.mshrHits::total 173 # number of ReadReq MSHR hits (Count)
|
|
system.cpu0.icache.ReadReq.mshrMisses::cpu0.inst 579 # number of ReadReq MSHR misses (Count)
|
|
system.cpu0.icache.ReadReq.mshrMisses::total 579 # number of ReadReq MSHR misses (Count)
|
|
system.cpu0.icache.ReadReq.mshrMissLatency::cpu0.inst 47739000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.icache.ReadReq.mshrMissLatency::total 47739000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.icache.ReadReq.mshrMissRate::cpu0.inst 0.029671 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.icache.ReadReq.mshrMissRate::total 0.029671 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.icache.ReadReq.avgMshrMissLatency::cpu0.inst 82450.777202 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.ReadReq.avgMshrMissLatency::total 82450.777202 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.icache.tags.tagsInUse 406.961669 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu0.icache.tags.totalRefs 19341 # Total number of references to valid blocks. (Count)
|
|
system.cpu0.icache.tags.sampledRefs 579 # Sample count of references to valid blocks. (Count)
|
|
system.cpu0.icache.tags.avgRefs 33.404145 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu0.icache.tags.warmupTick 87500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu0.icache.tags.occupancies::cpu0.inst 406.961669 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu0.icache.tags.avgOccs::cpu0.inst 0.794847 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu0.icache.tags.avgOccs::total 0.794847 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu0.icache.tags.occupanciesTaskId::1024 407 # Occupied blocks per task id (Count)
|
|
system.cpu0.icache.tags.ageTaskId_1024::4 407 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu0.icache.tags.ratioOccsTaskId::1024 0.794922 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu0.icache.tags.tagAccesses 39607 # Number of tag accesses (Count)
|
|
system.cpu0.icache.tags.dataAccesses 39607 # Number of data accesses (Count)
|
|
system.cpu0.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
|
|
system.cpu0.iew.squashCycles 16996 # Number of cycles IEW is squashing (Cycle)
|
|
system.cpu0.iew.blockCycles 400907 # Number of cycles IEW is blocking (Cycle)
|
|
system.cpu0.iew.unblockCycles 257387342 # Number of cycles IEW is unblocking (Cycle)
|
|
system.cpu0.iew.dispatchedInsts 30460260 # Number of instructions dispatched to IQ (Count)
|
|
system.cpu0.iew.dispSquashedInsts 67 # Number of squashed instructions skipped by dispatch (Count)
|
|
system.cpu0.iew.dispLoadInsts 2767100 # Number of dispatched load instructions (Count)
|
|
system.cpu0.iew.dispStoreInsts 5503879 # Number of dispatched store instructions (Count)
|
|
system.cpu0.iew.dispNonSpecInsts 35 # Number of dispatched non-speculative instructions (Count)
|
|
system.cpu0.iew.iqFullEvents 1627 # Number of times the IQ has become full, causing a stall (Count)
|
|
system.cpu0.iew.lsqFullEvents 257402097 # Number of times the LSQ has become full, causing a stall (Count)
|
|
system.cpu0.iew.memOrderViolationEvents 57 # Number of memory order violations (Count)
|
|
system.cpu0.iew.predictedTakenIncorrect 73 # Number of branches that were predicted taken incorrectly (Count)
|
|
system.cpu0.iew.predictedNotTakenIncorrect 536 # Number of branches that were predicted not taken incorrectly (Count)
|
|
system.cpu0.iew.branchMispredicts 609 # Number of branch mispredicts detected at execute (Count)
|
|
system.cpu0.iew.instsToCommit 30452796 # Cumulative count of insts sent to commit (Count)
|
|
system.cpu0.iew.writebackCount 30190382 # Cumulative count of insts written-back (Count)
|
|
system.cpu0.iew.producerInst 12047103 # Number of instructions producing a value (Count)
|
|
system.cpu0.iew.consumerInst 19244507 # Number of instructions consuming a value (Count)
|
|
system.cpu0.iew.wbRate 0.065868 # Insts written-back per cycle ((Count/Cycle))
|
|
system.cpu0.iew.wbFanout 0.626002 # Average fanout of values written-back ((Count/Count))
|
|
system.cpu0.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
|
|
system.cpu0.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu0.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu0.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.itb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu0.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu0.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu0.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu0.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu0.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu0.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu0.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu0.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.lsq0.forwLoads 2750452 # Number of loads that had data forwarded from stores (Count)
|
|
system.cpu0.lsq0.squashedLoads 264306 # Number of loads squashed (Count)
|
|
system.cpu0.lsq0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed (Count)
|
|
system.cpu0.lsq0.memOrderViolation 57 # Number of memory ordering violations (Count)
|
|
system.cpu0.lsq0.squashedStores 525608 # Number of stores squashed (Count)
|
|
system.cpu0.lsq0.rescheduledLoads 1 # Number of loads that were rescheduled (Count)
|
|
system.cpu0.lsq0.blockedByCache 9 # Number of times an access to memory failed due to the cache being blocked (Count)
|
|
system.cpu0.lsq0.loadToUse::samples 2502793 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::mean 2.106666 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::stdev 4.211826 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::0-9 2501138 99.93% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::10-19 4 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::20-29 15 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::30-39 9 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::40-49 1 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::50-59 2 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::100-109 1 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::110-119 4 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::120-129 23 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::130-139 40 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::140-149 1252 0.05% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::150-159 92 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::160-169 36 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::170-179 84 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::180-189 7 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::190-199 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::200-209 38 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::210-219 12 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::220-229 6 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::240-249 4 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::260-269 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::overflows 22 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::max_value 779 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::total 2502793 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.mmu.dtb.rdAccesses 2766312 # TLB accesses on read requests (Count)
|
|
system.cpu0.mmu.dtb.wrAccesses 5503345 # TLB accesses on write requests (Count)
|
|
system.cpu0.mmu.dtb.rdMisses 93 # TLB misses on read requests (Count)
|
|
system.cpu0.mmu.dtb.wrMisses 300974 # TLB misses on write requests (Count)
|
|
system.cpu0.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
|
|
system.cpu0.mmu.itb.wrAccesses 19553 # TLB accesses on write requests (Count)
|
|
system.cpu0.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
|
|
system.cpu0.mmu.itb.wrMisses 82 # TLB misses on write requests (Count)
|
|
system.cpu0.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.power_state.pwrStateResidencyTicks::ON 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.rename.squashCycles 16996 # Number of cycles rename is squashing (Cycle)
|
|
system.cpu0.rename.idleCycles 2276441 # Number of cycles rename is idle (Cycle)
|
|
system.cpu0.rename.blockCycles 257792091 # Number of cycles rename is blocking (Cycle)
|
|
system.cpu0.rename.serializeStallCycles 1089 # count of cycles rename stalled for serializing inst (Cycle)
|
|
system.cpu0.rename.runCycles 2944231 # Number of cycles rename is running (Cycle)
|
|
system.cpu0.rename.unblockCycles 195269741 # Number of cycles rename is unblocking (Cycle)
|
|
system.cpu0.rename.renamedInsts 30511991 # Number of instructions processed by rename (Count)
|
|
system.cpu0.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full (Count)
|
|
system.cpu0.rename.IQFullEvents 10639 # Number of times rename has blocked due to IQ full (Count)
|
|
system.cpu0.rename.SQFullEvents 194569910 # Number of times rename has blocked due to SQ full (Count)
|
|
system.cpu0.rename.renamedOperands 63785271 # Number of destination operands rename has renamed (Count)
|
|
system.cpu0.rename.lookups 124730686 # Number of register rename lookups that rename has made (Count)
|
|
system.cpu0.rename.intLookups 49881072 # Number of integer rename lookups (Count)
|
|
system.cpu0.rename.fpLookups 2296 # Number of floating rename lookups (Count)
|
|
system.cpu0.rename.committedMaps 57521754 # Number of HB maps that are committed (Count)
|
|
system.cpu0.rename.undoneMaps 6263502 # Number of HB maps that are undone due to squashing (Count)
|
|
system.cpu0.rename.serializing 45 # count of serializing insts renamed (Count)
|
|
system.cpu0.rename.tempSerializing 45 # count of temporary serializing insts renamed (Count)
|
|
system.cpu0.rename.skidInsts 18601704 # count of insts added to the skid buffer (Count)
|
|
system.cpu0.rob.reads 488047978 # The number of ROB reads (Count)
|
|
system.cpu0.rob.writes 61004944 # The number of ROB writes (Count)
|
|
system.cpu0.thread_0.numInsts 20000000 # Number of Instructions committed (Count)
|
|
system.cpu0.thread_0.numOps 27556226 # Number of Ops committed (Count)
|
|
system.cpu0.thread_0.numMemRefs 0 # Number of Memory References (Count)
|
|
system.cpu0.workload.numSyscalls 14 # Number of system calls (Count)
|
|
system.cpu1.numCycles 458344077 # Number of cpu cycles simulated (Cycle)
|
|
system.cpu1.cpi 22.917596 # CPI: cycles per instruction (core level) ((Cycle/Count))
|
|
system.cpu1.ipc 0.043635 # IPC: instructions per cycle (core level) ((Count/Cycle))
|
|
system.cpu1.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
|
|
system.cpu1.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
|
|
system.cpu1.instsAdded 30459800 # Number of instructions added to the IQ (excludes non-spec) (Count)
|
|
system.cpu1.nonSpecInstsAdded 103 # Number of non-speculative instructions added to the IQ (Count)
|
|
system.cpu1.instsIssued 30453688 # Number of instructions issued (Count)
|
|
system.cpu1.squashedInstsIssued 92 # Number of squashed instructions issued (Count)
|
|
system.cpu1.squashedInstsExamined 2904147 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
|
|
system.cpu1.squashedOperandsExamined 1083611 # Number of squashed operands that are examined and possibly removed from graph (Count)
|
|
system.cpu1.squashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed (Count)
|
|
system.cpu1.numIssuedDist::samples 458299757 # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::mean 0.066449 # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::stdev 0.457499 # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::0 446729027 97.48% 97.48% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::1 3246793 0.71% 98.18% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::2 1041645 0.23% 98.41% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::3 4632488 1.01% 99.42% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::4 2280876 0.50% 99.92% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::5 236010 0.05% 99.97% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::6 26420 0.01% 99.98% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::7 87917 0.02% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::8 18581 0.00% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::total 458299757 # Number of insts issued each cycle (Count)
|
|
system.cpu1.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::IntAlu 24564 99.55% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::IntMult 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::IntDiv 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatAdd 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatCmp 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatCvt 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatMult 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatMultAcc 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatDiv 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatMisc 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatSqrt 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdAdd 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdAddAcc 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdAlu 26 0.11% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdCvt 1 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdMisc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdMult 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdMatMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdShift 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdShiftAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdDiv 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdSqrt 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatAdd 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatAlu 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatCvt 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatDiv 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatMisc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatMult 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatMatMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatSqrt 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdReduceAdd 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdReduceAlu 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdReduceCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatReduceAdd 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatReduceCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdAes 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdAesMix 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdSha1Hash 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdSha1Hash2 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdSha256Hash 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdSha256Hash2 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdShaSigma2 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdShaSigma3 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdPredAlu 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::Matrix 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::MatrixMov 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::MatrixOP 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::MemRead 47 0.19% 99.85% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::MemWrite 27 0.11% 99.96% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatMemRead 1 0.00% 99.97% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatMemWrite 8 0.03% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorIntegerArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorFloatArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorFloatConvert 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorIntegerReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorFloatReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorMisc 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorIntegerExtension 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statIssuedInstType_0::No_OpClass 467 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::IntAlu 22182371 72.84% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::IntMult 46 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::IntDiv 83 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatAdd 168 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdAdd 10 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdAddAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdAlu 319 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdCmp 4 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdCvt 84 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdMisc 257 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdShift 7 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdShiftAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdReduceAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdAes 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdAesMix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdSha1Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdSha256Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdShaSigma2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdShaSigma3 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdPredAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::Matrix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::MatrixMov 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::MatrixOP 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::MemRead 2766319 9.08% 81.93% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::MemWrite 5502804 18.07% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatMemRead 167 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatMemWrite 582 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::total 30453688 # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.issueRate 0.066443 # Inst issue rate ((Count/Cycle))
|
|
system.cpu1.fuBusy 24674 # FU busy when requested (Count)
|
|
system.cpu1.fuBusyRate 0.000810 # FU busy rate (busy events/executed inst) ((Count/Count))
|
|
system.cpu1.intInstQueueReads 519228317 # Number of integer instruction queue reads (Count)
|
|
system.cpu1.intInstQueueWrites 33361926 # Number of integer instruction queue writes (Count)
|
|
system.cpu1.intInstQueueWakeupAccesses 30188311 # Number of integer instruction queue wakeup accesses (Count)
|
|
system.cpu1.fpInstQueueReads 3582 # Number of floating instruction queue reads (Count)
|
|
system.cpu1.fpInstQueueWrites 2183 # Number of floating instruction queue writes (Count)
|
|
system.cpu1.fpInstQueueWakeupAccesses 1736 # Number of floating instruction queue wakeup accesses (Count)
|
|
system.cpu1.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
|
|
system.cpu1.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
|
|
system.cpu1.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
|
|
system.cpu1.intAluAccesses 30476086 # Number of integer alu accesses (Count)
|
|
system.cpu1.fpAluAccesses 1809 # Number of floating point alu accesses (Count)
|
|
system.cpu1.vecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu1.numSquashedInsts 946 # Number of squashed instructions skipped in execute (Count)
|
|
system.cpu1.numSwp 0 # Number of swp insts executed (Count)
|
|
system.cpu1.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
|
|
system.cpu1.idleCycles 44320 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
|
|
system.cpu1.MemDepUnit__0.insertedLoads 2767078 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__0.insertedStores 5503853 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__0.conflictingLoads 1787944 # Number of conflicting loads. (Count)
|
|
system.cpu1.MemDepUnit__0.conflictingStores 230132 # Number of conflicting stores. (Count)
|
|
system.cpu1.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu1.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu1.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu1.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu1.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu1.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu1.branchPred.lookups 2864347 # Number of BP lookups (Count)
|
|
system.cpu1.branchPred.condPredicted 2853137 # Number of conditional branches predicted (Count)
|
|
system.cpu1.branchPred.condIncorrect 775 # Number of conditional branches incorrect (Count)
|
|
system.cpu1.branchPred.BTBLookups 2838689 # Number of BTB lookups (Count)
|
|
system.cpu1.branchPred.BTBUpdates 649 # Number of BTB updates (Count)
|
|
system.cpu1.branchPred.BTBHits 2838266 # Number of BTB hits (Count)
|
|
system.cpu1.branchPred.BTBHitRatio 0.999851 # BTB Hit Ratio (Ratio)
|
|
system.cpu1.branchPred.RASUsed 2577 # Number of times the RAS was used to get a target. (Count)
|
|
system.cpu1.branchPred.RASIncorrect 9 # Number of incorrect RAS predictions. (Count)
|
|
system.cpu1.branchPred.indirectLookups 2378 # Number of indirect predictor lookups. (Count)
|
|
system.cpu1.branchPred.indirectHits 2177 # Number of indirect target hits. (Count)
|
|
system.cpu1.branchPred.indirectMisses 201 # Number of indirect misses. (Count)
|
|
system.cpu1.branchPred.indirectMispredicted 63 # Number of mispredicted indirect branches. (Count)
|
|
system.cpu1.branchPred.loop_predictor.correct 2504751 # Number of times the loop predictor is the provider and the prediction is correct (Count)
|
|
system.cpu1.branchPred.loop_predictor.wrong 1864 # Number of times the loop predictor is the provider and the prediction is wrong (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProviderCorrect 1441725 # Number of times TAGE Longest Match is the provider and the prediction is correct (Count)
|
|
system.cpu1.branchPred.tage.altMatchProviderCorrect 56 # Number of times TAGE Alt Match is the provider and the prediction is correct (Count)
|
|
system.cpu1.branchPred.tage.bimodalAltMatchProviderCorrect 80 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct (Count)
|
|
system.cpu1.branchPred.tage.bimodalProviderCorrect 1064353 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProviderWrong 50 # Number of times TAGE Longest Match is the provider and the prediction is wrong (Count)
|
|
system.cpu1.branchPred.tage.altMatchProviderWrong 17 # Number of times TAGE Alt Match is the provider and the prediction is wrong (Count)
|
|
system.cpu1.branchPred.tage.bimodalAltMatchProviderWrong 31 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong (Count)
|
|
system.cpu1.branchPred.tage.bimodalProviderWrong 303 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong (Count)
|
|
system.cpu1.branchPred.tage.altMatchProviderWouldHaveHit 13 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProviderWouldHaveHit 36 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::0 0 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::1 1049925 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::2 387852 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::3 307 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::4 2326 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::5 118 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::6 368 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::7 616 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::8 16 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::9 74 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::10 67 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::11 105 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::12 74 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::0 1052335 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::1 386922 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::2 48 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::3 1155 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::4 424 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::5 591 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::6 92 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::7 32 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::8 3 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::9 68 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::10 104 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::11 74 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::12 0 # TAGE provider for alt match (Count)
|
|
system.cpu1.commit.commitSquashedInsts 2772831 # The number of squashed insts skipped by commit (Count)
|
|
system.cpu1.commit.commitNonSpecStalls 42 # The number of times commit has been forced to stall to communicate backwards (Count)
|
|
system.cpu1.commit.branchMispredicts 536 # The number of times a branch was mispredicted (Count)
|
|
system.cpu1.commit.numCommittedDist::samples 457952737 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::mean 0.060172 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::stdev 0.438319 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::0 447660491 97.75% 97.75% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::1 3031700 0.66% 98.41% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::2 318394 0.07% 98.48% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::3 4464629 0.97% 99.46% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::4 1961170 0.43% 99.89% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::5 493403 0.11% 99.99% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::6 317 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::7 1280 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::8 21353 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::total 457952737 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.amos 0 # Number of atomic instructions committed (Count)
|
|
system.cpu1.commit.membars 28 # Number of memory barriers committed (Count)
|
|
system.cpu1.commit.functionCalls 2307 # Number of function calls committed. (Count)
|
|
system.cpu1.commit.committedInstType_0::No_OpClass 250 0.00% 0.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::IntAlu 20073762 72.85% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::IntMult 41 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::IntDiv 56 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatAdd 146 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdAdd 10 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdAlu 237 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdCmp 4 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdCvt 76 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdMisc 235 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdShift 3 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdAes 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdAesMix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::Matrix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::MatrixMov 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::MatrixOP 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::MemRead 2502626 9.08% 81.93% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::MemWrite 4977671 18.06% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatMemRead 125 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::total 27555756 # Class of committed instruction (Count)
|
|
system.cpu1.commit.commitEligibleSamples 21353 # number cycles where commit BW limit reached (Cycle)
|
|
system.cpu1.commitStats0.numInsts 19999658 # Number of instructions committed (thread level) (Count)
|
|
system.cpu1.commitStats0.numOps 27555756 # Number of ops (including micro ops) committed (thread level) (Count)
|
|
system.cpu1.commitStats0.numInstsNotNOP 19999658 # Number of instructions committed excluding NOPs or prefetches (Count)
|
|
system.cpu1.commitStats0.numOpsNotNOP 27555756 # Number of Ops (including micro ops) Simulated (Count)
|
|
system.cpu1.commitStats0.cpi 22.917596 # CPI: cycles per instruction (thread level) ((Cycle/Count))
|
|
system.cpu1.commitStats0.ipc 0.043635 # IPC: instructions per cycle (thread level) ((Count/Cycle))
|
|
system.cpu1.commitStats0.numMemRefs 7480936 # Number of memory references committed (Count)
|
|
system.cpu1.commitStats0.numFpInsts 1513 # Number of float instructions (Count)
|
|
system.cpu1.commitStats0.numIntInsts 27554618 # Number of integer instructions (Count)
|
|
system.cpu1.commitStats0.numLoadInsts 2502751 # Number of load instructions (Count)
|
|
system.cpu1.commitStats0.numStoreInsts 4978185 # Number of store instructions (Count)
|
|
system.cpu1.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
|
|
system.cpu1.commitStats0.committedInstType::No_OpClass 250 0.00% 0.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::IntAlu 20073762 72.85% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::IntMult 41 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::IntDiv 56 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatAdd 146 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdAdd 10 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdAlu 237 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdCmp 4 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdCvt 76 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdMisc 235 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdShift 3 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdAes 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::Matrix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::MatrixMov 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::MatrixOP 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::MemRead 2502626 9.08% 81.93% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::MemWrite 4977671 18.06% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatMemRead 125 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::total 27555756 # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedControl::IsControl 2516633 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsDirectControl 2512173 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsIndirectControl 4460 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsCondControl 2506615 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsUncondControl 10018 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsCall 2307 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsReturn 2304 # Class of control type instructions committed (Count)
|
|
system.cpu1.dcache.demandHits::cpu1.data 2508071 # number of demand (read+write) hits (Count)
|
|
system.cpu1.dcache.demandHits::total 2508071 # number of demand (read+write) hits (Count)
|
|
system.cpu1.dcache.overallHits::cpu1.data 2508071 # number of overall hits (Count)
|
|
system.cpu1.dcache.overallHits::total 2508071 # number of overall hits (Count)
|
|
system.cpu1.dcache.demandMisses::cpu1.data 2485847 # number of demand (read+write) misses (Count)
|
|
system.cpu1.dcache.demandMisses::total 2485847 # number of demand (read+write) misses (Count)
|
|
system.cpu1.dcache.overallMisses::cpu1.data 2485847 # number of overall misses (Count)
|
|
system.cpu1.dcache.overallMisses::total 2485847 # number of overall misses (Count)
|
|
system.cpu1.dcache.demandMissLatency::cpu1.data 226367652500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu1.dcache.demandMissLatency::total 226367652500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu1.dcache.overallMissLatency::cpu1.data 226367652500 # number of overall miss ticks (Tick)
|
|
system.cpu1.dcache.overallMissLatency::total 226367652500 # number of overall miss ticks (Tick)
|
|
system.cpu1.dcache.demandAccesses::cpu1.data 4993918 # number of demand (read+write) accesses (Count)
|
|
system.cpu1.dcache.demandAccesses::total 4993918 # number of demand (read+write) accesses (Count)
|
|
system.cpu1.dcache.overallAccesses::cpu1.data 4993918 # number of overall (read+write) accesses (Count)
|
|
system.cpu1.dcache.overallAccesses::total 4993918 # number of overall (read+write) accesses (Count)
|
|
system.cpu1.dcache.demandMissRate::cpu1.data 0.497775 # miss rate for demand accesses (Ratio)
|
|
system.cpu1.dcache.demandMissRate::total 0.497775 # miss rate for demand accesses (Ratio)
|
|
system.cpu1.dcache.overallMissRate::cpu1.data 0.497775 # miss rate for overall accesses (Ratio)
|
|
system.cpu1.dcache.overallMissRate::total 0.497775 # miss rate for overall accesses (Ratio)
|
|
system.cpu1.dcache.demandAvgMissLatency::cpu1.data 91062.584503 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu1.dcache.demandAvgMissLatency::total 91062.584503 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu1.dcache.overallAvgMissLatency::cpu1.data 91062.584503 # average overall miss latency ((Tick/Count))
|
|
system.cpu1.dcache.overallAvgMissLatency::total 91062.584503 # average overall miss latency ((Tick/Count))
|
|
system.cpu1.dcache.blockedCycles::no_mshrs 505 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.dcache.blockedCauses::no_mshrs 10 # number of times access was blocked (Count)
|
|
system.cpu1.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu1.dcache.avgBlocked::no_mshrs 50.500000 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.dcache.writebacks::writebacks 2483812 # number of writebacks (Count)
|
|
system.cpu1.dcache.writebacks::total 2483812 # number of writebacks (Count)
|
|
system.cpu1.dcache.demandMshrHits::cpu1.data 1042 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu1.dcache.demandMshrHits::total 1042 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu1.dcache.overallMshrHits::cpu1.data 1042 # number of overall MSHR hits (Count)
|
|
system.cpu1.dcache.overallMshrHits::total 1042 # number of overall MSHR hits (Count)
|
|
system.cpu1.dcache.demandMshrMisses::cpu1.data 2484805 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu1.dcache.demandMshrMisses::total 2484805 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu1.dcache.overallMshrMisses::cpu1.data 2484805 # number of overall MSHR misses (Count)
|
|
system.cpu1.dcache.overallMshrMisses::total 2484805 # number of overall MSHR misses (Count)
|
|
system.cpu1.dcache.demandMshrMissLatency::cpu1.data 223804400500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.demandMshrMissLatency::total 223804400500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.overallMshrMissLatency::cpu1.data 223804400500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.overallMshrMissLatency::total 223804400500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.demandMshrMissRate::cpu1.data 0.497566 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu1.dcache.demandMshrMissRate::total 0.497566 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu1.dcache.overallMshrMissRate::cpu1.data 0.497566 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu1.dcache.overallMshrMissRate::total 0.497566 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu1.dcache.demandAvgMshrMissLatency::cpu1.data 90069.200802 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.demandAvgMshrMissLatency::total 90069.200802 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.overallAvgMshrMissLatency::cpu1.data 90069.200802 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.overallAvgMshrMissLatency::total 90069.200802 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.replacements 2484291 # number of replacements (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.hits::cpu1.data 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.hits::total 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.misses::cpu1.data 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.misses::total 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.missLatency::cpu1.data 100500 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu1.dcache.LockedRMWReadReq.missLatency::total 100500 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu1.dcache.LockedRMWReadReq.accesses::cpu1.data 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.accesses::total 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.missRate::cpu1.data 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu1.dcache.LockedRMWReadReq.missRate::total 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu1.dcache.LockedRMWReadReq.avgMissLatency::cpu1.data 100500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.LockedRMWReadReq.avgMissLatency::total 100500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMisses::cpu1.data 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMisses::total 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMissLatency::cpu1.data 252000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMissLatency::total 252000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMissRate::cpu1.data 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMissRate::total 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu1.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu1.data 252000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.LockedRMWReadReq.avgMshrMissLatency::total 252000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.LockedRMWWriteReq.hits::cpu1.data 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu1.dcache.LockedRMWWriteReq.hits::total 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu1.dcache.LockedRMWWriteReq.accesses::cpu1.data 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.LockedRMWWriteReq.accesses::total 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.ReadReq.hits::cpu1.data 13985 # number of ReadReq hits (Count)
|
|
system.cpu1.dcache.ReadReq.hits::total 13985 # number of ReadReq hits (Count)
|
|
system.cpu1.dcache.ReadReq.misses::cpu1.data 1793 # number of ReadReq misses (Count)
|
|
system.cpu1.dcache.ReadReq.misses::total 1793 # number of ReadReq misses (Count)
|
|
system.cpu1.dcache.ReadReq.missLatency::cpu1.data 136975000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu1.dcache.ReadReq.missLatency::total 136975000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu1.dcache.ReadReq.accesses::cpu1.data 15778 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.ReadReq.accesses::total 15778 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.ReadReq.missRate::cpu1.data 0.113639 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.dcache.ReadReq.missRate::total 0.113639 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.dcache.ReadReq.avgMissLatency::cpu1.data 76394.311210 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.ReadReq.avgMissLatency::total 76394.311210 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.ReadReq.mshrHits::cpu1.data 1042 # number of ReadReq MSHR hits (Count)
|
|
system.cpu1.dcache.ReadReq.mshrHits::total 1042 # number of ReadReq MSHR hits (Count)
|
|
system.cpu1.dcache.ReadReq.mshrMisses::cpu1.data 751 # number of ReadReq MSHR misses (Count)
|
|
system.cpu1.dcache.ReadReq.mshrMisses::total 751 # number of ReadReq MSHR misses (Count)
|
|
system.cpu1.dcache.ReadReq.mshrMissLatency::cpu1.data 57776000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.ReadReq.mshrMissLatency::total 57776000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.ReadReq.mshrMissRate::cpu1.data 0.047598 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.dcache.ReadReq.mshrMissRate::total 0.047598 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.dcache.ReadReq.avgMshrMissLatency::cpu1.data 76932.090546 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.ReadReq.avgMshrMissLatency::total 76932.090546 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.WriteReq.hits::cpu1.data 2494086 # number of WriteReq hits (Count)
|
|
system.cpu1.dcache.WriteReq.hits::total 2494086 # number of WriteReq hits (Count)
|
|
system.cpu1.dcache.WriteReq.misses::cpu1.data 2484054 # number of WriteReq misses (Count)
|
|
system.cpu1.dcache.WriteReq.misses::total 2484054 # number of WriteReq misses (Count)
|
|
system.cpu1.dcache.WriteReq.missLatency::cpu1.data 226230677500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu1.dcache.WriteReq.missLatency::total 226230677500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu1.dcache.WriteReq.accesses::cpu1.data 4978140 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.WriteReq.accesses::total 4978140 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.WriteReq.missRate::cpu1.data 0.498992 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu1.dcache.WriteReq.missRate::total 0.498992 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu1.dcache.WriteReq.avgMissLatency::cpu1.data 91073.172121 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.WriteReq.avgMissLatency::total 91073.172121 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.WriteReq.mshrMisses::cpu1.data 2484054 # number of WriteReq MSHR misses (Count)
|
|
system.cpu1.dcache.WriteReq.mshrMisses::total 2484054 # number of WriteReq MSHR misses (Count)
|
|
system.cpu1.dcache.WriteReq.mshrMissLatency::cpu1.data 223746624500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.WriteReq.mshrMissLatency::total 223746624500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.WriteReq.mshrMissRate::cpu1.data 0.498992 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu1.dcache.WriteReq.mshrMissRate::total 0.498992 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu1.dcache.WriteReq.avgMshrMissLatency::cpu1.data 90073.172524 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.WriteReq.avgMshrMissLatency::total 90073.172524 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.dcache.tags.tagsInUse 511.912173 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu1.dcache.tags.totalRefs 4992903 # Total number of references to valid blocks. (Count)
|
|
system.cpu1.dcache.tags.sampledRefs 2484803 # Sample count of references to valid blocks. (Count)
|
|
system.cpu1.dcache.tags.avgRefs 2.009376 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu1.dcache.tags.warmupTick 188500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu1.dcache.tags.occupancies::cpu1.data 511.912173 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu1.dcache.tags.avgOccs::cpu1.data 0.999828 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu1.dcache.tags.avgOccs::total 0.999828 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu1.dcache.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
|
|
system.cpu1.dcache.tags.ageTaskId_1024::0 110 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu1.dcache.tags.ageTaskId_1024::1 146 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu1.dcache.tags.ageTaskId_1024::4 256 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu1.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu1.dcache.tags.tagAccesses 12472695 # Number of tag accesses (Count)
|
|
system.cpu1.dcache.tags.dataAccesses 12472695 # Number of data accesses (Count)
|
|
system.cpu1.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.decode.idleCycles 1292906 # Number of cycles decode is idle (Cycle)
|
|
system.cpu1.decode.blockedCycles 453045876 # Number of cycles decode is blocked (Cycle)
|
|
system.cpu1.decode.runCycles 505925 # Number of cycles decode is running (Cycle)
|
|
system.cpu1.decode.unblockCycles 3438056 # Number of cycles decode is unblocking (Cycle)
|
|
system.cpu1.decode.squashCycles 16994 # Number of cycles decode is squashing (Cycle)
|
|
system.cpu1.decode.branchResolved 2772740 # Number of times decode resolved a branch (Count)
|
|
system.cpu1.decode.branchMispred 272 # Number of times decode detected a branch misprediction (Count)
|
|
system.cpu1.decode.decodedInsts 30644404 # Number of instructions handled by decode (Count)
|
|
system.cpu1.decode.squashedInsts 1183 # Number of squashed instructions handled by decode (Count)
|
|
system.cpu1.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu1.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu1.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.dtb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu1.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu1.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu1.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu1.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu1.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu1.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu1.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu1.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.executeStats0.numInsts 30452742 # Number of executed instructions (Count)
|
|
system.cpu1.executeStats0.numNop 0 # Number of nop insts executed (Count)
|
|
system.cpu1.executeStats0.numBranches 2779804 # Number of branches executed (Count)
|
|
system.cpu1.executeStats0.numLoadInsts 2766294 # Number of load instructions executed (Count)
|
|
system.cpu1.executeStats0.numStoreInsts 5503289 # Number of stores executed (Count)
|
|
system.cpu1.executeStats0.instRate 0.066441 # Inst execution rate ((Count/Cycle))
|
|
system.cpu1.executeStats0.numCCRegReads 13887950 # Number of times the CC registers were read (Count)
|
|
system.cpu1.executeStats0.numCCRegWrites 16559130 # Number of times the CC registers were written (Count)
|
|
system.cpu1.executeStats0.numFpRegReads 2147 # Number of times the floating registers were read (Count)
|
|
system.cpu1.executeStats0.numFpRegWrites 1094 # Number of times the floating registers were written (Count)
|
|
system.cpu1.executeStats0.numIntRegReads 49749354 # Number of times the integer registers were read (Count)
|
|
system.cpu1.executeStats0.numIntRegWrites 19397681 # Number of times the integer registers were written (Count)
|
|
system.cpu1.executeStats0.numMemRefs 8269583 # Number of memory refs (Count)
|
|
system.cpu1.executeStats0.numMiscRegReads 13828474 # Number of times the Misc registers were read (Count)
|
|
system.cpu1.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu1.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
|
|
system.cpu1.fetch.predictedBranches 2843020 # Number of branches that fetch has predicted taken (Count)
|
|
system.cpu1.fetch.cycles 458242034 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
|
|
system.cpu1.fetch.squashCycles 34524 # Number of cycles fetch has spent squashing (Cycle)
|
|
system.cpu1.fetch.miscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
|
|
system.cpu1.fetch.pendingTrapStallCycles 186 # Number of stall cycles due to pending traps (Cycle)
|
|
system.cpu1.fetch.cacheLines 19521 # Number of cache lines fetched (Count)
|
|
system.cpu1.fetch.icacheSquashes 415 # Number of outstanding Icache misses that were squashed (Count)
|
|
system.cpu1.fetch.nisnDist::samples 458299757 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::mean 0.068596 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::stdev 0.657271 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::0 451948397 98.61% 98.61% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::1 655790 0.14% 98.76% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::2 655101 0.14% 98.90% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::3 1537974 0.34% 99.24% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::4 316741 0.07% 99.30% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::5 311850 0.07% 99.37% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::6 313962 0.07% 99.44% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::7 331782 0.07% 99.51% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::8 2228160 0.49% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::total 458299757 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetchStats0.numInsts 22834825 # Number of instructions fetched (thread level) (Count)
|
|
system.cpu1.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
|
|
system.cpu1.fetchStats0.fetchRate 0.049820 # Number of inst fetches per cycle ((Count/Cycle))
|
|
system.cpu1.fetchStats0.numBranches 2864347 # Number of branches fetched (Count)
|
|
system.cpu1.fetchStats0.branchRate 0.006249 # Number of branch fetches per cycle (Ratio)
|
|
system.cpu1.fetchStats0.icacheStallCycles 40242 # ICache total stall cycles (Cycle)
|
|
system.cpu1.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
|
|
system.cpu1.icache.demandHits::cpu1.inst 18768 # number of demand (read+write) hits (Count)
|
|
system.cpu1.icache.demandHits::total 18768 # number of demand (read+write) hits (Count)
|
|
system.cpu1.icache.overallHits::cpu1.inst 18768 # number of overall hits (Count)
|
|
system.cpu1.icache.overallHits::total 18768 # number of overall hits (Count)
|
|
system.cpu1.icache.demandMisses::cpu1.inst 753 # number of demand (read+write) misses (Count)
|
|
system.cpu1.icache.demandMisses::total 753 # number of demand (read+write) misses (Count)
|
|
system.cpu1.icache.overallMisses::cpu1.inst 753 # number of overall misses (Count)
|
|
system.cpu1.icache.overallMisses::total 753 # number of overall misses (Count)
|
|
system.cpu1.icache.demandMissLatency::cpu1.inst 58649000 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu1.icache.demandMissLatency::total 58649000 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu1.icache.overallMissLatency::cpu1.inst 58649000 # number of overall miss ticks (Tick)
|
|
system.cpu1.icache.overallMissLatency::total 58649000 # number of overall miss ticks (Tick)
|
|
system.cpu1.icache.demandAccesses::cpu1.inst 19521 # number of demand (read+write) accesses (Count)
|
|
system.cpu1.icache.demandAccesses::total 19521 # number of demand (read+write) accesses (Count)
|
|
system.cpu1.icache.overallAccesses::cpu1.inst 19521 # number of overall (read+write) accesses (Count)
|
|
system.cpu1.icache.overallAccesses::total 19521 # number of overall (read+write) accesses (Count)
|
|
system.cpu1.icache.demandMissRate::cpu1.inst 0.038574 # miss rate for demand accesses (Ratio)
|
|
system.cpu1.icache.demandMissRate::total 0.038574 # miss rate for demand accesses (Ratio)
|
|
system.cpu1.icache.overallMissRate::cpu1.inst 0.038574 # miss rate for overall accesses (Ratio)
|
|
system.cpu1.icache.overallMissRate::total 0.038574 # miss rate for overall accesses (Ratio)
|
|
system.cpu1.icache.demandAvgMissLatency::cpu1.inst 77887.118194 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu1.icache.demandAvgMissLatency::total 77887.118194 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu1.icache.overallAvgMissLatency::cpu1.inst 77887.118194 # average overall miss latency ((Tick/Count))
|
|
system.cpu1.icache.overallAvgMissLatency::total 77887.118194 # average overall miss latency ((Tick/Count))
|
|
system.cpu1.icache.blockedCycles::no_mshrs 339 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.icache.blockedCauses::no_mshrs 4 # number of times access was blocked (Count)
|
|
system.cpu1.icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu1.icache.avgBlocked::no_mshrs 84.750000 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.icache.writebacks::writebacks 170 # number of writebacks (Count)
|
|
system.cpu1.icache.writebacks::total 170 # number of writebacks (Count)
|
|
system.cpu1.icache.demandMshrHits::cpu1.inst 174 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu1.icache.demandMshrHits::total 174 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu1.icache.overallMshrHits::cpu1.inst 174 # number of overall MSHR hits (Count)
|
|
system.cpu1.icache.overallMshrHits::total 174 # number of overall MSHR hits (Count)
|
|
system.cpu1.icache.demandMshrMisses::cpu1.inst 579 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu1.icache.demandMshrMisses::total 579 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu1.icache.overallMshrMisses::cpu1.inst 579 # number of overall MSHR misses (Count)
|
|
system.cpu1.icache.overallMshrMisses::total 579 # number of overall MSHR misses (Count)
|
|
system.cpu1.icache.demandMshrMissLatency::cpu1.inst 47918000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu1.icache.demandMshrMissLatency::total 47918000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu1.icache.overallMshrMissLatency::cpu1.inst 47918000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu1.icache.overallMshrMissLatency::total 47918000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu1.icache.demandMshrMissRate::cpu1.inst 0.029660 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu1.icache.demandMshrMissRate::total 0.029660 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu1.icache.overallMshrMissRate::cpu1.inst 0.029660 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu1.icache.overallMshrMissRate::total 0.029660 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu1.icache.demandAvgMshrMissLatency::cpu1.inst 82759.930915 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.demandAvgMshrMissLatency::total 82759.930915 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.overallAvgMshrMissLatency::cpu1.inst 82759.930915 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.overallAvgMshrMissLatency::total 82759.930915 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.replacements 170 # number of replacements (Count)
|
|
system.cpu1.icache.ReadReq.hits::cpu1.inst 18768 # number of ReadReq hits (Count)
|
|
system.cpu1.icache.ReadReq.hits::total 18768 # number of ReadReq hits (Count)
|
|
system.cpu1.icache.ReadReq.misses::cpu1.inst 753 # number of ReadReq misses (Count)
|
|
system.cpu1.icache.ReadReq.misses::total 753 # number of ReadReq misses (Count)
|
|
system.cpu1.icache.ReadReq.missLatency::cpu1.inst 58649000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu1.icache.ReadReq.missLatency::total 58649000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu1.icache.ReadReq.accesses::cpu1.inst 19521 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.icache.ReadReq.accesses::total 19521 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.icache.ReadReq.missRate::cpu1.inst 0.038574 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.icache.ReadReq.missRate::total 0.038574 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.icache.ReadReq.avgMissLatency::cpu1.inst 77887.118194 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu1.icache.ReadReq.avgMissLatency::total 77887.118194 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu1.icache.ReadReq.mshrHits::cpu1.inst 174 # number of ReadReq MSHR hits (Count)
|
|
system.cpu1.icache.ReadReq.mshrHits::total 174 # number of ReadReq MSHR hits (Count)
|
|
system.cpu1.icache.ReadReq.mshrMisses::cpu1.inst 579 # number of ReadReq MSHR misses (Count)
|
|
system.cpu1.icache.ReadReq.mshrMisses::total 579 # number of ReadReq MSHR misses (Count)
|
|
system.cpu1.icache.ReadReq.mshrMissLatency::cpu1.inst 47918000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.icache.ReadReq.mshrMissLatency::total 47918000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.icache.ReadReq.mshrMissRate::cpu1.inst 0.029660 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.icache.ReadReq.mshrMissRate::total 0.029660 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.icache.ReadReq.avgMshrMissLatency::cpu1.inst 82759.930915 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.ReadReq.avgMshrMissLatency::total 82759.930915 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.icache.tags.tagsInUse 406.961600 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu1.icache.tags.totalRefs 19347 # Total number of references to valid blocks. (Count)
|
|
system.cpu1.icache.tags.sampledRefs 579 # Sample count of references to valid blocks. (Count)
|
|
system.cpu1.icache.tags.avgRefs 33.414508 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu1.icache.tags.warmupTick 94500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu1.icache.tags.occupancies::cpu1.inst 406.961600 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu1.icache.tags.avgOccs::cpu1.inst 0.794847 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu1.icache.tags.avgOccs::total 0.794847 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu1.icache.tags.occupanciesTaskId::1024 407 # Occupied blocks per task id (Count)
|
|
system.cpu1.icache.tags.ageTaskId_1024::4 407 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu1.icache.tags.ratioOccsTaskId::1024 0.794922 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu1.icache.tags.tagAccesses 39621 # Number of tag accesses (Count)
|
|
system.cpu1.icache.tags.dataAccesses 39621 # Number of data accesses (Count)
|
|
system.cpu1.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
|
|
system.cpu1.iew.squashCycles 16994 # Number of cycles IEW is squashing (Cycle)
|
|
system.cpu1.iew.blockCycles 400618 # Number of cycles IEW is blocking (Cycle)
|
|
system.cpu1.iew.unblockCycles 253094878 # Number of cycles IEW is unblocking (Cycle)
|
|
system.cpu1.iew.dispatchedInsts 30459903 # Number of instructions dispatched to IQ (Count)
|
|
system.cpu1.iew.dispSquashedInsts 67 # Number of squashed instructions skipped by dispatch (Count)
|
|
system.cpu1.iew.dispLoadInsts 2767078 # Number of dispatched load instructions (Count)
|
|
system.cpu1.iew.dispStoreInsts 5503853 # Number of dispatched store instructions (Count)
|
|
system.cpu1.iew.dispNonSpecInsts 35 # Number of dispatched non-speculative instructions (Count)
|
|
system.cpu1.iew.iqFullEvents 1620 # Number of times the IQ has become full, causing a stall (Count)
|
|
system.cpu1.iew.lsqFullEvents 253109637 # Number of times the LSQ has become full, causing a stall (Count)
|
|
system.cpu1.iew.memOrderViolationEvents 62 # Number of memory order violations (Count)
|
|
system.cpu1.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly (Count)
|
|
system.cpu1.iew.predictedNotTakenIncorrect 535 # Number of branches that were predicted not taken incorrectly (Count)
|
|
system.cpu1.iew.branchMispredicts 611 # Number of branch mispredicts detected at execute (Count)
|
|
system.cpu1.iew.instsToCommit 30452460 # Cumulative count of insts sent to commit (Count)
|
|
system.cpu1.iew.writebackCount 30190047 # Cumulative count of insts written-back (Count)
|
|
system.cpu1.iew.producerInst 12047018 # Number of instructions producing a value (Count)
|
|
system.cpu1.iew.consumerInst 19244377 # Number of instructions consuming a value (Count)
|
|
system.cpu1.iew.wbRate 0.065868 # Insts written-back per cycle ((Count/Cycle))
|
|
system.cpu1.iew.wbFanout 0.626002 # Average fanout of values written-back ((Count/Count))
|
|
system.cpu1.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
|
|
system.cpu1.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu1.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu1.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.itb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu1.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu1.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu1.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu1.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu1.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu1.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu1.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu1.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.lsq0.forwLoads 2750414 # Number of loads that had data forwarded from stores (Count)
|
|
system.cpu1.lsq0.squashedLoads 264327 # Number of loads squashed (Count)
|
|
system.cpu1.lsq0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed (Count)
|
|
system.cpu1.lsq0.memOrderViolation 62 # Number of memory ordering violations (Count)
|
|
system.cpu1.lsq0.squashedStores 525668 # Number of stores squashed (Count)
|
|
system.cpu1.lsq0.rescheduledLoads 1 # Number of loads that were rescheduled (Count)
|
|
system.cpu1.lsq0.blockedByCache 9 # Number of times an access to memory failed due to the cache being blocked (Count)
|
|
system.cpu1.lsq0.loadToUse::samples 2502751 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::mean 2.106295 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::stdev 4.179802 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::0-9 2501094 99.93% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::10-19 9 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::20-29 19 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::30-39 4 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::40-49 1 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::50-59 2 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::100-109 1 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::110-119 6 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::120-129 27 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::130-139 43 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::140-149 1258 0.05% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::150-159 74 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::160-169 39 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::170-179 83 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::180-189 7 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::190-199 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::200-209 32 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::210-219 12 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::220-229 3 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::230-239 7 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::240-249 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::260-269 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::270-279 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::280-289 4 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::290-299 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::overflows 20 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::max_value 734 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::total 2502751 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.mmu.dtb.rdAccesses 2766280 # TLB accesses on read requests (Count)
|
|
system.cpu1.mmu.dtb.wrAccesses 5503289 # TLB accesses on write requests (Count)
|
|
system.cpu1.mmu.dtb.rdMisses 94 # TLB misses on read requests (Count)
|
|
system.cpu1.mmu.dtb.wrMisses 300973 # TLB misses on write requests (Count)
|
|
system.cpu1.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
|
|
system.cpu1.mmu.itb.wrAccesses 19554 # TLB accesses on write requests (Count)
|
|
system.cpu1.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
|
|
system.cpu1.mmu.itb.wrMisses 76 # TLB misses on write requests (Count)
|
|
system.cpu1.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.power_state.pwrStateResidencyTicks::ON 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.rename.squashCycles 16994 # Number of cycles rename is squashing (Cycle)
|
|
system.cpu1.rename.idleCycles 2275941 # Number of cycles rename is idle (Cycle)
|
|
system.cpu1.rename.blockCycles 253499217 # Number of cycles rename is blocking (Cycle)
|
|
system.cpu1.rename.serializeStallCycles 1088 # count of cycles rename stalled for serializing inst (Cycle)
|
|
system.cpu1.rename.runCycles 2944199 # Number of cycles rename is running (Cycle)
|
|
system.cpu1.rename.unblockCycles 199562318 # Number of cycles rename is unblocking (Cycle)
|
|
system.cpu1.rename.renamedInsts 30511693 # Number of instructions processed by rename (Count)
|
|
system.cpu1.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full (Count)
|
|
system.cpu1.rename.IQFullEvents 10631 # Number of times rename has blocked due to IQ full (Count)
|
|
system.cpu1.rename.SQFullEvents 198862503 # Number of times rename has blocked due to SQ full (Count)
|
|
system.cpu1.rename.renamedOperands 63784321 # Number of destination operands rename has renamed (Count)
|
|
system.cpu1.rename.lookups 124729310 # Number of register rename lookups that rename has made (Count)
|
|
system.cpu1.rename.intLookups 49880512 # Number of integer rename lookups (Count)
|
|
system.cpu1.rename.fpLookups 2341 # Number of floating rename lookups (Count)
|
|
system.cpu1.rename.committedMaps 57520768 # Number of HB maps that are committed (Count)
|
|
system.cpu1.rename.undoneMaps 6263553 # Number of HB maps that are undone due to squashing (Count)
|
|
system.cpu1.rename.serializing 45 # count of serializing insts renamed (Count)
|
|
system.cpu1.rename.tempSerializing 45 # count of temporary serializing insts renamed (Count)
|
|
system.cpu1.rename.skidInsts 18601304 # count of insts added to the skid buffer (Count)
|
|
system.cpu1.rob.reads 488046745 # The number of ROB reads (Count)
|
|
system.cpu1.rob.writes 61004208 # The number of ROB writes (Count)
|
|
system.cpu1.thread_0.numInsts 19999658 # Number of Instructions committed (Count)
|
|
system.cpu1.thread_0.numOps 27555756 # Number of Ops committed (Count)
|
|
system.cpu1.thread_0.numMemRefs 0 # Number of Memory References (Count)
|
|
system.cpu1.workload.numSyscalls 14 # Number of system calls (Count)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks (Tick)
|
|
system.cpu_voltage_domain.voltage 1 # Voltage in Volts (Volt)
|
|
system.l2.demandHits::cpu0.inst 11 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu0.data 26 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu1.inst 11 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu1.data 29 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::total 77 # number of demand (read+write) hits (Count)
|
|
system.l2.overallHits::cpu0.inst 11 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu0.data 26 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu1.inst 11 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu1.data 29 # number of overall hits (Count)
|
|
system.l2.overallHits::total 77 # number of overall hits (Count)
|
|
system.l2.demandMisses::cpu0.inst 566 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu0.data 2484818 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu1.inst 566 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu1.data 2484775 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::total 4970725 # number of demand (read+write) misses (Count)
|
|
system.l2.overallMisses::cpu0.inst 566 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu0.data 2484818 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu1.inst 566 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu1.data 2484775 # number of overall misses (Count)
|
|
system.l2.overallMisses::total 4970725 # number of overall misses (Count)
|
|
system.l2.demandMissLatency::cpu0.inst 46746000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu0.data 220076950000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu1.inst 46924500 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu1.data 220076938500 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::total 440247559000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu0.inst 46746000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu0.data 220076950000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu1.inst 46924500 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu1.data 220076938500 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::total 440247559000 # number of overall miss ticks (Tick)
|
|
system.l2.demandAccesses::cpu0.inst 577 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu0.data 2484844 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu1.inst 577 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu1.data 2484804 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::total 4970802 # number of demand (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu0.inst 577 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu0.data 2484844 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu1.inst 577 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu1.data 2484804 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::total 4970802 # number of overall (read+write) accesses (Count)
|
|
system.l2.demandMissRate::cpu0.inst 0.980936 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu0.data 0.999990 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu1.inst 0.980936 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu1.data 0.999988 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::total 0.999985 # miss rate for demand accesses (Ratio)
|
|
system.l2.overallMissRate::cpu0.inst 0.980936 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu0.data 0.999990 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu1.inst 0.980936 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu1.data 0.999988 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::total 0.999985 # miss rate for overall accesses (Ratio)
|
|
system.l2.demandAvgMissLatency::cpu0.inst 82590.106007 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu0.data 88568.639635 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu1.inst 82905.477032 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu1.data 88570.167721 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::total 88568.077896 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu0.inst 82590.106007 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu0.data 88568.639635 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu1.inst 82905.477032 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu1.data 88570.167721 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::total 88568.077896 # average overall miss latency ((Tick/Count))
|
|
system.l2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.l2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.l2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.l2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.l2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.l2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.l2.writebacks::writebacks 4951770 # number of writebacks (Count)
|
|
system.l2.writebacks::total 4951770 # number of writebacks (Count)
|
|
system.l2.demandMshrMisses::cpu0.inst 566 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu0.data 2484818 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu1.inst 566 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu1.data 2484775 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::total 4970725 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu0.inst 566 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu0.data 2484818 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu1.inst 566 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu1.data 2484775 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::total 4970725 # number of overall MSHR misses (Count)
|
|
system.l2.demandMshrMissLatency::cpu0.inst 41086000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu0.data 195228780000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu1.inst 41264500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu1.data 195229198500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::total 390540329000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu0.inst 41086000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu0.data 195228780000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu1.inst 41264500 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu1.data 195229198500 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::total 390540329000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissRate::cpu0.inst 0.980936 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu0.data 0.999990 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu1.inst 0.980936 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu1.data 0.999988 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::total 0.999985 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu0.inst 0.980936 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu0.data 0.999990 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu1.inst 0.980936 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu1.data 0.999988 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::total 0.999985 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.demandAvgMshrMissLatency::cpu0.inst 72590.106007 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu0.data 78568.643659 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu1.inst 72905.477032 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu1.data 78570.171746 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::total 78568.081920 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu0.inst 72590.106007 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu0.data 78568.643659 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu1.inst 72905.477032 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu1.data 78570.171746 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::total 78568.081920 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.replacements 4954343 # number of replacements (Count)
|
|
system.l2.ReadCleanReq.hits::cpu0.inst 11 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.hits::cpu1.inst 11 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.hits::total 22 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.misses::cpu0.inst 566 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.misses::cpu1.inst 566 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.misses::total 1132 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.missLatency::cpu0.inst 46746000 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.missLatency::cpu1.inst 46924500 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.missLatency::total 93670500 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.accesses::cpu0.inst 577 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.accesses::cpu1.inst 577 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.accesses::total 1154 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.missRate::cpu0.inst 0.980936 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.missRate::cpu1.inst 0.980936 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.missRate::total 0.980936 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.avgMissLatency::cpu0.inst 82590.106007 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMissLatency::cpu1.inst 82905.477032 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMissLatency::total 82747.791519 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.mshrMisses::cpu0.inst 566 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMisses::cpu1.inst 566 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMisses::total 1132 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMissLatency::cpu0.inst 41086000 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissLatency::cpu1.inst 41264500 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissLatency::total 82350500 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissRate::cpu0.inst 0.980936 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.mshrMissRate::cpu1.inst 0.980936 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.mshrMissRate::total 0.980936 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::cpu0.inst 72590.106007 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::cpu1.inst 72905.477032 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::total 72747.791519 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.hits::cpu0.data 7 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.hits::cpu1.data 6 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.hits::total 13 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.misses::cpu0.data 2484090 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.misses::cpu1.data 2484047 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.misses::total 4968137 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.missLatency::cpu0.data 220020669500 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.missLatency::cpu1.data 220020556500 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.missLatency::total 440041226000 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.accesses::cpu0.data 2484097 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.accesses::cpu1.data 2484053 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.accesses::total 4968150 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.missRate::cpu0.data 0.999997 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.missRate::cpu1.data 0.999998 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.missRate::total 0.999997 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.avgMissLatency::cpu0.data 88571.939624 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMissLatency::cpu1.data 88573.427355 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMissLatency::total 88572.683483 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.mshrMisses::cpu0.data 2484090 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMisses::cpu1.data 2484047 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMisses::total 4968137 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMissLatency::cpu0.data 195179779500 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissLatency::cpu1.data 195180096500 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissLatency::total 390359876000 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissRate::cpu0.data 0.999997 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.mshrMissRate::cpu1.data 0.999998 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.mshrMissRate::total 0.999997 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.avgMshrMissLatency::cpu0.data 78571.943649 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMshrMissLatency::cpu1.data 78573.431380 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMshrMissLatency::total 78572.687508 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.hits::cpu0.data 19 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.hits::cpu1.data 23 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.hits::total 42 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.misses::cpu0.data 728 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.misses::cpu1.data 728 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.misses::total 1456 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.missLatency::cpu0.data 56280500 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.missLatency::cpu1.data 56382000 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.missLatency::total 112662500 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.accesses::cpu0.data 747 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.accesses::cpu1.data 751 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.accesses::total 1498 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.missRate::cpu0.data 0.974565 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.missRate::cpu1.data 0.969374 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.missRate::total 0.971963 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.avgMissLatency::cpu0.data 77308.379121 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMissLatency::cpu1.data 77447.802198 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMissLatency::total 77378.090659 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.mshrMisses::cpu0.data 728 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMisses::cpu1.data 728 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMisses::total 1456 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMissLatency::cpu0.data 49000500 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissLatency::cpu1.data 49102000 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissLatency::total 98102500 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissRate::cpu0.data 0.974565 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.mshrMissRate::cpu1.data 0.969374 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.mshrMissRate::total 0.971963 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::cpu0.data 67308.379121 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::cpu1.data 67447.802198 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::total 67378.090659 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.UpgradeReq.hits::cpu0.data 2 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.hits::cpu1.data 2 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.hits::total 4 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.accesses::cpu0.data 2 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.UpgradeReq.accesses::cpu1.data 2 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.UpgradeReq.accesses::total 4 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.WritebackClean.hits::writebacks 340 # number of WritebackClean hits (Count)
|
|
system.l2.WritebackClean.hits::total 340 # number of WritebackClean hits (Count)
|
|
system.l2.WritebackClean.accesses::writebacks 340 # number of WritebackClean accesses(hits+misses) (Count)
|
|
system.l2.WritebackClean.accesses::total 340 # number of WritebackClean accesses(hits+misses) (Count)
|
|
system.l2.WritebackDirty.hits::writebacks 4967692 # number of WritebackDirty hits (Count)
|
|
system.l2.WritebackDirty.hits::total 4967692 # number of WritebackDirty hits (Count)
|
|
system.l2.WritebackDirty.accesses::writebacks 4967692 # number of WritebackDirty accesses(hits+misses) (Count)
|
|
system.l2.WritebackDirty.accesses::total 4967692 # number of WritebackDirty accesses(hits+misses) (Count)
|
|
system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.l2.tags.tagsInUse 16361.188106 # Average ticks per tags in use ((Tick/Count))
|
|
system.l2.tags.totalRefs 9939766 # Total number of references to valid blocks. (Count)
|
|
system.l2.tags.sampledRefs 4970727 # Sample count of references to valid blocks. (Count)
|
|
system.l2.tags.avgRefs 1.999660 # Average number of references to valid blocks. ((Count/Count))
|
|
system.l2.tags.warmupTick 77000 # The tick when the warmup percentage was hit. (Tick)
|
|
system.l2.tags.occupancies::writebacks 0.012075 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu0.inst 1.481976 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu0.data 8179.194047 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu1.inst 1.442971 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu1.data 8179.057038 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.avgOccs::writebacks 0.000001 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu0.inst 0.000090 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu0.data 0.499218 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu1.inst 0.000088 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu1.data 0.499210 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::total 0.998608 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.occupanciesTaskId::1024 16384 # Occupied blocks per task id (Count)
|
|
system.l2.tags.ageTaskId_1024::0 220 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::1 1979 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::2 14185 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.l2.tags.tagAccesses 84488871 # Number of tag accesses (Count)
|
|
system.l2.tags.dataAccesses 84488871 # Number of data accesses (Count)
|
|
system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.mem_ctrls.avgPriority_writebacks::samples 4951770.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu0.inst::samples 566.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu0.data::samples 2484817.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu1.inst::samples 566.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu1.data::samples 2484775.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (Second)
|
|
system.mem_ctrls.priorityMaxLatency 0.000369490500 # per QoS priority maximum request to response latency (Second)
|
|
system.mem_ctrls.numReadWriteTurnArounds 309481 # Number of turnarounds from READ to WRITE (Count)
|
|
system.mem_ctrls.numWriteReadTurnArounds 309481 # Number of turnarounds from WRITE to READ (Count)
|
|
system.mem_ctrls.numStayReadState 14023440 # Number of times bus staying in READ state (Count)
|
|
system.mem_ctrls.numStayWriteState 4652213 # Number of times bus staying in WRITE state (Count)
|
|
system.mem_ctrls.readReqs 4970724 # Number of read requests accepted (Count)
|
|
system.mem_ctrls.writeReqs 4951770 # Number of write requests accepted (Count)
|
|
system.mem_ctrls.readBursts 4970724 # Number of controller read bursts, including those serviced by the write queue (Count)
|
|
system.mem_ctrls.writeBursts 4951770 # Number of controller write bursts, including those merged in the write queue (Count)
|
|
system.mem_ctrls.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
|
|
system.mem_ctrls.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
|
|
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
|
|
system.mem_ctrls.avgRdQLen 1.67 # Average read queue length when enqueuing ((Count/Tick))
|
|
system.mem_ctrls.avgWrQLen 26.64 # Average write queue length when enqueuing ((Count/Tick))
|
|
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry (Count)
|
|
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry (Count)
|
|
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::6 4970724 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::6 4951770 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.rdQLenPdf::0 3346261 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::1 1623967 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::2 269 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::3 134 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::4 58 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::5 22 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::6 12 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::16 9 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::17 7188 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::18 308364 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::19 311072 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::20 309484 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::21 309480 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::22 316708 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::23 343389 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::24 324527 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::25 349738 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::26 311749 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::27 309488 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::28 326546 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::29 457297 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::30 313439 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::31 342659 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::32 309482 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::33 1135 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdPerTurnAround::samples 309481 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::mean 16.061448 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::gmean 16.000126 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::stdev 28.881700 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::0-511 309478 100.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::15872-16383 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::total 309481 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.wrPerTurnAround::samples 309481 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::mean 16.000149 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::gmean 16.000137 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::stdev 0.020808 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::16 309465 99.99% 99.99% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::18 2 0.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::19 14 0.00% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::total 309481 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
|
|
system.mem_ctrls.bytesReadSys 318126336 # Total read bytes from the system interface side (Byte)
|
|
system.mem_ctrls.bytesWrittenSys 316913280 # Total written bytes from the system interface side (Byte)
|
|
system.mem_ctrls.avgRdBWSys 1388155111.66331744 # Average system read bandwidth in Byte/s ((Byte/Second))
|
|
system.mem_ctrls.avgWrBWSys 1382861900.45576167 # Average system write bandwidth in Byte/s ((Byte/Second))
|
|
system.mem_ctrls.totGap 229172020500 # Total gap between requests (Tick)
|
|
system.mem_ctrls.avgGap 23096.21 # Average gap between requests ((Tick/Count))
|
|
system.mem_ctrls.requestorReadBytes::cpu0.inst 36224 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu0.data 159028288 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu1.inst 36224 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu1.data 159025600 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorWriteBytes::writebacks 316911488 # Per-requestor bytes write to memory (Byte)
|
|
system.mem_ctrls.requestorReadRate::cpu0.inst 158064.658830672881 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu0.data 693925355.762643218040 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu1.inst 158064.658830672881 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu1.data 693913626.583012700081 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorWriteRate::writebacks 1382854081.002674579620 # Per-requestor bytes write to memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadAccesses::cpu0.inst 566 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu0.data 2484817 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu1.inst 566 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu1.data 2484775 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorWriteAccesses::writebacks 4951770 # Per-requestor write serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu0.inst 17796500 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu0.data 93911930000 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu1.inst 17979000 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu1.data 93928975000 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorWriteTotalLat::writebacks 5780527683750 # Per-requestor write total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadAvgLat::cpu0.inst 31442.58 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu0.data 37794.30 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu1.inst 31765.02 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu1.data 37801.80 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorWriteAvgLat::writebacks 1167365.95 # Per-requestor write average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.dram.bytesRead::cpu0.inst 36224 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu0.data 159028288 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu1.inst 36224 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu1.data 159025600 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::total 318126336 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::cpu0.inst 36224 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::cpu1.inst 36224 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::total 72448 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesWritten::writebacks 316913280 # Number of bytes written to this memory (Byte)
|
|
system.mem_ctrls.dram.bytesWritten::total 316913280 # Number of bytes written to this memory (Byte)
|
|
system.mem_ctrls.dram.numReads::cpu0.inst 566 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu0.data 2484817 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu1.inst 566 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu1.data 2484775 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::total 4970724 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numWrites::writebacks 4951770 # Number of write requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numWrites::total 4951770 # Number of write requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.bwRead::cpu0.inst 158065 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu0.data 693925356 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu1.inst 158065 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu1.data 693913627 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::total 1388155112 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::cpu0.inst 158065 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::cpu1.inst 158065 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::total 316129 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwWrite::writebacks 1382861900 # Write bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwWrite::total 1382861900 # Write bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::writebacks 1382861900 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu0.inst 158065 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu0.data 693925356 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu1.inst 158065 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu1.data 693913627 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::total 2771017012 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.readBursts 4970724 # Number of DRAM read bursts (Count)
|
|
system.mem_ctrls.dram.writeBursts 4951742 # Number of DRAM write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::0 310736 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::1 310723 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::2 310573 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::3 310478 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::4 310573 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::5 310544 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::6 310509 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::7 310662 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::8 310787 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::9 310711 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::10 310730 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::11 310732 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::12 310619 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::13 310695 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::14 310855 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::15 310797 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::0 309506 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::1 309503 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::2 309425 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::3 309387 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::4 309421 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::5 309436 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::6 309434 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::7 309504 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::8 309524 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::9 309516 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::10 309504 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::11 309504 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::12 309504 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::13 309513 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::14 309509 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::15 309552 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.totQLat 94675605500 # Total ticks spent queuing (Tick)
|
|
system.mem_ctrls.dram.totBusLat 24853620000 # Total ticks spent in databus transfers (Tick)
|
|
system.mem_ctrls.dram.totMemAccLat 187876680500 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
|
|
system.mem_ctrls.dram.avgQLat 19046.64 # Average queueing delay per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.avgBusLat 5000.00 # Average bus latency per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.avgMemAccLat 37796.64 # Average memory access latency per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.readRowHits 4563071 # Number of row buffer hits during reads (Count)
|
|
system.mem_ctrls.dram.writeRowHits 4597794 # Number of row buffer hits during writes (Count)
|
|
system.mem_ctrls.dram.readRowHitRate 91.80 # Row buffer hit rate for reads (Ratio)
|
|
system.mem_ctrls.dram.writeRowHitRate 92.85 # Row buffer hit rate for writes (Ratio)
|
|
system.mem_ctrls.dram.bytesPerActivate::samples 761599 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::mean 833.821179 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::gmean 724.817096 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::stdev 299.562672 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::0-127 26080 3.42% 3.42% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::128-255 22354 2.94% 6.36% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::256-383 48459 6.36% 12.72% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::384-511 23422 3.08% 15.80% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::512-639 31301 4.11% 19.91% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::640-767 41147 5.40% 25.31% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::768-895 64136 8.42% 33.73% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::896-1023 32312 4.24% 37.97% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::1024-1151 472388 62.03% 100.00% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::total 761599 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesRead 318126336 # Total bytes read (Byte)
|
|
system.mem_ctrls.dram.bytesWritten 316911488 # Total bytes written (Byte)
|
|
system.mem_ctrls.dram.avgRdBW 1388.155112 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
|
|
system.mem_ctrls.dram.avgWrBW 1382.854081 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
|
|
system.mem_ctrls.dram.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
|
|
system.mem_ctrls.dram.busUtil 21.65 # Data bus utilization in percentage (Ratio)
|
|
system.mem_ctrls.dram.busUtilRead 10.84 # Data bus utilization in percentage for reads (Ratio)
|
|
system.mem_ctrls.dram.busUtilWrite 10.80 # Data bus utilization in percentage for writes (Ratio)
|
|
system.mem_ctrls.dram.pageHitRate 92.32 # Row buffer hit rate, read and write combined (Ratio)
|
|
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.mem_ctrls.dram.rank0.actEnergy 2718483600 # Energy for activate commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.preEnergy 1444900710 # Energy for precharge commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.readEnergy 17741457720 # Energy for read commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.writeEnergy 12922715520 # Energy for write commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.refreshEnergy 18090084480.000004 # Energy for refresh commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.actBackEnergy 60251240670 # Energy for active background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.preBackEnergy 37264176000 # Energy for precharge background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.totalEnergy 150433058700 # Total energy per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.averagePower 656.419780 # Core power per rank (mW) (Watt)
|
|
system.mem_ctrls.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE 95185474750 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::REF 7652320000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::ACT 126334243250 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.actEnergy 2719347540 # Energy for activate commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.preEnergy 1445367495 # Energy for precharge commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.readEnergy 17749511640 # Energy for read commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.writeEnergy 12925377720 # Energy for write commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.refreshEnergy 18090084480.000004 # Energy for refresh commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.actBackEnergy 60283523190 # Energy for active background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.preBackEnergy 37236990720 # Energy for precharge background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.totalEnergy 150450202785 # Total energy per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.averagePower 656.494589 # Core power per rank (mW) (Watt)
|
|
system.mem_ctrls.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE 95112187000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::REF 7652320000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::ACT 126407531000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.membus.transDist::ReadResp 2588 # Transaction distribution (Count)
|
|
system.membus.transDist::WritebackDirty 4951770 # Transaction distribution (Count)
|
|
system.membus.transDist::CleanEvict 1242 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadExReq 4968136 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadExResp 4968135 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadSharedReq 2588 # Transaction distribution (Count)
|
|
system.membus.pktCount_system.l2.mem_side_port::system.mem_ctrls.port 14894459 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktCount_system.l2.mem_side_port::total 14894459 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktCount::total 14894459 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktSize_system.l2.mem_side_port::system.mem_ctrls.port 635039552 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.pktSize_system.l2.mem_side_port::total 635039552 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.pktSize::total 635039552 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.snoops 0 # Total snoops (Count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (Byte)
|
|
system.membus.snoopFanout::samples 4970724 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::0 4970724 100.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::total 4970724 # Request fanout histogram (Count)
|
|
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.membus.reqLayer4.occupancy 29731568500 # Layer occupancy (ticks) (Tick)
|
|
system.membus.reqLayer4.utilization 0.1 # Layer utilization (Ratio)
|
|
system.membus.respLayer1.occupancy 25819291500 # Layer occupancy (ticks) (Tick)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (Ratio)
|
|
system.membus.snoop_filter.totRequests 9923736 # Total number of requests made to the snoop filter. (Count)
|
|
system.membus.snoop_filter.hitSingleRequests 4953012 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
|
|
system.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.tol2bus.transDist::ReadResp 2656 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::WritebackDirty 9919462 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::WritebackClean 340 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::CleanEvict 3503 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::UpgradeReq 4 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::UpgradeResp 4 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadExReq 4968150 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadExResp 4968148 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadCleanReq 1158 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadSharedReq 1498 # Transaction distribution (Count)
|
|
system.tol2bus.pktCount_system.cpu0.icache.mem_side_port::system.l2.cpu_side_port 1326 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu0.dcache.mem_side_port::system.l2.cpu_side_port 7454022 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu1.icache.mem_side_port::system.l2.cpu_side_port 1326 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu1.dcache.mem_side_port::system.l2.cpu_side_port 7453902 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount::total 14910576 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktSize_system.cpu0.icache.mem_side_port::system.l2.cpu_side_port 47808 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu0.dcache.mem_side_port::system.l2.cpu_side_port 317998272 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu1.icache.mem_side_port::system.l2.cpu_side_port 47808 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu1.dcache.mem_side_port::system.l2.cpu_side_port 317991360 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize::total 636085248 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.snoops 4954347 # Total snoops (Count)
|
|
system.tol2bus.snoopTraffic 316913536 # Total snoop traffic (Byte)
|
|
system.tol2bus.snoopFanout::samples 9925153 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::mean 0.000136 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::stdev 0.011658 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::0 9923810 99.99% 99.99% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::1 1341 0.01% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::2 2 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::5 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::6 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::7 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::8 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::max_value 2 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::total 9925153 # Request fanout histogram (Count)
|
|
system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 229172038000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.tol2bus.reqLayer0.occupancy 9937918000 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer0.occupancy 868500 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer1.occupancy 3727265500 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer4.occupancy 868999 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer4.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer5.occupancy 3727205500 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer5.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.snoop_filter.totRequests 9939772 # Total number of requests made to the snoop filter. (Count)
|
|
system.tol2bus.snoop_filter.hitSingleRequests 4968964 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
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system.tol2bus.snoop_filter.hitMultiRequests 8 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
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system.tol2bus.snoop_filter.totSnoops 1333 # Total number of snoops made to the snoop filter. (Count)
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system.tol2bus.snoop_filter.hitSingleSnoops 1331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
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system.tol2bus.snoop_filter.hitMultiSnoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
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system.voltage_domain.voltage 1 # Voltage in Volts (Volt)
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system.workload.inst.arm 0 # number of arm instructions executed (Count)
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system.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
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---------- End Simulation Statistics ----------
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