4434 lines
573 KiB
Plaintext
4434 lines
573 KiB
Plaintext
|
|
---------- Begin Simulation Statistics ----------
|
|
simSeconds 0.223206 # Number of seconds simulated (Second)
|
|
simTicks 223205548000 # Number of ticks simulated (Tick)
|
|
finalTick 223205548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
|
|
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
|
|
hostSeconds 624.39 # Real time elapsed on the host (Second)
|
|
hostTickRate 357479923 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
|
|
hostMemory 838044 # Number of bytes of host memory used (Byte)
|
|
simInsts 40491091 # Number of instructions simulated (Count)
|
|
simOps 56064193 # Number of ops (including micro ops) simulated (Count)
|
|
hostInstRate 64849 # Simulator instruction rate (inst/s) ((Count/Second))
|
|
hostOpRate 89791 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
|
|
system.clk_domain.clock 1000 # Clock period in ticks (Tick)
|
|
system.cpu0.numCycles 446411097 # Number of cpu cycles simulated (Cycle)
|
|
system.cpu0.cpi 22.320579 # CPI: cycles per instruction (core level) ((Cycle/Count))
|
|
system.cpu0.ipc 0.044802 # IPC: instructions per cycle (core level) ((Count/Cycle))
|
|
system.cpu0.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
|
|
system.cpu0.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
|
|
system.cpu0.instsAdded 30460239 # Number of instructions added to the IQ (excludes non-spec) (Count)
|
|
system.cpu0.nonSpecInstsAdded 94 # Number of non-speculative instructions added to the IQ (Count)
|
|
system.cpu0.instsIssued 30454024 # Number of instructions issued (Count)
|
|
system.cpu0.squashedInstsIssued 88 # Number of squashed instructions issued (Count)
|
|
system.cpu0.squashedInstsExamined 2904137 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
|
|
system.cpu0.squashedOperandsExamined 1084249 # Number of squashed operands that are examined and possibly removed from graph (Count)
|
|
system.cpu0.squashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed (Count)
|
|
system.cpu0.numIssuedDist::samples 446356745 # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::mean 0.068228 # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::stdev 0.463449 # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::0 434785860 97.41% 97.41% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::1 3246826 0.73% 98.14% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::2 1041684 0.23% 98.37% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::3 4632536 1.04% 99.41% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::4 2280891 0.51% 99.92% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::5 236060 0.05% 99.97% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::6 26419 0.01% 99.98% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::7 87908 0.02% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::8 18561 0.00% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
|
|
system.cpu0.numIssuedDist::total 446356745 # Number of insts issued each cycle (Count)
|
|
system.cpu0.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::IntAlu 24583 99.55% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::IntMult 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::IntDiv 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::FloatAdd 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::FloatCmp 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::FloatCvt 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::FloatMult 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::FloatMultAcc 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::FloatDiv 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::FloatMisc 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::FloatSqrt 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdAdd 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdAddAcc 0 0.00% 99.55% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdAlu 26 0.11% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdCvt 1 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdMisc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdMult 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdMatMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdShift 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdShiftAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdDiv 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdSqrt 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatAdd 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatAlu 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatCvt 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatDiv 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatMisc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatMult 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatMatMultAcc 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatSqrt 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdReduceAdd 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdReduceAlu 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdReduceCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatReduceAdd 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdFloatReduceCmp 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdAes 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdAesMix 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdSha1Hash 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdSha1Hash2 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdSha256Hash 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdSha256Hash2 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdShaSigma2 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdShaSigma3 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::SimdPredAlu 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::Matrix 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::MatrixMov 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::MatrixOP 0 0.00% 99.66% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::MemRead 47 0.19% 99.85% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::MemWrite 27 0.11% 99.96% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::FloatMemRead 1 0.00% 99.96% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::FloatMemWrite 9 0.04% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorIntegerArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorFloatArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorFloatConvert 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorIntegerReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorFloatReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorMisc 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorIntegerExtension 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statFuBusy::VectorConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu0.statIssuedInstType_0::No_OpClass 468 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::IntAlu 22182649 72.84% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::IntMult 46 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::IntDiv 76 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatAdd 168 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdAdd 10 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdAddAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdAlu 303 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdCmp 4 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdCvt 84 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdMisc 257 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdShift 7 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdShiftAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdReduceAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdAes 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdAesMix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdSha1Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdSha256Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdShaSigma2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdShaSigma3 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::SimdPredAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::Matrix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::MatrixMov 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::MatrixOP 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::MemRead 2766362 9.08% 81.93% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::MemWrite 5502841 18.07% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatMemRead 167 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::FloatMemWrite 582 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.statIssuedInstType_0::total 30454024 # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu0.issueRate 0.068220 # Inst issue rate ((Count/Cycle))
|
|
system.cpu0.fuBusy 24694 # FU busy when requested (Count)
|
|
system.cpu0.fuBusyRate 0.000811 # FU busy rate (busy events/executed inst) ((Count/Count))
|
|
system.cpu0.intInstQueueReads 507286024 # Number of integer instruction queue reads (Count)
|
|
system.cpu0.intInstQueueWrites 33362398 # Number of integer instruction queue writes (Count)
|
|
system.cpu0.intInstQueueWakeupAccesses 30188679 # Number of integer instruction queue wakeup accesses (Count)
|
|
system.cpu0.fpInstQueueReads 3551 # Number of floating instruction queue reads (Count)
|
|
system.cpu0.fpInstQueueWrites 2127 # Number of floating instruction queue writes (Count)
|
|
system.cpu0.fpInstQueueWakeupAccesses 1720 # Number of floating instruction queue wakeup accesses (Count)
|
|
system.cpu0.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
|
|
system.cpu0.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
|
|
system.cpu0.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
|
|
system.cpu0.intAluAccesses 30476456 # Number of integer alu accesses (Count)
|
|
system.cpu0.fpAluAccesses 1794 # Number of floating point alu accesses (Count)
|
|
system.cpu0.vecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu0.numSquashedInsts 929 # Number of squashed instructions skipped in execute (Count)
|
|
system.cpu0.numSwp 0 # Number of swp insts executed (Count)
|
|
system.cpu0.timesIdled 367 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
|
|
system.cpu0.idleCycles 54352 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
|
|
system.cpu0.MemDepUnit__0.insertedLoads 2767120 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__0.insertedStores 5503879 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__0.conflictingLoads 1787938 # Number of conflicting loads. (Count)
|
|
system.cpu0.MemDepUnit__0.conflictingStores 230138 # Number of conflicting stores. (Count)
|
|
system.cpu0.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu0.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu0.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu0.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu0.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu0.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu0.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu0.branchPred.lookups 2864422 # Number of BP lookups (Count)
|
|
system.cpu0.branchPred.condPredicted 2853188 # Number of conditional branches predicted (Count)
|
|
system.cpu0.branchPred.condIncorrect 771 # Number of conditional branches incorrect (Count)
|
|
system.cpu0.branchPred.BTBLookups 2838748 # Number of BTB lookups (Count)
|
|
system.cpu0.branchPred.BTBUpdates 641 # Number of BTB updates (Count)
|
|
system.cpu0.branchPred.BTBHits 2838333 # Number of BTB hits (Count)
|
|
system.cpu0.branchPred.BTBHitRatio 0.999854 # BTB Hit Ratio (Ratio)
|
|
system.cpu0.branchPred.RASUsed 2585 # Number of times the RAS was used to get a target. (Count)
|
|
system.cpu0.branchPred.RASIncorrect 9 # Number of incorrect RAS predictions. (Count)
|
|
system.cpu0.branchPred.indirectLookups 2386 # Number of indirect predictor lookups. (Count)
|
|
system.cpu0.branchPred.indirectHits 2178 # Number of indirect target hits. (Count)
|
|
system.cpu0.branchPred.indirectMisses 208 # Number of indirect misses. (Count)
|
|
system.cpu0.branchPred.indirectMispredicted 63 # Number of mispredicted indirect branches. (Count)
|
|
system.cpu0.branchPred.loop_predictor.correct 2504779 # Number of times the loop predictor is the provider and the prediction is correct (Count)
|
|
system.cpu0.branchPred.loop_predictor.wrong 1876 # Number of times the loop predictor is the provider and the prediction is wrong (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProviderCorrect 1441754 # Number of times TAGE Longest Match is the provider and the prediction is correct (Count)
|
|
system.cpu0.branchPred.tage.altMatchProviderCorrect 62 # Number of times TAGE Alt Match is the provider and the prediction is correct (Count)
|
|
system.cpu0.branchPred.tage.bimodalAltMatchProviderCorrect 87 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct (Count)
|
|
system.cpu0.branchPred.tage.bimodalProviderCorrect 1064347 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProviderWrong 51 # Number of times TAGE Longest Match is the provider and the prediction is wrong (Count)
|
|
system.cpu0.branchPred.tage.altMatchProviderWrong 19 # Number of times TAGE Alt Match is the provider and the prediction is wrong (Count)
|
|
system.cpu0.branchPred.tage.bimodalAltMatchProviderWrong 30 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong (Count)
|
|
system.cpu0.branchPred.tage.bimodalProviderWrong 305 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong (Count)
|
|
system.cpu0.branchPred.tage.altMatchProviderWouldHaveHit 9 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProviderWouldHaveHit 34 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::0 0 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::1 1411 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::2 1048963 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::3 2047 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::4 388022 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::5 121 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::6 678 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::7 90 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::8 270 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::9 114 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::10 9 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::11 0 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.longestMatchProvider::12 161 # TAGE provider for longest match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::0 1052307 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::1 1149 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::2 387020 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::3 0 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::4 432 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::5 587 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::6 78 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::7 40 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::8 109 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::9 164 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::10 0 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::11 0 # TAGE provider for alt match (Count)
|
|
system.cpu0.branchPred.tage.altMatchProvider::12 0 # TAGE provider for alt match (Count)
|
|
system.cpu0.commit.commitSquashedInsts 2772838 # The number of squashed insts skipped by commit (Count)
|
|
system.cpu0.commit.commitNonSpecStalls 42 # The number of times commit has been forced to stall to communicate backwards (Count)
|
|
system.cpu0.commit.branchMispredicts 542 # The number of times a branch was mispredicted (Count)
|
|
system.cpu0.commit.numCommittedDist::samples 446009726 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::mean 0.061784 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::stdev 0.444040 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::0 435717301 97.69% 97.69% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::1 3031762 0.68% 98.37% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::2 318409 0.07% 98.44% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::3 4464704 1.00% 99.44% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::4 1961181 0.44% 99.88% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::5 493421 0.11% 99.99% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::6 317 0.00% 99.99% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::7 1275 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::8 21356 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.numCommittedDist::total 446009726 # Number of insts commited each cycle (Count)
|
|
system.cpu0.commit.amos 0 # Number of atomic instructions committed (Count)
|
|
system.cpu0.commit.membars 28 # Number of memory barriers committed (Count)
|
|
system.cpu0.commit.functionCalls 2307 # Number of function calls committed. (Count)
|
|
system.cpu0.commit.committedInstType_0::No_OpClass 250 0.00% 0.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::IntAlu 20074082 72.85% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::IntMult 41 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::IntDiv 56 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatAdd 146 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdAdd 10 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdAlu 237 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdCmp 4 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdCvt 76 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdMisc 235 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdShift 3 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdAes 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdAesMix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::Matrix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::MatrixMov 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::MatrixOP 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::MemRead 2502666 9.08% 81.93% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::MemWrite 4977751 18.06% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatMemRead 125 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu0.commit.committedInstType_0::total 27556196 # Class of committed instruction (Count)
|
|
system.cpu0.commit.commitEligibleSamples 21356 # number cycles where commit BW limit reached (Cycle)
|
|
system.cpu0.commitStats0.numInsts 19999978 # Number of instructions committed (thread level) (Count)
|
|
system.cpu0.commitStats0.numOps 27556196 # Number of ops (including micro ops) committed (thread level) (Count)
|
|
system.cpu0.commitStats0.numInstsNotNOP 19999978 # Number of instructions committed excluding NOPs or prefetches (Count)
|
|
system.cpu0.commitStats0.numOpsNotNOP 27556196 # Number of Ops (including micro ops) Simulated (Count)
|
|
system.cpu0.commitStats0.cpi 22.320579 # CPI: cycles per instruction (thread level) ((Cycle/Count))
|
|
system.cpu0.commitStats0.ipc 0.044802 # IPC: instructions per cycle (thread level) ((Count/Cycle))
|
|
system.cpu0.commitStats0.numMemRefs 7481056 # Number of memory references committed (Count)
|
|
system.cpu0.commitStats0.numFpInsts 1513 # Number of float instructions (Count)
|
|
system.cpu0.commitStats0.numIntInsts 27555058 # Number of integer instructions (Count)
|
|
system.cpu0.commitStats0.numLoadInsts 2502791 # Number of load instructions (Count)
|
|
system.cpu0.commitStats0.numStoreInsts 4978265 # Number of store instructions (Count)
|
|
system.cpu0.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
|
|
system.cpu0.commitStats0.committedInstType::No_OpClass 250 0.00% 0.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::IntAlu 20074082 72.85% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::IntMult 41 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::IntDiv 56 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatAdd 146 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdAdd 10 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdAlu 237 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdCmp 4 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdCvt 76 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdMisc 235 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdShift 3 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdAes 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::Matrix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::MatrixMov 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::MatrixOP 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::MemRead 2502666 9.08% 81.93% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::MemWrite 4977751 18.06% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatMemRead 125 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedInstType::total 27556196 # Class of committed instruction. (Count)
|
|
system.cpu0.commitStats0.committedControl::IsControl 2516673 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsDirectControl 2512213 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsIndirectControl 4460 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsCondControl 2506655 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsUncondControl 10018 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsCall 2307 # Class of control type instructions committed (Count)
|
|
system.cpu0.commitStats0.committedControl::IsReturn 2304 # Class of control type instructions committed (Count)
|
|
system.cpu0.dcache.demandHits::cpu0.data 2508120 # number of demand (read+write) hits (Count)
|
|
system.cpu0.dcache.demandHits::total 2508120 # number of demand (read+write) hits (Count)
|
|
system.cpu0.dcache.overallHits::cpu0.data 2508120 # number of overall hits (Count)
|
|
system.cpu0.dcache.overallHits::total 2508120 # number of overall hits (Count)
|
|
system.cpu0.dcache.demandMisses::cpu0.data 2485891 # number of demand (read+write) misses (Count)
|
|
system.cpu0.dcache.demandMisses::total 2485891 # number of demand (read+write) misses (Count)
|
|
system.cpu0.dcache.overallMisses::cpu0.data 2485891 # number of overall misses (Count)
|
|
system.cpu0.dcache.overallMisses::total 2485891 # number of overall misses (Count)
|
|
system.cpu0.dcache.demandMissLatency::cpu0.data 220410518500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu0.dcache.demandMissLatency::total 220410518500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu0.dcache.overallMissLatency::cpu0.data 220410518500 # number of overall miss ticks (Tick)
|
|
system.cpu0.dcache.overallMissLatency::total 220410518500 # number of overall miss ticks (Tick)
|
|
system.cpu0.dcache.demandAccesses::cpu0.data 4994011 # number of demand (read+write) accesses (Count)
|
|
system.cpu0.dcache.demandAccesses::total 4994011 # number of demand (read+write) accesses (Count)
|
|
system.cpu0.dcache.overallAccesses::cpu0.data 4994011 # number of overall (read+write) accesses (Count)
|
|
system.cpu0.dcache.overallAccesses::total 4994011 # number of overall (read+write) accesses (Count)
|
|
system.cpu0.dcache.demandMissRate::cpu0.data 0.497774 # miss rate for demand accesses (Ratio)
|
|
system.cpu0.dcache.demandMissRate::total 0.497774 # miss rate for demand accesses (Ratio)
|
|
system.cpu0.dcache.overallMissRate::cpu0.data 0.497774 # miss rate for overall accesses (Ratio)
|
|
system.cpu0.dcache.overallMissRate::total 0.497774 # miss rate for overall accesses (Ratio)
|
|
system.cpu0.dcache.demandAvgMissLatency::cpu0.data 88664.594908 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu0.dcache.demandAvgMissLatency::total 88664.594908 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu0.dcache.overallAvgMissLatency::cpu0.data 88664.594908 # average overall miss latency ((Tick/Count))
|
|
system.cpu0.dcache.overallAvgMissLatency::total 88664.594908 # average overall miss latency ((Tick/Count))
|
|
system.cpu0.dcache.blockedCycles::no_mshrs 752 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.dcache.blockedCauses::no_mshrs 9 # number of times access was blocked (Count)
|
|
system.cpu0.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu0.dcache.avgBlocked::no_mshrs 83.555556 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.dcache.writebacks::writebacks 2483623 # number of writebacks (Count)
|
|
system.cpu0.dcache.writebacks::total 2483623 # number of writebacks (Count)
|
|
system.cpu0.dcache.demandMshrHits::cpu0.data 1049 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu0.dcache.demandMshrHits::total 1049 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu0.dcache.overallMshrHits::cpu0.data 1049 # number of overall MSHR hits (Count)
|
|
system.cpu0.dcache.overallMshrHits::total 1049 # number of overall MSHR hits (Count)
|
|
system.cpu0.dcache.demandMshrMisses::cpu0.data 2484842 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu0.dcache.demandMshrMisses::total 2484842 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu0.dcache.overallMshrMisses::cpu0.data 2484842 # number of overall MSHR misses (Count)
|
|
system.cpu0.dcache.overallMshrMisses::total 2484842 # number of overall MSHR misses (Count)
|
|
system.cpu0.dcache.demandMshrMissLatency::cpu0.data 217834178500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.demandMshrMissLatency::total 217834178500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.overallMshrMissLatency::cpu0.data 217834178500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.overallMshrMissLatency::total 217834178500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.demandMshrMissRate::cpu0.data 0.497564 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu0.dcache.demandMshrMissRate::total 0.497564 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu0.dcache.overallMshrMissRate::cpu0.data 0.497564 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu0.dcache.overallMshrMissRate::total 0.497564 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu0.dcache.demandAvgMshrMissLatency::cpu0.data 87665.203059 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.demandAvgMshrMissLatency::total 87665.203059 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.overallAvgMshrMissLatency::cpu0.data 87665.203059 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.overallAvgMshrMissLatency::total 87665.203059 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.replacements 2484328 # number of replacements (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.hits::cpu0.data 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.hits::total 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.misses::cpu0.data 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.misses::total 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.missLatency::cpu0.data 96500 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu0.dcache.LockedRMWReadReq.missLatency::total 96500 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu0.dcache.LockedRMWReadReq.accesses::cpu0.data 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.accesses::total 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.missRate::cpu0.data 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu0.dcache.LockedRMWReadReq.missRate::total 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu0.dcache.LockedRMWReadReq.avgMissLatency::cpu0.data 96500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.LockedRMWReadReq.avgMissLatency::total 96500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMisses::cpu0.data 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMisses::total 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMissLatency::cpu0.data 244000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMissLatency::total 244000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMissRate::cpu0.data 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu0.dcache.LockedRMWReadReq.mshrMissRate::total 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu0.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu0.data 244000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.LockedRMWReadReq.avgMshrMissLatency::total 244000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.LockedRMWWriteReq.hits::cpu0.data 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu0.dcache.LockedRMWWriteReq.hits::total 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu0.dcache.LockedRMWWriteReq.accesses::cpu0.data 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.LockedRMWWriteReq.accesses::total 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.ReadReq.hits::cpu0.data 13994 # number of ReadReq hits (Count)
|
|
system.cpu0.dcache.ReadReq.hits::total 13994 # number of ReadReq hits (Count)
|
|
system.cpu0.dcache.ReadReq.misses::cpu0.data 1797 # number of ReadReq misses (Count)
|
|
system.cpu0.dcache.ReadReq.misses::total 1797 # number of ReadReq misses (Count)
|
|
system.cpu0.dcache.ReadReq.missLatency::cpu0.data 158911000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu0.dcache.ReadReq.missLatency::total 158911000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu0.dcache.ReadReq.accesses::cpu0.data 15791 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.ReadReq.accesses::total 15791 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.ReadReq.missRate::cpu0.data 0.113799 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.dcache.ReadReq.missRate::total 0.113799 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.dcache.ReadReq.avgMissLatency::cpu0.data 88431.274346 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.ReadReq.avgMissLatency::total 88431.274346 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.ReadReq.mshrHits::cpu0.data 1049 # number of ReadReq MSHR hits (Count)
|
|
system.cpu0.dcache.ReadReq.mshrHits::total 1049 # number of ReadReq MSHR hits (Count)
|
|
system.cpu0.dcache.ReadReq.mshrMisses::cpu0.data 748 # number of ReadReq MSHR misses (Count)
|
|
system.cpu0.dcache.ReadReq.mshrMisses::total 748 # number of ReadReq MSHR misses (Count)
|
|
system.cpu0.dcache.ReadReq.mshrMissLatency::cpu0.data 66664000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.ReadReq.mshrMissLatency::total 66664000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.ReadReq.mshrMissRate::cpu0.data 0.047369 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.dcache.ReadReq.mshrMissRate::total 0.047369 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.dcache.ReadReq.avgMshrMissLatency::cpu0.data 89122.994652 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.ReadReq.avgMshrMissLatency::total 89122.994652 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.WriteReq.hits::cpu0.data 2494126 # number of WriteReq hits (Count)
|
|
system.cpu0.dcache.WriteReq.hits::total 2494126 # number of WriteReq hits (Count)
|
|
system.cpu0.dcache.WriteReq.misses::cpu0.data 2484094 # number of WriteReq misses (Count)
|
|
system.cpu0.dcache.WriteReq.misses::total 2484094 # number of WriteReq misses (Count)
|
|
system.cpu0.dcache.WriteReq.missLatency::cpu0.data 220251607500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu0.dcache.WriteReq.missLatency::total 220251607500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu0.dcache.WriteReq.accesses::cpu0.data 4978220 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.WriteReq.accesses::total 4978220 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu0.dcache.WriteReq.missRate::cpu0.data 0.498992 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu0.dcache.WriteReq.missRate::total 0.498992 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu0.dcache.WriteReq.avgMissLatency::cpu0.data 88664.763693 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.WriteReq.avgMissLatency::total 88664.763693 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu0.dcache.WriteReq.mshrMisses::cpu0.data 2484094 # number of WriteReq MSHR misses (Count)
|
|
system.cpu0.dcache.WriteReq.mshrMisses::total 2484094 # number of WriteReq MSHR misses (Count)
|
|
system.cpu0.dcache.WriteReq.mshrMissLatency::cpu0.data 217767514500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.WriteReq.mshrMissLatency::total 217767514500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu0.dcache.WriteReq.mshrMissRate::cpu0.data 0.498992 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu0.dcache.WriteReq.mshrMissRate::total 0.498992 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu0.dcache.WriteReq.avgMshrMissLatency::cpu0.data 87664.764095 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.WriteReq.avgMshrMissLatency::total 87664.764095 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.dcache.tags.tagsInUse 511.896087 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu0.dcache.tags.totalRefs 4992989 # Total number of references to valid blocks. (Count)
|
|
system.cpu0.dcache.tags.sampledRefs 2484840 # Sample count of references to valid blocks. (Count)
|
|
system.cpu0.dcache.tags.avgRefs 2.009380 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu0.dcache.tags.warmupTick 190500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu0.dcache.tags.occupancies::cpu0.data 511.896087 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu0.dcache.tags.avgOccs::cpu0.data 0.999797 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu0.dcache.tags.avgOccs::total 0.999797 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu0.dcache.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
|
|
system.cpu0.dcache.tags.ageTaskId_1024::0 114 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu0.dcache.tags.ageTaskId_1024::1 334 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu0.dcache.tags.ageTaskId_1024::2 63 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu0.dcache.tags.ageTaskId_1024::4 1 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu0.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu0.dcache.tags.tagAccesses 12472918 # Number of tag accesses (Count)
|
|
system.cpu0.dcache.tags.dataAccesses 12472918 # Number of data accesses (Count)
|
|
system.cpu0.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.decode.idleCycles 1295482 # Number of cycles decode is idle (Cycle)
|
|
system.cpu0.decode.blockedCycles 441100212 # Number of cycles decode is blocked (Cycle)
|
|
system.cpu0.decode.runCycles 505953 # Number of cycles decode is running (Cycle)
|
|
system.cpu0.decode.unblockCycles 3438100 # Number of cycles decode is unblocking (Cycle)
|
|
system.cpu0.decode.squashCycles 16998 # Number of cycles decode is squashing (Cycle)
|
|
system.cpu0.decode.branchResolved 2772782 # Number of times decode resolved a branch (Count)
|
|
system.cpu0.decode.branchMispred 265 # Number of times decode detected a branch misprediction (Count)
|
|
system.cpu0.decode.decodedInsts 30644840 # Number of instructions handled by decode (Count)
|
|
system.cpu0.decode.squashedInsts 1175 # Number of squashed instructions handled by decode (Count)
|
|
system.cpu0.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu0.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu0.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.dtb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu0.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu0.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu0.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu0.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu0.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu0.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu0.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu0.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.executeStats0.numInsts 30453095 # Number of executed instructions (Count)
|
|
system.cpu0.executeStats0.numNop 0 # Number of nop insts executed (Count)
|
|
system.cpu0.executeStats0.numBranches 2779834 # Number of branches executed (Count)
|
|
system.cpu0.executeStats0.numLoadInsts 2766332 # Number of load instructions executed (Count)
|
|
system.cpu0.executeStats0.numStoreInsts 5503339 # Number of stores executed (Count)
|
|
system.cpu0.executeStats0.instRate 0.068218 # Inst execution rate ((Count/Cycle))
|
|
system.cpu0.executeStats0.numCCRegReads 13888083 # Number of times the CC registers were read (Count)
|
|
system.cpu0.executeStats0.numCCRegWrites 16559285 # Number of times the CC registers were written (Count)
|
|
system.cpu0.executeStats0.numFpRegReads 2115 # Number of times the floating registers were read (Count)
|
|
system.cpu0.executeStats0.numFpRegWrites 1078 # Number of times the floating registers were written (Count)
|
|
system.cpu0.executeStats0.numIntRegReads 49749875 # Number of times the integer registers were read (Count)
|
|
system.cpu0.executeStats0.numIntRegWrites 19397917 # Number of times the integer registers were written (Count)
|
|
system.cpu0.executeStats0.numMemRefs 8269671 # Number of memory refs (Count)
|
|
system.cpu0.executeStats0.numMiscRegReads 13828645 # Number of times the Misc registers were read (Count)
|
|
system.cpu0.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu0.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
|
|
system.cpu0.fetch.predictedBranches 2843096 # Number of branches that fetch has predicted taken (Count)
|
|
system.cpu0.fetch.cycles 446296123 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
|
|
system.cpu0.fetch.squashCycles 34518 # Number of cycles fetch has spent squashing (Cycle)
|
|
system.cpu0.fetch.miscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
|
|
system.cpu0.fetch.pendingTrapStallCycles 200 # Number of stall cycles due to pending traps (Cycle)
|
|
system.cpu0.fetch.cacheLines 19570 # Number of cache lines fetched (Count)
|
|
system.cpu0.fetch.icacheSquashes 420 # Number of outstanding Icache misses that were squashed (Count)
|
|
system.cpu0.fetch.nisnDist::samples 446356745 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::mean 0.070433 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::stdev 0.665914 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::0 440005258 98.58% 98.58% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::1 655792 0.15% 98.72% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::2 655116 0.15% 98.87% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::3 1538006 0.34% 99.22% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::4 316780 0.07% 99.29% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::5 311856 0.07% 99.36% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::6 313963 0.07% 99.43% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::7 331792 0.07% 99.50% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::8 2228182 0.50% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetch.nisnDist::total 446356745 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu0.fetchStats0.numInsts 22835259 # Number of instructions fetched (thread level) (Count)
|
|
system.cpu0.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
|
|
system.cpu0.fetchStats0.fetchRate 0.051153 # Number of inst fetches per cycle ((Count/Cycle))
|
|
system.cpu0.fetchStats0.numBranches 2864422 # Number of branches fetched (Count)
|
|
system.cpu0.fetchStats0.branchRate 0.006417 # Number of branch fetches per cycle (Ratio)
|
|
system.cpu0.fetchStats0.icacheStallCycles 43126 # ICache total stall cycles (Cycle)
|
|
system.cpu0.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
|
|
system.cpu0.icache.demandHits::cpu0.inst 18819 # number of demand (read+write) hits (Count)
|
|
system.cpu0.icache.demandHits::total 18819 # number of demand (read+write) hits (Count)
|
|
system.cpu0.icache.overallHits::cpu0.inst 18819 # number of overall hits (Count)
|
|
system.cpu0.icache.overallHits::total 18819 # number of overall hits (Count)
|
|
system.cpu0.icache.demandMisses::cpu0.inst 751 # number of demand (read+write) misses (Count)
|
|
system.cpu0.icache.demandMisses::total 751 # number of demand (read+write) misses (Count)
|
|
system.cpu0.icache.overallMisses::cpu0.inst 751 # number of overall misses (Count)
|
|
system.cpu0.icache.overallMisses::total 751 # number of overall misses (Count)
|
|
system.cpu0.icache.demandMissLatency::cpu0.inst 70218500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu0.icache.demandMissLatency::total 70218500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu0.icache.overallMissLatency::cpu0.inst 70218500 # number of overall miss ticks (Tick)
|
|
system.cpu0.icache.overallMissLatency::total 70218500 # number of overall miss ticks (Tick)
|
|
system.cpu0.icache.demandAccesses::cpu0.inst 19570 # number of demand (read+write) accesses (Count)
|
|
system.cpu0.icache.demandAccesses::total 19570 # number of demand (read+write) accesses (Count)
|
|
system.cpu0.icache.overallAccesses::cpu0.inst 19570 # number of overall (read+write) accesses (Count)
|
|
system.cpu0.icache.overallAccesses::total 19570 # number of overall (read+write) accesses (Count)
|
|
system.cpu0.icache.demandMissRate::cpu0.inst 0.038375 # miss rate for demand accesses (Ratio)
|
|
system.cpu0.icache.demandMissRate::total 0.038375 # miss rate for demand accesses (Ratio)
|
|
system.cpu0.icache.overallMissRate::cpu0.inst 0.038375 # miss rate for overall accesses (Ratio)
|
|
system.cpu0.icache.overallMissRate::total 0.038375 # miss rate for overall accesses (Ratio)
|
|
system.cpu0.icache.demandAvgMissLatency::cpu0.inst 93500 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu0.icache.demandAvgMissLatency::total 93500 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu0.icache.overallAvgMissLatency::cpu0.inst 93500 # average overall miss latency ((Tick/Count))
|
|
system.cpu0.icache.overallAvgMissLatency::total 93500 # average overall miss latency ((Tick/Count))
|
|
system.cpu0.icache.blockedCycles::no_mshrs 636 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.icache.blockedCauses::no_mshrs 7 # number of times access was blocked (Count)
|
|
system.cpu0.icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu0.icache.avgBlocked::no_mshrs 90.857143 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.icache.writebacks::writebacks 168 # number of writebacks (Count)
|
|
system.cpu0.icache.writebacks::total 168 # number of writebacks (Count)
|
|
system.cpu0.icache.demandMshrHits::cpu0.inst 174 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu0.icache.demandMshrHits::total 174 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu0.icache.overallMshrHits::cpu0.inst 174 # number of overall MSHR hits (Count)
|
|
system.cpu0.icache.overallMshrHits::total 174 # number of overall MSHR hits (Count)
|
|
system.cpu0.icache.demandMshrMisses::cpu0.inst 577 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu0.icache.demandMshrMisses::total 577 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu0.icache.overallMshrMisses::cpu0.inst 577 # number of overall MSHR misses (Count)
|
|
system.cpu0.icache.overallMshrMisses::total 577 # number of overall MSHR misses (Count)
|
|
system.cpu0.icache.demandMshrMissLatency::cpu0.inst 57362000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu0.icache.demandMshrMissLatency::total 57362000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu0.icache.overallMshrMissLatency::cpu0.inst 57362000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu0.icache.overallMshrMissLatency::total 57362000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu0.icache.demandMshrMissRate::cpu0.inst 0.029484 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu0.icache.demandMshrMissRate::total 0.029484 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu0.icache.overallMshrMissRate::cpu0.inst 0.029484 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu0.icache.overallMshrMissRate::total 0.029484 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu0.icache.demandAvgMshrMissLatency::cpu0.inst 99414.211438 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.demandAvgMshrMissLatency::total 99414.211438 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.overallAvgMshrMissLatency::cpu0.inst 99414.211438 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.overallAvgMshrMissLatency::total 99414.211438 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.replacements 168 # number of replacements (Count)
|
|
system.cpu0.icache.ReadReq.hits::cpu0.inst 18819 # number of ReadReq hits (Count)
|
|
system.cpu0.icache.ReadReq.hits::total 18819 # number of ReadReq hits (Count)
|
|
system.cpu0.icache.ReadReq.misses::cpu0.inst 751 # number of ReadReq misses (Count)
|
|
system.cpu0.icache.ReadReq.misses::total 751 # number of ReadReq misses (Count)
|
|
system.cpu0.icache.ReadReq.missLatency::cpu0.inst 70218500 # number of ReadReq miss ticks (Tick)
|
|
system.cpu0.icache.ReadReq.missLatency::total 70218500 # number of ReadReq miss ticks (Tick)
|
|
system.cpu0.icache.ReadReq.accesses::cpu0.inst 19570 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.icache.ReadReq.accesses::total 19570 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu0.icache.ReadReq.missRate::cpu0.inst 0.038375 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.icache.ReadReq.missRate::total 0.038375 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.icache.ReadReq.avgMissLatency::cpu0.inst 93500 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu0.icache.ReadReq.avgMissLatency::total 93500 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu0.icache.ReadReq.mshrHits::cpu0.inst 174 # number of ReadReq MSHR hits (Count)
|
|
system.cpu0.icache.ReadReq.mshrHits::total 174 # number of ReadReq MSHR hits (Count)
|
|
system.cpu0.icache.ReadReq.mshrMisses::cpu0.inst 577 # number of ReadReq MSHR misses (Count)
|
|
system.cpu0.icache.ReadReq.mshrMisses::total 577 # number of ReadReq MSHR misses (Count)
|
|
system.cpu0.icache.ReadReq.mshrMissLatency::cpu0.inst 57362000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.icache.ReadReq.mshrMissLatency::total 57362000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu0.icache.ReadReq.mshrMissRate::cpu0.inst 0.029484 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.icache.ReadReq.mshrMissRate::total 0.029484 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu0.icache.ReadReq.avgMshrMissLatency::cpu0.inst 99414.211438 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.ReadReq.avgMshrMissLatency::total 99414.211438 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu0.icache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.icache.tags.tagsInUse 406.953505 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu0.icache.tags.totalRefs 19396 # Total number of references to valid blocks. (Count)
|
|
system.cpu0.icache.tags.sampledRefs 577 # Sample count of references to valid blocks. (Count)
|
|
system.cpu0.icache.tags.avgRefs 33.615251 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu0.icache.tags.warmupTick 87500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu0.icache.tags.occupancies::cpu0.inst 406.953505 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu0.icache.tags.avgOccs::cpu0.inst 0.794831 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu0.icache.tags.avgOccs::total 0.794831 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu0.icache.tags.occupanciesTaskId::1024 407 # Occupied blocks per task id (Count)
|
|
system.cpu0.icache.tags.ageTaskId_1024::4 407 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu0.icache.tags.ratioOccsTaskId::1024 0.794922 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu0.icache.tags.tagAccesses 39717 # Number of tag accesses (Count)
|
|
system.cpu0.icache.tags.dataAccesses 39717 # Number of data accesses (Count)
|
|
system.cpu0.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
|
|
system.cpu0.iew.squashCycles 16998 # Number of cycles IEW is squashing (Cycle)
|
|
system.cpu0.iew.blockCycles 416008 # Number of cycles IEW is blocking (Cycle)
|
|
system.cpu0.iew.unblockCycles 233231147 # Number of cycles IEW is unblocking (Cycle)
|
|
system.cpu0.iew.dispatchedInsts 30460333 # Number of instructions dispatched to IQ (Count)
|
|
system.cpu0.iew.dispSquashedInsts 67 # Number of squashed instructions skipped by dispatch (Count)
|
|
system.cpu0.iew.dispLoadInsts 2767120 # Number of dispatched load instructions (Count)
|
|
system.cpu0.iew.dispStoreInsts 5503879 # Number of dispatched store instructions (Count)
|
|
system.cpu0.iew.dispNonSpecInsts 32 # Number of dispatched non-speculative instructions (Count)
|
|
system.cpu0.iew.iqFullEvents 1622 # Number of times the IQ has become full, causing a stall (Count)
|
|
system.cpu0.iew.lsqFullEvents 233245910 # Number of times the LSQ has become full, causing a stall (Count)
|
|
system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations (Count)
|
|
system.cpu0.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly (Count)
|
|
system.cpu0.iew.predictedNotTakenIncorrect 533 # Number of branches that were predicted not taken incorrectly (Count)
|
|
system.cpu0.iew.branchMispredicts 612 # Number of branch mispredicts detected at execute (Count)
|
|
system.cpu0.iew.instsToCommit 30452806 # Cumulative count of insts sent to commit (Count)
|
|
system.cpu0.iew.writebackCount 30190399 # Cumulative count of insts written-back (Count)
|
|
system.cpu0.iew.producerInst 12047112 # Number of instructions producing a value (Count)
|
|
system.cpu0.iew.consumerInst 19244423 # Number of instructions consuming a value (Count)
|
|
system.cpu0.iew.wbRate 0.067629 # Insts written-back per cycle ((Count/Cycle))
|
|
system.cpu0.iew.wbFanout 0.626005 # Average fanout of values written-back ((Count/Count))
|
|
system.cpu0.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
|
|
system.cpu0.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu0.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu0.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu0.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu0.itb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu0.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu0.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu0.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu0.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu0.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu0.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu0.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu0.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.lsq0.forwLoads 2750442 # Number of loads that had data forwarded from stores (Count)
|
|
system.cpu0.lsq0.squashedLoads 264329 # Number of loads squashed (Count)
|
|
system.cpu0.lsq0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed (Count)
|
|
system.cpu0.lsq0.memOrderViolation 58 # Number of memory ordering violations (Count)
|
|
system.cpu0.lsq0.squashedStores 525614 # Number of stores squashed (Count)
|
|
system.cpu0.lsq0.rescheduledLoads 1 # Number of loads that were rescheduled (Count)
|
|
system.cpu0.lsq0.blockedByCache 8 # Number of times an access to memory failed due to the cache being blocked (Count)
|
|
system.cpu0.lsq0.loadToUse::samples 2502791 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::mean 2.122421 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::stdev 4.900960 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::0-9 2501137 99.93% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::10-19 4 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::20-29 16 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::30-39 4 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::40-49 5 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::100-109 1 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::110-119 2 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::120-129 17 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::130-139 16 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::140-149 696 0.03% 99.96% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::150-159 93 0.00% 99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::160-169 74 0.00% 99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::170-179 76 0.00% 99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::180-189 37 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::190-199 136 0.01% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::200-209 281 0.01% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::210-219 62 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::220-229 32 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::230-239 20 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::240-249 13 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::250-259 12 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::260-269 11 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::270-279 9 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::280-289 8 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::290-299 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::overflows 27 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::max_value 892 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.lsq0.loadToUse::total 2502791 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu0.mmu.dtb.rdAccesses 2766320 # TLB accesses on read requests (Count)
|
|
system.cpu0.mmu.dtb.wrAccesses 5503339 # TLB accesses on write requests (Count)
|
|
system.cpu0.mmu.dtb.rdMisses 130 # TLB misses on read requests (Count)
|
|
system.cpu0.mmu.dtb.wrMisses 300981 # TLB misses on write requests (Count)
|
|
system.cpu0.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
|
|
system.cpu0.mmu.itb.wrAccesses 19607 # TLB accesses on write requests (Count)
|
|
system.cpu0.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
|
|
system.cpu0.mmu.itb.wrMisses 121 # TLB misses on write requests (Count)
|
|
system.cpu0.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.power_state.pwrStateResidencyTicks::ON 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu0.rename.squashCycles 16998 # Number of cycles rename is squashing (Cycle)
|
|
system.cpu0.rename.idleCycles 2278536 # Number of cycles rename is idle (Cycle)
|
|
system.cpu0.rename.blockCycles 233650963 # Number of cycles rename is blocking (Cycle)
|
|
system.cpu0.rename.serializeStallCycles 1161 # count of cycles rename stalled for serializing inst (Cycle)
|
|
system.cpu0.rename.runCycles 2944255 # Number of cycles rename is running (Cycle)
|
|
system.cpu0.rename.unblockCycles 207464832 # Number of cycles rename is unblocking (Cycle)
|
|
system.cpu0.rename.renamedInsts 30512130 # Number of instructions processed by rename (Count)
|
|
system.cpu0.rename.ROBFullEvents 29 # Number of times rename has blocked due to ROB full (Count)
|
|
system.cpu0.rename.IQFullEvents 10636 # Number of times rename has blocked due to IQ full (Count)
|
|
system.cpu0.rename.SQFullEvents 206765014 # Number of times rename has blocked due to SQ full (Count)
|
|
system.cpu0.rename.renamedOperands 63785190 # Number of destination operands rename has renamed (Count)
|
|
system.cpu0.rename.lookups 124731000 # Number of register rename lookups that rename has made (Count)
|
|
system.cpu0.rename.intLookups 49881208 # Number of integer rename lookups (Count)
|
|
system.cpu0.rename.fpLookups 2293 # Number of floating rename lookups (Count)
|
|
system.cpu0.rename.committedMaps 57521688 # Number of HB maps that are committed (Count)
|
|
system.cpu0.rename.undoneMaps 6263502 # Number of HB maps that are undone due to squashing (Count)
|
|
system.cpu0.rename.serializing 45 # count of serializing insts renamed (Count)
|
|
system.cpu0.rename.tempSerializing 45 # count of temporary serializing insts renamed (Count)
|
|
system.cpu0.rename.skidInsts 18601678 # count of insts added to the skid buffer (Count)
|
|
system.cpu0.rob.reads 476104178 # The number of ROB reads (Count)
|
|
system.cpu0.rob.writes 61005099 # The number of ROB writes (Count)
|
|
system.cpu0.thread_0.numInsts 19999978 # Number of Instructions committed (Count)
|
|
system.cpu0.thread_0.numOps 27556196 # Number of Ops committed (Count)
|
|
system.cpu0.thread_0.numMemRefs 0 # Number of Memory References (Count)
|
|
system.cpu0.workload.numSyscalls 14 # Number of system calls (Count)
|
|
system.cpu1.numCycles 446411097 # Number of cpu cycles simulated (Cycle)
|
|
system.cpu1.cpi 22.320554 # CPI: cycles per instruction (core level) ((Cycle/Count))
|
|
system.cpu1.ipc 0.044802 # IPC: instructions per cycle (core level) ((Count/Cycle))
|
|
system.cpu1.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
|
|
system.cpu1.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
|
|
system.cpu1.instsAdded 30459987 # Number of instructions added to the IQ (excludes non-spec) (Count)
|
|
system.cpu1.nonSpecInstsAdded 100 # Number of non-speculative instructions added to the IQ (Count)
|
|
system.cpu1.instsIssued 30453908 # Number of instructions issued (Count)
|
|
system.cpu1.squashedInstsIssued 92 # Number of squashed instructions issued (Count)
|
|
system.cpu1.squashedInstsExamined 2903858 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
|
|
system.cpu1.squashedOperandsExamined 1083434 # Number of squashed operands that are examined and possibly removed from graph (Count)
|
|
system.cpu1.squashedNonSpecRemoved 58 # Number of squashed non-spec instructions that were removed (Count)
|
|
system.cpu1.numIssuedDist::samples 446356407 # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::mean 0.068228 # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::stdev 0.463456 # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::0 434785618 97.41% 97.41% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::1 3248013 0.73% 98.14% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::2 1039182 0.23% 98.37% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::3 4633764 1.04% 99.41% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::4 2280884 0.51% 99.92% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::5 236040 0.05% 99.97% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::6 26413 0.01% 99.98% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::7 87919 0.02% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::8 18574 0.00% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
|
|
system.cpu1.numIssuedDist::total 446356407 # Number of insts issued each cycle (Count)
|
|
system.cpu1.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::IntAlu 24569 99.58% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::IntMult 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::IntDiv 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatAdd 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatCmp 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatCvt 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatMult 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatMultAcc 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatDiv 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatMisc 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatSqrt 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdAdd 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdAddAcc 0 0.00% 99.58% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdAlu 26 0.11% 99.68% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdCmp 0 0.00% 99.68% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdCvt 1 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdMisc 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdMult 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdMultAcc 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdMatMultAcc 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdShift 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdShiftAcc 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdDiv 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdSqrt 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatAdd 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatAlu 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatCmp 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatCvt 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatDiv 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatMisc 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatMult 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatMultAcc 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatMatMultAcc 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatSqrt 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdReduceAdd 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdReduceAlu 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdReduceCmp 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatReduceAdd 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdFloatReduceCmp 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdAes 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdAesMix 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdSha1Hash 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdSha1Hash2 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdSha256Hash 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdSha256Hash2 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdShaSigma2 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdShaSigma3 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::SimdPredAlu 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::Matrix 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::MatrixMov 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::MatrixOP 0 0.00% 99.69% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::MemRead 41 0.17% 99.85% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::MemWrite 25 0.10% 99.96% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatMemRead 1 0.00% 99.96% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::FloatMemWrite 10 0.04% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorIntegerArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorFloatArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorFloatConvert 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorIntegerReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorFloatReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorMisc 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorIntegerExtension 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statFuBusy::VectorConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu1.statIssuedInstType_0::No_OpClass 469 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::IntAlu 22182529 72.84% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::IntMult 47 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::IntDiv 84 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatAdd 166 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdAdd 10 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdAddAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdAlu 313 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdCmp 4 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdCvt 84 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdMisc 257 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdShift 7 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdShiftAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatCvt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatDiv 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatMisc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatMult 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdReduceAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdAes 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdAesMix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdSha1Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdSha256Hash 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdShaSigma2 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdShaSigma3 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::SimdPredAlu 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::Matrix 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::MatrixMov 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::MatrixOP 0 0.00% 72.84% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::MemRead 2766342 9.08% 81.93% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::MemWrite 5502857 18.07% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatMemRead 163 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::FloatMemWrite 576 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.statIssuedInstType_0::total 30453908 # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu1.issueRate 0.068219 # Inst issue rate ((Count/Cycle))
|
|
system.cpu1.fuBusy 24673 # FU busy when requested (Count)
|
|
system.cpu1.fuBusyRate 0.000810 # FU busy rate (busy events/executed inst) ((Count/Count))
|
|
system.cpu1.intInstQueueReads 507285440 # Number of integer instruction queue reads (Count)
|
|
system.cpu1.intInstQueueWrites 33361855 # Number of integer instruction queue writes (Count)
|
|
system.cpu1.intInstQueueWakeupAccesses 30188565 # Number of integer instruction queue wakeup accesses (Count)
|
|
system.cpu1.fpInstQueueReads 3548 # Number of floating instruction queue reads (Count)
|
|
system.cpu1.fpInstQueueWrites 2143 # Number of floating instruction queue writes (Count)
|
|
system.cpu1.fpInstQueueWakeupAccesses 1721 # Number of floating instruction queue wakeup accesses (Count)
|
|
system.cpu1.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
|
|
system.cpu1.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
|
|
system.cpu1.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
|
|
system.cpu1.intAluAccesses 30476319 # Number of integer alu accesses (Count)
|
|
system.cpu1.fpAluAccesses 1793 # Number of floating point alu accesses (Count)
|
|
system.cpu1.vecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu1.numSquashedInsts 931 # Number of squashed instructions skipped in execute (Count)
|
|
system.cpu1.numSwp 0 # Number of swp insts executed (Count)
|
|
system.cpu1.timesIdled 363 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
|
|
system.cpu1.idleCycles 54690 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
|
|
system.cpu1.MemDepUnit__0.insertedLoads 2767073 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__0.insertedStores 5503885 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__0.conflictingLoads 1786698 # Number of conflicting loads. (Count)
|
|
system.cpu1.MemDepUnit__0.conflictingStores 230126 # Number of conflicting stores. (Count)
|
|
system.cpu1.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu1.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu1.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu1.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu1.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu1.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu1.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu1.branchPred.lookups 2864322 # Number of BP lookups (Count)
|
|
system.cpu1.branchPred.condPredicted 2853141 # Number of conditional branches predicted (Count)
|
|
system.cpu1.branchPred.condIncorrect 763 # Number of conditional branches incorrect (Count)
|
|
system.cpu1.branchPred.BTBLookups 2838704 # Number of BTB lookups (Count)
|
|
system.cpu1.branchPred.BTBUpdates 641 # Number of BTB updates (Count)
|
|
system.cpu1.branchPred.BTBHits 2838289 # Number of BTB hits (Count)
|
|
system.cpu1.branchPred.BTBHitRatio 0.999854 # BTB Hit Ratio (Ratio)
|
|
system.cpu1.branchPred.RASUsed 2573 # Number of times the RAS was used to get a target. (Count)
|
|
system.cpu1.branchPred.RASIncorrect 9 # Number of incorrect RAS predictions. (Count)
|
|
system.cpu1.branchPred.indirectLookups 2378 # Number of indirect predictor lookups. (Count)
|
|
system.cpu1.branchPred.indirectHits 2174 # Number of indirect target hits. (Count)
|
|
system.cpu1.branchPred.indirectMisses 204 # Number of indirect misses. (Count)
|
|
system.cpu1.branchPred.indirectMispredicted 63 # Number of mispredicted indirect branches. (Count)
|
|
system.cpu1.branchPred.loop_predictor.correct 2504792 # Number of times the loop predictor is the provider and the prediction is correct (Count)
|
|
system.cpu1.branchPred.loop_predictor.wrong 1865 # Number of times the loop predictor is the provider and the prediction is wrong (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProviderCorrect 1441768 # Number of times TAGE Longest Match is the provider and the prediction is correct (Count)
|
|
system.cpu1.branchPred.tage.altMatchProviderCorrect 61 # Number of times TAGE Alt Match is the provider and the prediction is correct (Count)
|
|
system.cpu1.branchPred.tage.bimodalAltMatchProviderCorrect 90 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct (Count)
|
|
system.cpu1.branchPred.tage.bimodalProviderCorrect 1064344 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProviderWrong 45 # Number of times TAGE Longest Match is the provider and the prediction is wrong (Count)
|
|
system.cpu1.branchPred.tage.altMatchProviderWrong 18 # Number of times TAGE Alt Match is the provider and the prediction is wrong (Count)
|
|
system.cpu1.branchPred.tage.bimodalAltMatchProviderWrong 27 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong (Count)
|
|
system.cpu1.branchPred.tage.bimodalProviderWrong 304 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong (Count)
|
|
system.cpu1.branchPred.tage.altMatchProviderWouldHaveHit 5 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProviderWouldHaveHit 34 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::0 0 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::1 330 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::2 1048638 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::3 389333 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::4 2168 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::5 68 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::6 742 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::7 290 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::8 38 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::9 90 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::10 121 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::11 0 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.longestMatchProvider::12 74 # TAGE provider for longest match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::0 1052320 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::1 156 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::2 386867 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::3 1800 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::4 66 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::5 71 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::6 296 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::7 45 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::8 76 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::9 121 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::10 74 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::11 0 # TAGE provider for alt match (Count)
|
|
system.cpu1.branchPred.tage.altMatchProvider::12 0 # TAGE provider for alt match (Count)
|
|
system.cpu1.commit.commitSquashedInsts 2772543 # The number of squashed insts skipped by commit (Count)
|
|
system.cpu1.commit.commitNonSpecStalls 42 # The number of times commit has been forced to stall to communicate backwards (Count)
|
|
system.cpu1.commit.branchMispredicts 529 # The number of times a branch was mispredicted (Count)
|
|
system.cpu1.commit.numCommittedDist::samples 446009449 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::mean 0.061784 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::stdev 0.444034 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::0 435717026 97.69% 97.69% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::1 3032972 0.68% 98.37% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::2 314710 0.07% 98.44% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::3 4467182 1.00% 99.44% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::4 1962430 0.44% 99.88% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::5 492179 0.11% 99.99% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::6 325 0.00% 99.99% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::7 1275 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::8 21350 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.numCommittedDist::total 446009449 # Number of insts commited each cycle (Count)
|
|
system.cpu1.commit.amos 0 # Number of atomic instructions committed (Count)
|
|
system.cpu1.commit.membars 28 # Number of memory barriers committed (Count)
|
|
system.cpu1.commit.functionCalls 2307 # Number of function calls committed. (Count)
|
|
system.cpu1.commit.committedInstType_0::No_OpClass 250 0.00% 0.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::IntAlu 20074105 72.85% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::IntMult 41 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::IntDiv 56 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatAdd 146 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdAdd 10 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdAlu 237 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdCmp 4 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdCvt 76 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdMisc 235 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdShift 3 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdAes 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdAesMix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::Matrix 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::MatrixMov 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::MatrixOP 0 0.00% 72.85% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::MemRead 2502669 9.08% 81.93% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::MemWrite 4977757 18.06% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatMemRead 125 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu1.commit.committedInstType_0::total 27556228 # Class of committed instruction (Count)
|
|
system.cpu1.commit.commitEligibleSamples 21350 # number cycles where commit BW limit reached (Cycle)
|
|
system.cpu1.commitStats0.numInsts 20000001 # Number of instructions committed (thread level) (Count)
|
|
system.cpu1.commitStats0.numOps 27556228 # Number of ops (including micro ops) committed (thread level) (Count)
|
|
system.cpu1.commitStats0.numInstsNotNOP 20000001 # Number of instructions committed excluding NOPs or prefetches (Count)
|
|
system.cpu1.commitStats0.numOpsNotNOP 27556228 # Number of Ops (including micro ops) Simulated (Count)
|
|
system.cpu1.commitStats0.cpi 22.320554 # CPI: cycles per instruction (thread level) ((Cycle/Count))
|
|
system.cpu1.commitStats0.ipc 0.044802 # IPC: instructions per cycle (thread level) ((Count/Cycle))
|
|
system.cpu1.commitStats0.numMemRefs 7481065 # Number of memory references committed (Count)
|
|
system.cpu1.commitStats0.numFpInsts 1513 # Number of float instructions (Count)
|
|
system.cpu1.commitStats0.numIntInsts 27555090 # Number of integer instructions (Count)
|
|
system.cpu1.commitStats0.numLoadInsts 2502794 # Number of load instructions (Count)
|
|
system.cpu1.commitStats0.numStoreInsts 4978271 # Number of store instructions (Count)
|
|
system.cpu1.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
|
|
system.cpu1.commitStats0.committedInstType::No_OpClass 250 0.00% 0.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::IntAlu 20074105 72.85% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::IntMult 41 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::IntDiv 56 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatAdd 146 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdAdd 10 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdAddAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdAlu 237 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdCmp 4 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdCvt 76 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdMisc 235 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdShift 3 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatMult 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdAes 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::Matrix 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::MatrixMov 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::MatrixOP 0 0.00% 72.85% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::MemRead 2502669 9.08% 81.93% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::MemWrite 4977757 18.06% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatMemRead 125 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::FloatMemWrite 514 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedInstType::total 27556228 # Class of committed instruction. (Count)
|
|
system.cpu1.commitStats0.committedControl::IsControl 2516676 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsDirectControl 2512216 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsIndirectControl 4460 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsCondControl 2506658 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsUncondControl 10018 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsCall 2307 # Class of control type instructions committed (Count)
|
|
system.cpu1.commitStats0.committedControl::IsReturn 2304 # Class of control type instructions committed (Count)
|
|
system.cpu1.dcache.demandHits::cpu1.data 2508089 # number of demand (read+write) hits (Count)
|
|
system.cpu1.dcache.demandHits::total 2508089 # number of demand (read+write) hits (Count)
|
|
system.cpu1.dcache.overallHits::cpu1.data 2508089 # number of overall hits (Count)
|
|
system.cpu1.dcache.overallHits::total 2508089 # number of overall hits (Count)
|
|
system.cpu1.dcache.demandMisses::cpu1.data 2485887 # number of demand (read+write) misses (Count)
|
|
system.cpu1.dcache.demandMisses::total 2485887 # number of demand (read+write) misses (Count)
|
|
system.cpu1.dcache.overallMisses::cpu1.data 2485887 # number of overall misses (Count)
|
|
system.cpu1.dcache.overallMisses::total 2485887 # number of overall misses (Count)
|
|
system.cpu1.dcache.demandMissLatency::cpu1.data 220411705500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu1.dcache.demandMissLatency::total 220411705500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu1.dcache.overallMissLatency::cpu1.data 220411705500 # number of overall miss ticks (Tick)
|
|
system.cpu1.dcache.overallMissLatency::total 220411705500 # number of overall miss ticks (Tick)
|
|
system.cpu1.dcache.demandAccesses::cpu1.data 4993976 # number of demand (read+write) accesses (Count)
|
|
system.cpu1.dcache.demandAccesses::total 4993976 # number of demand (read+write) accesses (Count)
|
|
system.cpu1.dcache.overallAccesses::cpu1.data 4993976 # number of overall (read+write) accesses (Count)
|
|
system.cpu1.dcache.overallAccesses::total 4993976 # number of overall (read+write) accesses (Count)
|
|
system.cpu1.dcache.demandMissRate::cpu1.data 0.497777 # miss rate for demand accesses (Ratio)
|
|
system.cpu1.dcache.demandMissRate::total 0.497777 # miss rate for demand accesses (Ratio)
|
|
system.cpu1.dcache.overallMissRate::cpu1.data 0.497777 # miss rate for overall accesses (Ratio)
|
|
system.cpu1.dcache.overallMissRate::total 0.497777 # miss rate for overall accesses (Ratio)
|
|
system.cpu1.dcache.demandAvgMissLatency::cpu1.data 88665.215072 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu1.dcache.demandAvgMissLatency::total 88665.215072 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu1.dcache.overallAvgMissLatency::cpu1.data 88665.215072 # average overall miss latency ((Tick/Count))
|
|
system.cpu1.dcache.overallAvgMissLatency::total 88665.215072 # average overall miss latency ((Tick/Count))
|
|
system.cpu1.dcache.blockedCycles::no_mshrs 949 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.dcache.blockedCauses::no_mshrs 9 # number of times access was blocked (Count)
|
|
system.cpu1.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu1.dcache.avgBlocked::no_mshrs 105.444444 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.dcache.writebacks::writebacks 2483627 # number of writebacks (Count)
|
|
system.cpu1.dcache.writebacks::total 2483627 # number of writebacks (Count)
|
|
system.cpu1.dcache.demandMshrHits::cpu1.data 1042 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu1.dcache.demandMshrHits::total 1042 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu1.dcache.overallMshrHits::cpu1.data 1042 # number of overall MSHR hits (Count)
|
|
system.cpu1.dcache.overallMshrHits::total 1042 # number of overall MSHR hits (Count)
|
|
system.cpu1.dcache.demandMshrMisses::cpu1.data 2484845 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu1.dcache.demandMshrMisses::total 2484845 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu1.dcache.overallMshrMisses::cpu1.data 2484845 # number of overall MSHR misses (Count)
|
|
system.cpu1.dcache.overallMshrMisses::total 2484845 # number of overall MSHR misses (Count)
|
|
system.cpu1.dcache.demandMshrMissLatency::cpu1.data 217834900500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.demandMshrMissLatency::total 217834900500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.overallMshrMissLatency::cpu1.data 217834900500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.overallMshrMissLatency::total 217834900500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.demandMshrMissRate::cpu1.data 0.497568 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu1.dcache.demandMshrMissRate::total 0.497568 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu1.dcache.overallMshrMissRate::cpu1.data 0.497568 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu1.dcache.overallMshrMissRate::total 0.497568 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu1.dcache.demandAvgMshrMissLatency::cpu1.data 87665.387781 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.demandAvgMshrMissLatency::total 87665.387781 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.overallAvgMshrMissLatency::cpu1.data 87665.387781 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.overallAvgMshrMissLatency::total 87665.387781 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.replacements 2484331 # number of replacements (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.hits::cpu1.data 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.hits::total 13 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.misses::cpu1.data 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.misses::total 1 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.missLatency::cpu1.data 108500 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu1.dcache.LockedRMWReadReq.missLatency::total 108500 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu1.dcache.LockedRMWReadReq.accesses::cpu1.data 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.accesses::total 14 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.missRate::cpu1.data 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu1.dcache.LockedRMWReadReq.missRate::total 0.071429 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu1.dcache.LockedRMWReadReq.avgMissLatency::cpu1.data 108500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.LockedRMWReadReq.avgMissLatency::total 108500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMisses::cpu1.data 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMisses::total 1 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMissLatency::cpu1.data 268000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMissLatency::total 268000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMissRate::cpu1.data 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu1.dcache.LockedRMWReadReq.mshrMissRate::total 0.071429 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu1.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu1.data 268000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.LockedRMWReadReq.avgMshrMissLatency::total 268000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.LockedRMWWriteReq.hits::cpu1.data 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu1.dcache.LockedRMWWriteReq.hits::total 14 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu1.dcache.LockedRMWWriteReq.accesses::cpu1.data 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.LockedRMWWriteReq.accesses::total 14 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.ReadReq.hits::cpu1.data 13961 # number of ReadReq hits (Count)
|
|
system.cpu1.dcache.ReadReq.hits::total 13961 # number of ReadReq hits (Count)
|
|
system.cpu1.dcache.ReadReq.misses::cpu1.data 1789 # number of ReadReq misses (Count)
|
|
system.cpu1.dcache.ReadReq.misses::total 1789 # number of ReadReq misses (Count)
|
|
system.cpu1.dcache.ReadReq.missLatency::cpu1.data 159720000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu1.dcache.ReadReq.missLatency::total 159720000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu1.dcache.ReadReq.accesses::cpu1.data 15750 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.ReadReq.accesses::total 15750 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.ReadReq.missRate::cpu1.data 0.113587 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.dcache.ReadReq.missRate::total 0.113587 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.dcache.ReadReq.avgMissLatency::cpu1.data 89278.926775 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.ReadReq.avgMissLatency::total 89278.926775 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.ReadReq.mshrHits::cpu1.data 1042 # number of ReadReq MSHR hits (Count)
|
|
system.cpu1.dcache.ReadReq.mshrHits::total 1042 # number of ReadReq MSHR hits (Count)
|
|
system.cpu1.dcache.ReadReq.mshrMisses::cpu1.data 747 # number of ReadReq MSHR misses (Count)
|
|
system.cpu1.dcache.ReadReq.mshrMisses::total 747 # number of ReadReq MSHR misses (Count)
|
|
system.cpu1.dcache.ReadReq.mshrMissLatency::cpu1.data 67012000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.ReadReq.mshrMissLatency::total 67012000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.ReadReq.mshrMissRate::cpu1.data 0.047429 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.dcache.ReadReq.mshrMissRate::total 0.047429 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.dcache.ReadReq.avgMshrMissLatency::cpu1.data 89708.165997 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.ReadReq.avgMshrMissLatency::total 89708.165997 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.WriteReq.hits::cpu1.data 2494128 # number of WriteReq hits (Count)
|
|
system.cpu1.dcache.WriteReq.hits::total 2494128 # number of WriteReq hits (Count)
|
|
system.cpu1.dcache.WriteReq.misses::cpu1.data 2484098 # number of WriteReq misses (Count)
|
|
system.cpu1.dcache.WriteReq.misses::total 2484098 # number of WriteReq misses (Count)
|
|
system.cpu1.dcache.WriteReq.missLatency::cpu1.data 220251985500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu1.dcache.WriteReq.missLatency::total 220251985500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu1.dcache.WriteReq.accesses::cpu1.data 4978226 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.WriteReq.accesses::total 4978226 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu1.dcache.WriteReq.missRate::cpu1.data 0.498993 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu1.dcache.WriteReq.missRate::total 0.498993 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu1.dcache.WriteReq.avgMissLatency::cpu1.data 88664.773089 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.WriteReq.avgMissLatency::total 88664.773089 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu1.dcache.WriteReq.mshrMisses::cpu1.data 2484098 # number of WriteReq MSHR misses (Count)
|
|
system.cpu1.dcache.WriteReq.mshrMisses::total 2484098 # number of WriteReq MSHR misses (Count)
|
|
system.cpu1.dcache.WriteReq.mshrMissLatency::cpu1.data 217767888500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.WriteReq.mshrMissLatency::total 217767888500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu1.dcache.WriteReq.mshrMissRate::cpu1.data 0.498993 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu1.dcache.WriteReq.mshrMissRate::total 0.498993 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu1.dcache.WriteReq.avgMshrMissLatency::cpu1.data 87664.773491 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.WriteReq.avgMshrMissLatency::total 87664.773491 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.dcache.tags.tagsInUse 511.896078 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu1.dcache.tags.totalRefs 4992961 # Total number of references to valid blocks. (Count)
|
|
system.cpu1.dcache.tags.sampledRefs 2484843 # Sample count of references to valid blocks. (Count)
|
|
system.cpu1.dcache.tags.avgRefs 2.009367 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu1.dcache.tags.warmupTick 202500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu1.dcache.tags.occupancies::cpu1.data 511.896078 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu1.dcache.tags.avgOccs::cpu1.data 0.999797 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu1.dcache.tags.avgOccs::total 0.999797 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu1.dcache.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
|
|
system.cpu1.dcache.tags.ageTaskId_1024::0 114 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu1.dcache.tags.ageTaskId_1024::1 333 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu1.dcache.tags.ageTaskId_1024::2 64 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu1.dcache.tags.ageTaskId_1024::4 1 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu1.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu1.dcache.tags.tagAccesses 12472851 # Number of tag accesses (Count)
|
|
system.cpu1.dcache.tags.dataAccesses 12472851 # Number of data accesses (Count)
|
|
system.cpu1.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.decode.idleCycles 1295765 # Number of cycles decode is idle (Cycle)
|
|
system.cpu1.decode.blockedCycles 441099689 # Number of cycles decode is blocked (Cycle)
|
|
system.cpu1.decode.runCycles 505869 # Number of cycles decode is running (Cycle)
|
|
system.cpu1.decode.unblockCycles 3438100 # Number of cycles decode is unblocking (Cycle)
|
|
system.cpu1.decode.squashCycles 16984 # Number of cycles decode is squashing (Cycle)
|
|
system.cpu1.decode.branchResolved 2772766 # Number of times decode resolved a branch (Count)
|
|
system.cpu1.decode.branchMispred 268 # Number of times decode detected a branch misprediction (Count)
|
|
system.cpu1.decode.decodedInsts 30644489 # Number of instructions handled by decode (Count)
|
|
system.cpu1.decode.squashedInsts 1170 # Number of squashed instructions handled by decode (Count)
|
|
system.cpu1.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu1.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu1.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.dtb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu1.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu1.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu1.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu1.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu1.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu1.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu1.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu1.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.executeStats0.numInsts 30452977 # Number of executed instructions (Count)
|
|
system.cpu1.executeStats0.numNop 0 # Number of nop insts executed (Count)
|
|
system.cpu1.executeStats0.numBranches 2779812 # Number of branches executed (Count)
|
|
system.cpu1.executeStats0.numLoadInsts 2766315 # Number of load instructions executed (Count)
|
|
system.cpu1.executeStats0.numStoreInsts 5503343 # Number of stores executed (Count)
|
|
system.cpu1.executeStats0.instRate 0.068217 # Inst execution rate ((Count/Cycle))
|
|
system.cpu1.executeStats0.numCCRegReads 13888049 # Number of times the CC registers were read (Count)
|
|
system.cpu1.executeStats0.numCCRegWrites 16559359 # Number of times the CC registers were written (Count)
|
|
system.cpu1.executeStats0.numFpRegReads 2129 # Number of times the floating registers were read (Count)
|
|
system.cpu1.executeStats0.numFpRegWrites 1085 # Number of times the floating registers were written (Count)
|
|
system.cpu1.executeStats0.numIntRegReads 49749887 # Number of times the integer registers were read (Count)
|
|
system.cpu1.executeStats0.numIntRegWrites 19397844 # Number of times the integer registers were written (Count)
|
|
system.cpu1.executeStats0.numMemRefs 8269658 # Number of memory refs (Count)
|
|
system.cpu1.executeStats0.numMiscRegReads 13828541 # Number of times the Misc registers were read (Count)
|
|
system.cpu1.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu1.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
|
|
system.cpu1.fetch.predictedBranches 2843036 # Number of branches that fetch has predicted taken (Count)
|
|
system.cpu1.fetch.cycles 446295447 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
|
|
system.cpu1.fetch.squashCycles 34498 # Number of cycles fetch has spent squashing (Cycle)
|
|
system.cpu1.fetch.miscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
|
|
system.cpu1.fetch.pendingTrapStallCycles 194 # Number of stall cycles due to pending traps (Cycle)
|
|
system.cpu1.fetch.cacheLines 19464 # Number of cache lines fetched (Count)
|
|
system.cpu1.fetch.icacheSquashes 413 # Number of outstanding Icache misses that were squashed (Count)
|
|
system.cpu1.fetch.nisnDist::samples 446356407 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::mean 0.070432 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::stdev 0.665924 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::0 440005045 98.58% 98.58% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::1 655793 0.15% 98.72% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::2 655106 0.15% 98.87% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::3 1539213 0.34% 99.22% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::4 315508 0.07% 99.29% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::5 311847 0.07% 99.36% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::6 313972 0.07% 99.43% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::7 330560 0.07% 99.50% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::8 2229363 0.50% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetch.nisnDist::total 446356407 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu1.fetchStats0.numInsts 22834851 # Number of instructions fetched (thread level) (Count)
|
|
system.cpu1.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
|
|
system.cpu1.fetchStats0.fetchRate 0.051152 # Number of inst fetches per cycle ((Count/Cycle))
|
|
system.cpu1.fetchStats0.numBranches 2864322 # Number of branches fetched (Count)
|
|
system.cpu1.fetchStats0.branchRate 0.006416 # Number of branch fetches per cycle (Ratio)
|
|
system.cpu1.fetchStats0.icacheStallCycles 43482 # ICache total stall cycles (Cycle)
|
|
system.cpu1.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
|
|
system.cpu1.icache.demandHits::cpu1.inst 18709 # number of demand (read+write) hits (Count)
|
|
system.cpu1.icache.demandHits::total 18709 # number of demand (read+write) hits (Count)
|
|
system.cpu1.icache.overallHits::cpu1.inst 18709 # number of overall hits (Count)
|
|
system.cpu1.icache.overallHits::total 18709 # number of overall hits (Count)
|
|
system.cpu1.icache.demandMisses::cpu1.inst 755 # number of demand (read+write) misses (Count)
|
|
system.cpu1.icache.demandMisses::total 755 # number of demand (read+write) misses (Count)
|
|
system.cpu1.icache.overallMisses::cpu1.inst 755 # number of overall misses (Count)
|
|
system.cpu1.icache.overallMisses::total 755 # number of overall misses (Count)
|
|
system.cpu1.icache.demandMissLatency::cpu1.inst 71967500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu1.icache.demandMissLatency::total 71967500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu1.icache.overallMissLatency::cpu1.inst 71967500 # number of overall miss ticks (Tick)
|
|
system.cpu1.icache.overallMissLatency::total 71967500 # number of overall miss ticks (Tick)
|
|
system.cpu1.icache.demandAccesses::cpu1.inst 19464 # number of demand (read+write) accesses (Count)
|
|
system.cpu1.icache.demandAccesses::total 19464 # number of demand (read+write) accesses (Count)
|
|
system.cpu1.icache.overallAccesses::cpu1.inst 19464 # number of overall (read+write) accesses (Count)
|
|
system.cpu1.icache.overallAccesses::total 19464 # number of overall (read+write) accesses (Count)
|
|
system.cpu1.icache.demandMissRate::cpu1.inst 0.038790 # miss rate for demand accesses (Ratio)
|
|
system.cpu1.icache.demandMissRate::total 0.038790 # miss rate for demand accesses (Ratio)
|
|
system.cpu1.icache.overallMissRate::cpu1.inst 0.038790 # miss rate for overall accesses (Ratio)
|
|
system.cpu1.icache.overallMissRate::total 0.038790 # miss rate for overall accesses (Ratio)
|
|
system.cpu1.icache.demandAvgMissLatency::cpu1.inst 95321.192053 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu1.icache.demandAvgMissLatency::total 95321.192053 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu1.icache.overallAvgMissLatency::cpu1.inst 95321.192053 # average overall miss latency ((Tick/Count))
|
|
system.cpu1.icache.overallAvgMissLatency::total 95321.192053 # average overall miss latency ((Tick/Count))
|
|
system.cpu1.icache.blockedCycles::no_mshrs 283 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.icache.blockedCauses::no_mshrs 4 # number of times access was blocked (Count)
|
|
system.cpu1.icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu1.icache.avgBlocked::no_mshrs 70.750000 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.icache.writebacks::writebacks 169 # number of writebacks (Count)
|
|
system.cpu1.icache.writebacks::total 169 # number of writebacks (Count)
|
|
system.cpu1.icache.demandMshrHits::cpu1.inst 177 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu1.icache.demandMshrHits::total 177 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu1.icache.overallMshrHits::cpu1.inst 177 # number of overall MSHR hits (Count)
|
|
system.cpu1.icache.overallMshrHits::total 177 # number of overall MSHR hits (Count)
|
|
system.cpu1.icache.demandMshrMisses::cpu1.inst 578 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu1.icache.demandMshrMisses::total 578 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu1.icache.overallMshrMisses::cpu1.inst 578 # number of overall MSHR misses (Count)
|
|
system.cpu1.icache.overallMshrMisses::total 578 # number of overall MSHR misses (Count)
|
|
system.cpu1.icache.demandMshrMissLatency::cpu1.inst 58370500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu1.icache.demandMshrMissLatency::total 58370500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu1.icache.overallMshrMissLatency::cpu1.inst 58370500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu1.icache.overallMshrMissLatency::total 58370500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu1.icache.demandMshrMissRate::cpu1.inst 0.029696 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu1.icache.demandMshrMissRate::total 0.029696 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu1.icache.overallMshrMissRate::cpu1.inst 0.029696 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu1.icache.overallMshrMissRate::total 0.029696 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu1.icache.demandAvgMshrMissLatency::cpu1.inst 100987.024221 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.demandAvgMshrMissLatency::total 100987.024221 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.overallAvgMshrMissLatency::cpu1.inst 100987.024221 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.overallAvgMshrMissLatency::total 100987.024221 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.replacements 169 # number of replacements (Count)
|
|
system.cpu1.icache.ReadReq.hits::cpu1.inst 18709 # number of ReadReq hits (Count)
|
|
system.cpu1.icache.ReadReq.hits::total 18709 # number of ReadReq hits (Count)
|
|
system.cpu1.icache.ReadReq.misses::cpu1.inst 755 # number of ReadReq misses (Count)
|
|
system.cpu1.icache.ReadReq.misses::total 755 # number of ReadReq misses (Count)
|
|
system.cpu1.icache.ReadReq.missLatency::cpu1.inst 71967500 # number of ReadReq miss ticks (Tick)
|
|
system.cpu1.icache.ReadReq.missLatency::total 71967500 # number of ReadReq miss ticks (Tick)
|
|
system.cpu1.icache.ReadReq.accesses::cpu1.inst 19464 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.icache.ReadReq.accesses::total 19464 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu1.icache.ReadReq.missRate::cpu1.inst 0.038790 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.icache.ReadReq.missRate::total 0.038790 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.icache.ReadReq.avgMissLatency::cpu1.inst 95321.192053 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu1.icache.ReadReq.avgMissLatency::total 95321.192053 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu1.icache.ReadReq.mshrHits::cpu1.inst 177 # number of ReadReq MSHR hits (Count)
|
|
system.cpu1.icache.ReadReq.mshrHits::total 177 # number of ReadReq MSHR hits (Count)
|
|
system.cpu1.icache.ReadReq.mshrMisses::cpu1.inst 578 # number of ReadReq MSHR misses (Count)
|
|
system.cpu1.icache.ReadReq.mshrMisses::total 578 # number of ReadReq MSHR misses (Count)
|
|
system.cpu1.icache.ReadReq.mshrMissLatency::cpu1.inst 58370500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.icache.ReadReq.mshrMissLatency::total 58370500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu1.icache.ReadReq.mshrMissRate::cpu1.inst 0.029696 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.icache.ReadReq.mshrMissRate::total 0.029696 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu1.icache.ReadReq.avgMshrMissLatency::cpu1.inst 100987.024221 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.ReadReq.avgMshrMissLatency::total 100987.024221 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu1.icache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.icache.tags.tagsInUse 406.952815 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu1.icache.tags.totalRefs 19287 # Total number of references to valid blocks. (Count)
|
|
system.cpu1.icache.tags.sampledRefs 578 # Sample count of references to valid blocks. (Count)
|
|
system.cpu1.icache.tags.avgRefs 33.368512 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu1.icache.tags.warmupTick 94500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu1.icache.tags.occupancies::cpu1.inst 406.952815 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu1.icache.tags.avgOccs::cpu1.inst 0.794830 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu1.icache.tags.avgOccs::total 0.794830 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu1.icache.tags.occupanciesTaskId::1024 407 # Occupied blocks per task id (Count)
|
|
system.cpu1.icache.tags.ageTaskId_1024::4 407 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu1.icache.tags.ratioOccsTaskId::1024 0.794922 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu1.icache.tags.tagAccesses 39506 # Number of tag accesses (Count)
|
|
system.cpu1.icache.tags.dataAccesses 39506 # Number of data accesses (Count)
|
|
system.cpu1.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
|
|
system.cpu1.iew.squashCycles 16984 # Number of cycles IEW is squashing (Cycle)
|
|
system.cpu1.iew.blockCycles 415221 # Number of cycles IEW is blocking (Cycle)
|
|
system.cpu1.iew.unblockCycles 232728157 # Number of cycles IEW is unblocking (Cycle)
|
|
system.cpu1.iew.dispatchedInsts 30460087 # Number of instructions dispatched to IQ (Count)
|
|
system.cpu1.iew.dispSquashedInsts 75 # Number of squashed instructions skipped by dispatch (Count)
|
|
system.cpu1.iew.dispLoadInsts 2767073 # Number of dispatched load instructions (Count)
|
|
system.cpu1.iew.dispStoreInsts 5503885 # Number of dispatched store instructions (Count)
|
|
system.cpu1.iew.dispNonSpecInsts 34 # Number of dispatched non-speculative instructions (Count)
|
|
system.cpu1.iew.iqFullEvents 1622 # Number of times the IQ has become full, causing a stall (Count)
|
|
system.cpu1.iew.lsqFullEvents 232742914 # Number of times the LSQ has become full, causing a stall (Count)
|
|
system.cpu1.iew.memOrderViolationEvents 56 # Number of memory order violations (Count)
|
|
system.cpu1.iew.predictedTakenIncorrect 70 # Number of branches that were predicted taken incorrectly (Count)
|
|
system.cpu1.iew.predictedNotTakenIncorrect 530 # Number of branches that were predicted not taken incorrectly (Count)
|
|
system.cpu1.iew.branchMispredicts 600 # Number of branch mispredicts detected at execute (Count)
|
|
system.cpu1.iew.instsToCommit 30452694 # Cumulative count of insts sent to commit (Count)
|
|
system.cpu1.iew.writebackCount 30190286 # Cumulative count of insts written-back (Count)
|
|
system.cpu1.iew.producerInst 12050749 # Number of instructions producing a value (Count)
|
|
system.cpu1.iew.consumerInst 19250702 # Number of instructions consuming a value (Count)
|
|
system.cpu1.iew.wbRate 0.067629 # Insts written-back per cycle ((Count/Cycle))
|
|
system.cpu1.iew.wbFanout 0.625990 # Average fanout of values written-back ((Count/Count))
|
|
system.cpu1.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
|
|
system.cpu1.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu1.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu1.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu1.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu1.itb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu1.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu1.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu1.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu1.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu1.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu1.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu1.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu1.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.lsq0.forwLoads 2750464 # Number of loads that had data forwarded from stores (Count)
|
|
system.cpu1.lsq0.squashedLoads 264279 # Number of loads squashed (Count)
|
|
system.cpu1.lsq0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed (Count)
|
|
system.cpu1.lsq0.memOrderViolation 56 # Number of memory ordering violations (Count)
|
|
system.cpu1.lsq0.squashedStores 525614 # Number of stores squashed (Count)
|
|
system.cpu1.lsq0.rescheduledLoads 1 # Number of loads that were rescheduled (Count)
|
|
system.cpu1.lsq0.blockedByCache 8 # Number of times an access to memory failed due to the cache being blocked (Count)
|
|
system.cpu1.lsq0.loadToUse::samples 2502793 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::mean 2.123166 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::stdev 4.967454 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::0-9 2501138 99.93% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::10-19 4 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::20-29 15 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::30-39 4 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::40-49 5 0.00% 99.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::50-59 2 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::90-99 1 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::110-119 1 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::120-129 10 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::130-139 23 0.00% 99.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::140-149 710 0.03% 99.96% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::150-159 119 0.00% 99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::160-169 58 0.00% 99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::170-179 82 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::180-189 56 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::190-199 102 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::200-209 220 0.01% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::210-219 70 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::220-229 48 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::230-239 28 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::240-249 16 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::250-259 10 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::260-269 8 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::270-279 13 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::280-289 12 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::290-299 3 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::overflows 35 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::max_value 771 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.lsq0.loadToUse::total 2502793 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu1.mmu.dtb.rdAccesses 2766302 # TLB accesses on read requests (Count)
|
|
system.cpu1.mmu.dtb.wrAccesses 5503343 # TLB accesses on write requests (Count)
|
|
system.cpu1.mmu.dtb.rdMisses 125 # TLB misses on read requests (Count)
|
|
system.cpu1.mmu.dtb.wrMisses 300978 # TLB misses on write requests (Count)
|
|
system.cpu1.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
|
|
system.cpu1.mmu.itb.wrAccesses 19499 # TLB accesses on write requests (Count)
|
|
system.cpu1.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
|
|
system.cpu1.mmu.itb.wrMisses 119 # TLB misses on write requests (Count)
|
|
system.cpu1.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.power_state.pwrStateResidencyTicks::ON 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu1.rename.squashCycles 16984 # Number of cycles rename is squashing (Cycle)
|
|
system.cpu1.rename.idleCycles 2278807 # Number of cycles rename is idle (Cycle)
|
|
system.cpu1.rename.blockCycles 233147315 # Number of cycles rename is blocking (Cycle)
|
|
system.cpu1.rename.serializeStallCycles 1208 # count of cycles rename stalled for serializing inst (Cycle)
|
|
system.cpu1.rename.runCycles 2944178 # Number of cycles rename is running (Cycle)
|
|
system.cpu1.rename.unblockCycles 207967915 # Number of cycles rename is unblocking (Cycle)
|
|
system.cpu1.rename.renamedInsts 30511850 # Number of instructions processed by rename (Count)
|
|
system.cpu1.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full (Count)
|
|
system.cpu1.rename.IQFullEvents 10620 # Number of times rename has blocked due to IQ full (Count)
|
|
system.cpu1.rename.SQFullEvents 207269320 # Number of times rename has blocked due to SQ full (Count)
|
|
system.cpu1.rename.renamedOperands 63785140 # Number of destination operands rename has renamed (Count)
|
|
system.cpu1.rename.lookups 124730400 # Number of register rename lookups that rename has made (Count)
|
|
system.cpu1.rename.intLookups 49880949 # Number of integer rename lookups (Count)
|
|
system.cpu1.rename.fpLookups 2319 # Number of floating rename lookups (Count)
|
|
system.cpu1.rename.committedMaps 57521754 # Number of HB maps that are committed (Count)
|
|
system.cpu1.rename.undoneMaps 6263383 # Number of HB maps that are undone due to squashing (Count)
|
|
system.cpu1.rename.serializing 45 # count of serializing insts renamed (Count)
|
|
system.cpu1.rename.tempSerializing 45 # count of temporary serializing insts renamed (Count)
|
|
system.cpu1.rename.skidInsts 18596752 # count of insts added to the skid buffer (Count)
|
|
system.cpu1.rob.reads 476103644 # The number of ROB reads (Count)
|
|
system.cpu1.rob.writes 61004514 # The number of ROB writes (Count)
|
|
system.cpu1.thread_0.numInsts 20000001 # Number of Instructions committed (Count)
|
|
system.cpu1.thread_0.numOps 27556228 # Number of Ops committed (Count)
|
|
system.cpu1.thread_0.numMemRefs 0 # Number of Memory References (Count)
|
|
system.cpu1.workload.numSyscalls 14 # Number of system calls (Count)
|
|
system.cpu2.numCycles 870331 # Number of cpu cycles simulated (Cycle)
|
|
system.cpu2.cpi 2.405911 # CPI: cycles per instruction (core level) ((Cycle/Count))
|
|
system.cpu2.ipc 0.415643 # IPC: instructions per cycle (core level) ((Count/Cycle))
|
|
system.cpu2.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
|
|
system.cpu2.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
|
|
system.cpu2.instsAdded 1016251 # Number of instructions added to the IQ (excludes non-spec) (Count)
|
|
system.cpu2.nonSpecInstsAdded 366 # Number of non-speculative instructions added to the IQ (Count)
|
|
system.cpu2.instsIssued 907170 # Number of instructions issued (Count)
|
|
system.cpu2.squashedInstsIssued 1374 # Number of squashed instructions issued (Count)
|
|
system.cpu2.squashedInstsExamined 315966 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
|
|
system.cpu2.squashedOperandsExamined 589306 # Number of squashed operands that are examined and possibly removed from graph (Count)
|
|
system.cpu2.squashedNonSpecRemoved 141 # Number of squashed non-spec instructions that were removed (Count)
|
|
system.cpu2.numIssuedDist::samples 690755 # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::mean 1.313302 # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::stdev 2.200764 # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::0 454437 65.79% 65.79% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::1 38490 5.57% 71.36% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::2 40202 5.82% 77.18% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::3 36305 5.26% 82.44% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::4 32122 4.65% 87.09% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::5 28149 4.08% 91.16% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::6 30060 4.35% 95.51% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::7 18152 2.63% 98.14% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::8 12838 1.86% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
|
|
system.cpu2.numIssuedDist::total 690755 # Number of insts issued each cycle (Count)
|
|
system.cpu2.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::IntAlu 10407 69.44% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::IntMult 0 0.00% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::IntDiv 0 0.00% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::FloatAdd 0 0.00% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::FloatCmp 0 0.00% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::FloatCvt 0 0.00% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::FloatMult 0 0.00% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::FloatMultAcc 0 0.00% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::FloatDiv 0 0.00% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::FloatMisc 0 0.00% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::FloatSqrt 0 0.00% 69.44% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdAdd 2 0.01% 69.45% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdAddAcc 0 0.00% 69.45% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdAlu 114 0.76% 70.21% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdCmp 0 0.00% 70.21% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdCvt 148 0.99% 71.20% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdMisc 16 0.11% 71.30% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdMult 0 0.00% 71.30% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdMultAcc 0 0.00% 71.30% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdMatMultAcc 0 0.00% 71.30% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdShift 94 0.63% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdShiftAcc 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdDiv 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdSqrt 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatAdd 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatAlu 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatCmp 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatCvt 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatDiv 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatMisc 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatMult 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatMultAcc 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatMatMultAcc 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatSqrt 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdReduceAdd 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdReduceAlu 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdReduceCmp 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatReduceAdd 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdFloatReduceCmp 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdAes 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdAesMix 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdSha1Hash 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdSha1Hash2 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdSha256Hash 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdSha256Hash2 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdShaSigma2 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdShaSigma3 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::SimdPredAlu 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::Matrix 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::MatrixMov 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::MatrixOP 0 0.00% 71.93% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::MemRead 2824 18.84% 90.77% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::MemWrite 1111 7.41% 98.19% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::FloatMemRead 193 1.29% 99.47% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::FloatMemWrite 79 0.53% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorIntegerArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorFloatArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorFloatConvert 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorIntegerReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorFloatReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorMisc 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorIntegerExtension 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statFuBusy::VectorConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu2.statIssuedInstType_0::No_OpClass 13557 1.49% 1.49% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::IntAlu 666696 73.49% 74.99% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::IntMult 2383 0.26% 75.25% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::IntDiv 6279 0.69% 75.94% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::FloatAdd 1978 0.22% 76.16% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::FloatCmp 0 0.00% 76.16% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::FloatCvt 0 0.00% 76.16% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::FloatMult 0 0.00% 76.16% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::FloatMultAcc 0 0.00% 76.16% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::FloatDiv 0 0.00% 76.16% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::FloatMisc 0 0.00% 76.16% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::FloatSqrt 0 0.00% 76.16% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdAdd 3291 0.36% 76.52% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdAddAcc 0 0.00% 76.52% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdAlu 8784 0.97% 77.49% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdCmp 0 0.00% 77.49% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdCvt 7982 0.88% 78.37% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdMisc 4730 0.52% 78.89% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdMult 0 0.00% 78.89% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdMultAcc 0 0.00% 78.89% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 78.89% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdShift 3984 0.44% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdShiftAcc 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdDiv 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdSqrt 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatAdd 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatAlu 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatCmp 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatCvt 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatDiv 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatMisc 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatMult 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdReduceAdd 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdReduceAlu 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdReduceCmp 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdAes 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdAesMix 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdSha1Hash 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdSha256Hash 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdShaSigma2 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdShaSigma3 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::SimdPredAlu 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::Matrix 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::MatrixMov 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::MatrixOP 0 0.00% 79.33% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::MemRead 118792 13.09% 92.43% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::MemWrite 53170 5.86% 98.29% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::FloatMemRead 11852 1.31% 99.59% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::FloatMemWrite 3692 0.41% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.statIssuedInstType_0::total 907170 # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu2.issueRate 1.042328 # Inst issue rate ((Count/Cycle))
|
|
system.cpu2.fuBusy 14988 # FU busy when requested (Count)
|
|
system.cpu2.fuBusyRate 0.016522 # FU busy rate (busy events/executed inst) ((Count/Count))
|
|
system.cpu2.intInstQueueReads 2424993 # Number of integer instruction queue reads (Count)
|
|
system.cpu2.intInstQueueWrites 1242539 # Number of integer instruction queue writes (Count)
|
|
system.cpu2.intInstQueueWakeupAccesses 842031 # Number of integer instruction queue wakeup accesses (Count)
|
|
system.cpu2.fpInstQueueReads 96464 # Number of floating instruction queue reads (Count)
|
|
system.cpu2.fpInstQueueWrites 90195 # Number of floating instruction queue writes (Count)
|
|
system.cpu2.fpInstQueueWakeupAccesses 44795 # Number of floating instruction queue wakeup accesses (Count)
|
|
system.cpu2.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
|
|
system.cpu2.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
|
|
system.cpu2.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
|
|
system.cpu2.intAluAccesses 860134 # Number of integer alu accesses (Count)
|
|
system.cpu2.fpAluAccesses 48467 # Number of floating point alu accesses (Count)
|
|
system.cpu2.vecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu2.numSquashedInsts 11455 # Number of squashed instructions skipped in execute (Count)
|
|
system.cpu2.numSwp 0 # Number of swp insts executed (Count)
|
|
system.cpu2.timesIdled 1494 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
|
|
system.cpu2.idleCycles 179576 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
|
|
system.cpu2.MemDepUnit__0.insertedLoads 139792 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu2.MemDepUnit__0.insertedStores 61687 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu2.MemDepUnit__0.conflictingLoads 5125 # Number of conflicting loads. (Count)
|
|
system.cpu2.MemDepUnit__0.conflictingStores 5892 # Number of conflicting stores. (Count)
|
|
system.cpu2.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu2.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu2.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu2.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu2.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu2.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu2.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu2.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu2.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu2.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu2.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu2.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu2.branchPred.lookups 116911 # Number of BP lookups (Count)
|
|
system.cpu2.branchPred.condPredicted 96581 # Number of conditional branches predicted (Count)
|
|
system.cpu2.branchPred.condIncorrect 7226 # Number of conditional branches incorrect (Count)
|
|
system.cpu2.branchPred.BTBLookups 46686 # Number of BTB lookups (Count)
|
|
system.cpu2.branchPred.BTBUpdates 4312 # Number of BTB updates (Count)
|
|
system.cpu2.branchPred.BTBHits 45081 # Number of BTB hits (Count)
|
|
system.cpu2.branchPred.BTBHitRatio 0.965621 # BTB Hit Ratio (Ratio)
|
|
system.cpu2.branchPred.RASUsed 5385 # Number of times the RAS was used to get a target. (Count)
|
|
system.cpu2.branchPred.RASIncorrect 12 # Number of incorrect RAS predictions. (Count)
|
|
system.cpu2.branchPred.indirectLookups 4986 # Number of indirect predictor lookups. (Count)
|
|
system.cpu2.branchPred.indirectHits 1553 # Number of indirect target hits. (Count)
|
|
system.cpu2.branchPred.indirectMisses 3433 # Number of indirect misses. (Count)
|
|
system.cpu2.branchPred.indirectMispredicted 1131 # Number of mispredicted indirect branches. (Count)
|
|
system.cpu2.branchPred.loop_predictor.correct 46442 # Number of times the loop predictor is the provider and the prediction is correct (Count)
|
|
system.cpu2.branchPred.loop_predictor.wrong 14111 # Number of times the loop predictor is the provider and the prediction is wrong (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProviderCorrect 23163 # Number of times TAGE Longest Match is the provider and the prediction is correct (Count)
|
|
system.cpu2.branchPred.tage.altMatchProviderCorrect 1453 # Number of times TAGE Alt Match is the provider and the prediction is correct (Count)
|
|
system.cpu2.branchPred.tage.bimodalAltMatchProviderCorrect 470 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct (Count)
|
|
system.cpu2.branchPred.tage.bimodalProviderCorrect 31085 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProviderWrong 1889 # Number of times TAGE Longest Match is the provider and the prediction is wrong (Count)
|
|
system.cpu2.branchPred.tage.altMatchProviderWrong 654 # Number of times TAGE Alt Match is the provider and the prediction is wrong (Count)
|
|
system.cpu2.branchPred.tage.bimodalAltMatchProviderWrong 226 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong (Count)
|
|
system.cpu2.branchPred.tage.bimodalProviderWrong 1603 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong (Count)
|
|
system.cpu2.branchPred.tage.altMatchProviderWouldHaveHit 506 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProviderWouldHaveHit 551 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::0 0 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::1 6670 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::2 5787 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::3 4676 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::4 3016 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::5 3068 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::6 2898 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::7 943 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::8 71 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::9 25 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::10 2 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::11 3 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.longestMatchProvider::12 0 # TAGE provider for longest match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::0 12994 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::1 2715 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::2 2928 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::3 2926 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::4 2419 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::5 2316 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::6 825 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::7 34 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::8 1 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::9 1 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::10 0 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::11 0 # TAGE provider for alt match (Count)
|
|
system.cpu2.branchPred.tage.altMatchProvider::12 0 # TAGE provider for alt match (Count)
|
|
system.cpu2.commit.commitSquashedInsts 312467 # The number of squashed insts skipped by commit (Count)
|
|
system.cpu2.commit.commitNonSpecStalls 225 # The number of times commit has been forced to stall to communicate backwards (Count)
|
|
system.cpu2.commit.branchMispredicts 6568 # The number of times a branch was mispredicted (Count)
|
|
system.cpu2.commit.numCommittedDist::samples 646748 # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::mean 1.083345 # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::stdev 2.269610 # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::0 473166 73.16% 73.16% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::1 38190 5.90% 79.07% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::2 29445 4.55% 83.62% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::3 30103 4.65% 88.27% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::4 11932 1.84% 90.12% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::5 9470 1.46% 91.58% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::6 5979 0.92% 92.51% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::7 5394 0.83% 93.34% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::8 43069 6.66% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.numCommittedDist::total 646748 # Number of insts commited each cycle (Count)
|
|
system.cpu2.commit.amos 0 # Number of atomic instructions committed (Count)
|
|
system.cpu2.commit.membars 150 # Number of memory barriers committed (Count)
|
|
system.cpu2.commit.functionCalls 3340 # Number of function calls committed. (Count)
|
|
system.cpu2.commit.committedInstType_0::No_OpClass 6569 0.94% 0.94% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::IntAlu 523518 74.72% 75.66% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::IntMult 1993 0.28% 75.94% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::IntDiv 5747 0.82% 76.76% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::FloatAdd 1329 0.19% 76.95% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::FloatCmp 0 0.00% 76.95% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::FloatCvt 0 0.00% 76.95% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::FloatMult 0 0.00% 76.95% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::FloatMultAcc 0 0.00% 76.95% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::FloatDiv 0 0.00% 76.95% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::FloatMisc 0 0.00% 76.95% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::FloatSqrt 0 0.00% 76.95% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdAdd 2394 0.34% 77.29% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdAddAcc 0 0.00% 77.29% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdAlu 5275 0.75% 78.05% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdCmp 0 0.00% 78.05% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdCvt 5238 0.75% 78.79% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdMisc 3906 0.56% 79.35% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdMult 0 0.00% 79.35% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdMultAcc 0 0.00% 79.35% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 79.35% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdShift 2062 0.29% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdShiftAcc 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdDiv 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdSqrt 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatAdd 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatAlu 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatCmp 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatCvt 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatDiv 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatMisc 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatMult 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdReduceAdd 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdReduceAlu 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdReduceCmp 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdAes 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdAesMix 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdSha1Hash 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdSha256Hash 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdShaSigma2 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdShaSigma3 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::SimdPredAlu 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::Matrix 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::MatrixMov 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::MatrixOP 0 0.00% 79.64% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::MemRead 92967 13.27% 92.91% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::MemWrite 40526 5.78% 98.70% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::FloatMemRead 6027 0.86% 99.56% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::FloatMemWrite 3100 0.44% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu2.commit.committedInstType_0::total 700651 # Class of committed instruction (Count)
|
|
system.cpu2.commit.commitEligibleSamples 43069 # number cycles where commit BW limit reached (Cycle)
|
|
system.cpu2.commitStats0.numInsts 361747 # Number of instructions committed (thread level) (Count)
|
|
system.cpu2.commitStats0.numOps 700651 # Number of ops (including micro ops) committed (thread level) (Count)
|
|
system.cpu2.commitStats0.numInstsNotNOP 361747 # Number of instructions committed excluding NOPs or prefetches (Count)
|
|
system.cpu2.commitStats0.numOpsNotNOP 700651 # Number of Ops (including micro ops) Simulated (Count)
|
|
system.cpu2.commitStats0.cpi 2.405911 # CPI: cycles per instruction (thread level) ((Cycle/Count))
|
|
system.cpu2.commitStats0.ipc 0.415643 # IPC: instructions per cycle (thread level) ((Count/Cycle))
|
|
system.cpu2.commitStats0.numMemRefs 142620 # Number of memory references committed (Count)
|
|
system.cpu2.commitStats0.numFpInsts 30579 # Number of float instructions (Count)
|
|
system.cpu2.commitStats0.numIntInsts 671364 # Number of integer instructions (Count)
|
|
system.cpu2.commitStats0.numLoadInsts 98994 # Number of load instructions (Count)
|
|
system.cpu2.commitStats0.numStoreInsts 43626 # Number of store instructions (Count)
|
|
system.cpu2.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
|
|
system.cpu2.commitStats0.committedInstType::No_OpClass 6569 0.94% 0.94% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::IntAlu 523518 74.72% 75.66% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::IntMult 1993 0.28% 75.94% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::IntDiv 5747 0.82% 76.76% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::FloatAdd 1329 0.19% 76.95% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::FloatCmp 0 0.00% 76.95% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::FloatCvt 0 0.00% 76.95% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::FloatMult 0 0.00% 76.95% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::FloatMultAcc 0 0.00% 76.95% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::FloatDiv 0 0.00% 76.95% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::FloatMisc 0 0.00% 76.95% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::FloatSqrt 0 0.00% 76.95% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdAdd 2394 0.34% 77.29% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdAddAcc 0 0.00% 77.29% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdAlu 5275 0.75% 78.05% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdCmp 0 0.00% 78.05% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdCvt 5238 0.75% 78.79% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdMisc 3906 0.56% 79.35% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdMult 0 0.00% 79.35% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdMultAcc 0 0.00% 79.35% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 79.35% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdShift 2062 0.29% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdDiv 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdSqrt 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatMult 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdAes 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdAesMix 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::SimdPredAlu 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::Matrix 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::MatrixMov 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::MatrixOP 0 0.00% 79.64% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::MemRead 92967 13.27% 92.91% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::MemWrite 40526 5.78% 98.70% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::FloatMemRead 6027 0.86% 99.56% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::FloatMemWrite 3100 0.44% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedInstType::total 700651 # Class of committed instruction. (Count)
|
|
system.cpu2.commitStats0.committedControl::IsControl 71594 # Class of control type instructions committed (Count)
|
|
system.cpu2.commitStats0.committedControl::IsDirectControl 66259 # Class of control type instructions committed (Count)
|
|
system.cpu2.commitStats0.committedControl::IsIndirectControl 4932 # Class of control type instructions committed (Count)
|
|
system.cpu2.commitStats0.committedControl::IsCondControl 60150 # Class of control type instructions committed (Count)
|
|
system.cpu2.commitStats0.committedControl::IsUncondControl 11041 # Class of control type instructions committed (Count)
|
|
system.cpu2.commitStats0.committedControl::IsCall 3340 # Class of control type instructions committed (Count)
|
|
system.cpu2.commitStats0.committedControl::IsReturn 3335 # Class of control type instructions committed (Count)
|
|
system.cpu2.dcache.demandHits::cpu2.data 148212 # number of demand (read+write) hits (Count)
|
|
system.cpu2.dcache.demandHits::total 148212 # number of demand (read+write) hits (Count)
|
|
system.cpu2.dcache.overallHits::cpu2.data 148212 # number of overall hits (Count)
|
|
system.cpu2.dcache.overallHits::total 148212 # number of overall hits (Count)
|
|
system.cpu2.dcache.demandMisses::cpu2.data 10537 # number of demand (read+write) misses (Count)
|
|
system.cpu2.dcache.demandMisses::total 10537 # number of demand (read+write) misses (Count)
|
|
system.cpu2.dcache.overallMisses::cpu2.data 10537 # number of overall misses (Count)
|
|
system.cpu2.dcache.overallMisses::total 10537 # number of overall misses (Count)
|
|
system.cpu2.dcache.demandMissLatency::cpu2.data 696612499 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu2.dcache.demandMissLatency::total 696612499 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu2.dcache.overallMissLatency::cpu2.data 696612499 # number of overall miss ticks (Tick)
|
|
system.cpu2.dcache.overallMissLatency::total 696612499 # number of overall miss ticks (Tick)
|
|
system.cpu2.dcache.demandAccesses::cpu2.data 158749 # number of demand (read+write) accesses (Count)
|
|
system.cpu2.dcache.demandAccesses::total 158749 # number of demand (read+write) accesses (Count)
|
|
system.cpu2.dcache.overallAccesses::cpu2.data 158749 # number of overall (read+write) accesses (Count)
|
|
system.cpu2.dcache.overallAccesses::total 158749 # number of overall (read+write) accesses (Count)
|
|
system.cpu2.dcache.demandMissRate::cpu2.data 0.066375 # miss rate for demand accesses (Ratio)
|
|
system.cpu2.dcache.demandMissRate::total 0.066375 # miss rate for demand accesses (Ratio)
|
|
system.cpu2.dcache.overallMissRate::cpu2.data 0.066375 # miss rate for overall accesses (Ratio)
|
|
system.cpu2.dcache.overallMissRate::total 0.066375 # miss rate for overall accesses (Ratio)
|
|
system.cpu2.dcache.demandAvgMissLatency::cpu2.data 66111.084654 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu2.dcache.demandAvgMissLatency::total 66111.084654 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu2.dcache.overallAvgMissLatency::cpu2.data 66111.084654 # average overall miss latency ((Tick/Count))
|
|
system.cpu2.dcache.overallAvgMissLatency::total 66111.084654 # average overall miss latency ((Tick/Count))
|
|
system.cpu2.dcache.blockedCycles::no_mshrs 7555 # number of cycles access was blocked (Cycle)
|
|
system.cpu2.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu2.dcache.blockedCauses::no_mshrs 166 # number of times access was blocked (Count)
|
|
system.cpu2.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu2.dcache.avgBlocked::no_mshrs 45.512048 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu2.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu2.dcache.writebacks::writebacks 1169 # number of writebacks (Count)
|
|
system.cpu2.dcache.writebacks::total 1169 # number of writebacks (Count)
|
|
system.cpu2.dcache.demandMshrHits::cpu2.data 6040 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu2.dcache.demandMshrHits::total 6040 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu2.dcache.overallMshrHits::cpu2.data 6040 # number of overall MSHR hits (Count)
|
|
system.cpu2.dcache.overallMshrHits::total 6040 # number of overall MSHR hits (Count)
|
|
system.cpu2.dcache.demandMshrMisses::cpu2.data 4497 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu2.dcache.demandMshrMisses::total 4497 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu2.dcache.overallMshrMisses::cpu2.data 4497 # number of overall MSHR misses (Count)
|
|
system.cpu2.dcache.overallMshrMisses::total 4497 # number of overall MSHR misses (Count)
|
|
system.cpu2.dcache.demandMshrMissLatency::cpu2.data 286187999 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu2.dcache.demandMshrMissLatency::total 286187999 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu2.dcache.overallMshrMissLatency::cpu2.data 286187999 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu2.dcache.overallMshrMissLatency::total 286187999 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu2.dcache.demandMshrMissRate::cpu2.data 0.028328 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu2.dcache.demandMshrMissRate::total 0.028328 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu2.dcache.overallMshrMissRate::cpu2.data 0.028328 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu2.dcache.overallMshrMissRate::total 0.028328 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu2.dcache.demandAvgMshrMissLatency::cpu2.data 63639.759618 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu2.dcache.demandAvgMshrMissLatency::total 63639.759618 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu2.dcache.overallAvgMshrMissLatency::cpu2.data 63639.759618 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu2.dcache.overallAvgMshrMissLatency::total 63639.759618 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu2.dcache.replacements 3983 # number of replacements (Count)
|
|
system.cpu2.dcache.LockedRMWReadReq.hits::cpu2.data 73 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu2.dcache.LockedRMWReadReq.hits::total 73 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu2.dcache.LockedRMWReadReq.misses::cpu2.data 2 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu2.dcache.LockedRMWReadReq.misses::total 2 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu2.dcache.LockedRMWReadReq.missLatency::cpu2.data 113000 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu2.dcache.LockedRMWReadReq.missLatency::total 113000 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu2.dcache.LockedRMWReadReq.accesses::cpu2.data 75 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu2.dcache.LockedRMWReadReq.accesses::total 75 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu2.dcache.LockedRMWReadReq.missRate::cpu2.data 0.026667 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu2.dcache.LockedRMWReadReq.missRate::total 0.026667 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu2.dcache.LockedRMWReadReq.avgMissLatency::cpu2.data 56500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu2.dcache.LockedRMWReadReq.avgMissLatency::total 56500 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu2.dcache.LockedRMWReadReq.mshrMisses::cpu2.data 2 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu2.dcache.LockedRMWReadReq.mshrMisses::total 2 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu2.dcache.LockedRMWReadReq.mshrMissLatency::cpu2.data 516000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu2.dcache.LockedRMWReadReq.mshrMissLatency::total 516000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu2.dcache.LockedRMWReadReq.mshrMissRate::cpu2.data 0.026667 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu2.dcache.LockedRMWReadReq.mshrMissRate::total 0.026667 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu2.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu2.data 258000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu2.dcache.LockedRMWReadReq.avgMshrMissLatency::total 258000 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu2.dcache.LockedRMWWriteReq.hits::cpu2.data 75 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu2.dcache.LockedRMWWriteReq.hits::total 75 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu2.dcache.LockedRMWWriteReq.accesses::cpu2.data 75 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu2.dcache.LockedRMWWriteReq.accesses::total 75 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu2.dcache.ReadReq.hits::cpu2.data 105376 # number of ReadReq hits (Count)
|
|
system.cpu2.dcache.ReadReq.hits::total 105376 # number of ReadReq hits (Count)
|
|
system.cpu2.dcache.ReadReq.misses::cpu2.data 9818 # number of ReadReq misses (Count)
|
|
system.cpu2.dcache.ReadReq.misses::total 9818 # number of ReadReq misses (Count)
|
|
system.cpu2.dcache.ReadReq.missLatency::cpu2.data 636610000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu2.dcache.ReadReq.missLatency::total 636610000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu2.dcache.ReadReq.accesses::cpu2.data 115194 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu2.dcache.ReadReq.accesses::total 115194 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu2.dcache.ReadReq.missRate::cpu2.data 0.085230 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu2.dcache.ReadReq.missRate::total 0.085230 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu2.dcache.ReadReq.avgMissLatency::cpu2.data 64841.108169 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu2.dcache.ReadReq.avgMissLatency::total 64841.108169 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu2.dcache.ReadReq.mshrHits::cpu2.data 6037 # number of ReadReq MSHR hits (Count)
|
|
system.cpu2.dcache.ReadReq.mshrHits::total 6037 # number of ReadReq MSHR hits (Count)
|
|
system.cpu2.dcache.ReadReq.mshrMisses::cpu2.data 3781 # number of ReadReq MSHR misses (Count)
|
|
system.cpu2.dcache.ReadReq.mshrMisses::total 3781 # number of ReadReq MSHR misses (Count)
|
|
system.cpu2.dcache.ReadReq.mshrMissLatency::cpu2.data 226930500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu2.dcache.ReadReq.mshrMissLatency::total 226930500 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu2.dcache.ReadReq.mshrMissRate::cpu2.data 0.032823 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu2.dcache.ReadReq.mshrMissRate::total 0.032823 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu2.dcache.ReadReq.avgMshrMissLatency::cpu2.data 60018.645861 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu2.dcache.ReadReq.avgMshrMissLatency::total 60018.645861 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu2.dcache.WriteReq.hits::cpu2.data 42836 # number of WriteReq hits (Count)
|
|
system.cpu2.dcache.WriteReq.hits::total 42836 # number of WriteReq hits (Count)
|
|
system.cpu2.dcache.WriteReq.misses::cpu2.data 719 # number of WriteReq misses (Count)
|
|
system.cpu2.dcache.WriteReq.misses::total 719 # number of WriteReq misses (Count)
|
|
system.cpu2.dcache.WriteReq.missLatency::cpu2.data 60002499 # number of WriteReq miss ticks (Tick)
|
|
system.cpu2.dcache.WriteReq.missLatency::total 60002499 # number of WriteReq miss ticks (Tick)
|
|
system.cpu2.dcache.WriteReq.accesses::cpu2.data 43555 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu2.dcache.WriteReq.accesses::total 43555 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu2.dcache.WriteReq.missRate::cpu2.data 0.016508 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu2.dcache.WriteReq.missRate::total 0.016508 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu2.dcache.WriteReq.avgMissLatency::cpu2.data 83452.710709 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu2.dcache.WriteReq.avgMissLatency::total 83452.710709 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu2.dcache.WriteReq.mshrHits::cpu2.data 3 # number of WriteReq MSHR hits (Count)
|
|
system.cpu2.dcache.WriteReq.mshrHits::total 3 # number of WriteReq MSHR hits (Count)
|
|
system.cpu2.dcache.WriteReq.mshrMisses::cpu2.data 716 # number of WriteReq MSHR misses (Count)
|
|
system.cpu2.dcache.WriteReq.mshrMisses::total 716 # number of WriteReq MSHR misses (Count)
|
|
system.cpu2.dcache.WriteReq.mshrMissLatency::cpu2.data 59257499 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu2.dcache.WriteReq.mshrMissLatency::total 59257499 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu2.dcache.WriteReq.mshrMissRate::cpu2.data 0.016439 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu2.dcache.WriteReq.mshrMissRate::total 0.016439 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu2.dcache.WriteReq.avgMshrMissLatency::cpu2.data 82761.870112 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu2.dcache.WriteReq.avgMshrMissLatency::total 82761.870112 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu2.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.dcache.tags.tagsInUse 511.894769 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu2.dcache.tags.totalRefs 152859 # Total number of references to valid blocks. (Count)
|
|
system.cpu2.dcache.tags.sampledRefs 4495 # Sample count of references to valid blocks. (Count)
|
|
system.cpu2.dcache.tags.avgRefs 34.006452 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu2.dcache.tags.warmupTick 238500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu2.dcache.tags.occupancies::cpu2.data 511.894769 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu2.dcache.tags.avgOccs::cpu2.data 0.999794 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu2.dcache.tags.avgOccs::total 0.999794 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu2.dcache.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
|
|
system.cpu2.dcache.tags.ageTaskId_1024::4 512 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu2.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu2.dcache.tags.tagAccesses 322293 # Number of tag accesses (Count)
|
|
system.cpu2.dcache.tags.dataAccesses 322293 # Number of data accesses (Count)
|
|
system.cpu2.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.decode.idleCycles 135490 # Number of cycles decode is idle (Cycle)
|
|
system.cpu2.decode.blockedCycles 387566 # Number of cycles decode is blocked (Cycle)
|
|
system.cpu2.decode.runCycles 141405 # Number of cycles decode is running (Cycle)
|
|
system.cpu2.decode.unblockCycles 19359 # Number of cycles decode is unblocking (Cycle)
|
|
system.cpu2.decode.squashCycles 6935 # Number of cycles decode is squashing (Cycle)
|
|
system.cpu2.decode.branchResolved 42848 # Number of times decode resolved a branch (Count)
|
|
system.cpu2.decode.branchMispred 1203 # Number of times decode detected a branch misprediction (Count)
|
|
system.cpu2.decode.decodedInsts 1088917 # Number of instructions handled by decode (Count)
|
|
system.cpu2.decode.squashedInsts 5755 # Number of squashed instructions handled by decode (Count)
|
|
system.cpu2.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu2.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu2.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu2.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu2.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu2.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu2.dtb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu2.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu2.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu2.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu2.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu2.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu2.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu2.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu2.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.executeStats0.numInsts 895715 # Number of executed instructions (Count)
|
|
system.cpu2.executeStats0.numNop 0 # Number of nop insts executed (Count)
|
|
system.cpu2.executeStats0.numBranches 82442 # Number of branches executed (Count)
|
|
system.cpu2.executeStats0.numLoadInsts 128371 # Number of load instructions executed (Count)
|
|
system.cpu2.executeStats0.numStoreInsts 56012 # Number of stores executed (Count)
|
|
system.cpu2.executeStats0.instRate 1.029166 # Inst execution rate ((Count/Cycle))
|
|
system.cpu2.executeStats0.numCCRegReads 490782 # Number of times the CC registers were read (Count)
|
|
system.cpu2.executeStats0.numCCRegWrites 283402 # Number of times the CC registers were written (Count)
|
|
system.cpu2.executeStats0.numFpRegReads 69881 # Number of times the floating registers were read (Count)
|
|
system.cpu2.executeStats0.numFpRegWrites 38035 # Number of times the floating registers were written (Count)
|
|
system.cpu2.executeStats0.numIntRegReads 1127439 # Number of times the integer registers were read (Count)
|
|
system.cpu2.executeStats0.numIntRegWrites 655090 # Number of times the integer registers were written (Count)
|
|
system.cpu2.executeStats0.numMemRefs 184383 # Number of memory refs (Count)
|
|
system.cpu2.executeStats0.numMiscRegReads 355783 # Number of times the Misc registers were read (Count)
|
|
system.cpu2.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu2.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
|
|
system.cpu2.fetch.predictedBranches 52019 # Number of branches that fetch has predicted taken (Count)
|
|
system.cpu2.fetch.cycles 524101 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
|
|
system.cpu2.fetch.squashCycles 16238 # Number of cycles fetch has spent squashing (Cycle)
|
|
system.cpu2.fetch.miscStallCycles 610 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
|
|
system.cpu2.fetch.pendingTrapStallCycles 3937 # Number of stall cycles due to pending traps (Cycle)
|
|
system.cpu2.fetch.icacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR (Cycle)
|
|
system.cpu2.fetch.cacheLines 77361 # Number of cache lines fetched (Count)
|
|
system.cpu2.fetch.icacheSquashes 2697 # Number of outstanding Icache misses that were squashed (Count)
|
|
system.cpu2.fetch.nisnDist::samples 690755 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::mean 1.688405 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::stdev 3.037695 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::0 505641 73.20% 73.20% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::1 10430 1.51% 74.71% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::2 11578 1.68% 76.39% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::3 10597 1.53% 77.92% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::4 9452 1.37% 79.29% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::5 12924 1.87% 81.16% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::6 13551 1.96% 83.12% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::7 15493 2.24% 85.37% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::8 101089 14.63% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetch.nisnDist::total 690755 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu2.fetchStats0.numInsts 593230 # Number of instructions fetched (thread level) (Count)
|
|
system.cpu2.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
|
|
system.cpu2.fetchStats0.fetchRate 0.681614 # Number of inst fetches per cycle ((Count/Cycle))
|
|
system.cpu2.fetchStats0.numBranches 116911 # Number of branches fetched (Count)
|
|
system.cpu2.fetchStats0.branchRate 0.134329 # Number of branch fetches per cycle (Ratio)
|
|
system.cpu2.fetchStats0.icacheStallCycles 153928 # ICache total stall cycles (Cycle)
|
|
system.cpu2.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
|
|
system.cpu2.icache.demandHits::cpu2.inst 74284 # number of demand (read+write) hits (Count)
|
|
system.cpu2.icache.demandHits::total 74284 # number of demand (read+write) hits (Count)
|
|
system.cpu2.icache.overallHits::cpu2.inst 74284 # number of overall hits (Count)
|
|
system.cpu2.icache.overallHits::total 74284 # number of overall hits (Count)
|
|
system.cpu2.icache.demandMisses::cpu2.inst 3076 # number of demand (read+write) misses (Count)
|
|
system.cpu2.icache.demandMisses::total 3076 # number of demand (read+write) misses (Count)
|
|
system.cpu2.icache.overallMisses::cpu2.inst 3076 # number of overall misses (Count)
|
|
system.cpu2.icache.overallMisses::total 3076 # number of overall misses (Count)
|
|
system.cpu2.icache.demandMissLatency::cpu2.inst 230933000 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu2.icache.demandMissLatency::total 230933000 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu2.icache.overallMissLatency::cpu2.inst 230933000 # number of overall miss ticks (Tick)
|
|
system.cpu2.icache.overallMissLatency::total 230933000 # number of overall miss ticks (Tick)
|
|
system.cpu2.icache.demandAccesses::cpu2.inst 77360 # number of demand (read+write) accesses (Count)
|
|
system.cpu2.icache.demandAccesses::total 77360 # number of demand (read+write) accesses (Count)
|
|
system.cpu2.icache.overallAccesses::cpu2.inst 77360 # number of overall (read+write) accesses (Count)
|
|
system.cpu2.icache.overallAccesses::total 77360 # number of overall (read+write) accesses (Count)
|
|
system.cpu2.icache.demandMissRate::cpu2.inst 0.039762 # miss rate for demand accesses (Ratio)
|
|
system.cpu2.icache.demandMissRate::total 0.039762 # miss rate for demand accesses (Ratio)
|
|
system.cpu2.icache.overallMissRate::cpu2.inst 0.039762 # miss rate for overall accesses (Ratio)
|
|
system.cpu2.icache.overallMissRate::total 0.039762 # miss rate for overall accesses (Ratio)
|
|
system.cpu2.icache.demandAvgMissLatency::cpu2.inst 75075.747724 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu2.icache.demandAvgMissLatency::total 75075.747724 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu2.icache.overallAvgMissLatency::cpu2.inst 75075.747724 # average overall miss latency ((Tick/Count))
|
|
system.cpu2.icache.overallAvgMissLatency::total 75075.747724 # average overall miss latency ((Tick/Count))
|
|
system.cpu2.icache.blockedCycles::no_mshrs 734 # number of cycles access was blocked (Cycle)
|
|
system.cpu2.icache.blockedCycles::no_targets 65 # number of cycles access was blocked (Cycle)
|
|
system.cpu2.icache.blockedCauses::no_mshrs 11 # number of times access was blocked (Count)
|
|
system.cpu2.icache.blockedCauses::no_targets 1 # number of times access was blocked (Count)
|
|
system.cpu2.icache.avgBlocked::no_mshrs 66.727273 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu2.icache.avgBlocked::no_targets 65 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu2.icache.writebacks::writebacks 1891 # number of writebacks (Count)
|
|
system.cpu2.icache.writebacks::total 1891 # number of writebacks (Count)
|
|
system.cpu2.icache.demandMshrHits::cpu2.inst 671 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu2.icache.demandMshrHits::total 671 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu2.icache.overallMshrHits::cpu2.inst 671 # number of overall MSHR hits (Count)
|
|
system.cpu2.icache.overallMshrHits::total 671 # number of overall MSHR hits (Count)
|
|
system.cpu2.icache.demandMshrMisses::cpu2.inst 2405 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu2.icache.demandMshrMisses::total 2405 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu2.icache.overallMshrMisses::cpu2.inst 2405 # number of overall MSHR misses (Count)
|
|
system.cpu2.icache.overallMshrMisses::total 2405 # number of overall MSHR misses (Count)
|
|
system.cpu2.icache.demandMshrMissLatency::cpu2.inst 181425000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu2.icache.demandMshrMissLatency::total 181425000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu2.icache.overallMshrMissLatency::cpu2.inst 181425000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu2.icache.overallMshrMissLatency::total 181425000 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu2.icache.demandMshrMissRate::cpu2.inst 0.031088 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu2.icache.demandMshrMissRate::total 0.031088 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu2.icache.overallMshrMissRate::cpu2.inst 0.031088 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu2.icache.overallMshrMissRate::total 0.031088 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu2.icache.demandAvgMshrMissLatency::cpu2.inst 75436.590437 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu2.icache.demandAvgMshrMissLatency::total 75436.590437 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu2.icache.overallAvgMshrMissLatency::cpu2.inst 75436.590437 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu2.icache.overallAvgMshrMissLatency::total 75436.590437 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu2.icache.replacements 1891 # number of replacements (Count)
|
|
system.cpu2.icache.ReadReq.hits::cpu2.inst 74284 # number of ReadReq hits (Count)
|
|
system.cpu2.icache.ReadReq.hits::total 74284 # number of ReadReq hits (Count)
|
|
system.cpu2.icache.ReadReq.misses::cpu2.inst 3076 # number of ReadReq misses (Count)
|
|
system.cpu2.icache.ReadReq.misses::total 3076 # number of ReadReq misses (Count)
|
|
system.cpu2.icache.ReadReq.missLatency::cpu2.inst 230933000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu2.icache.ReadReq.missLatency::total 230933000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu2.icache.ReadReq.accesses::cpu2.inst 77360 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu2.icache.ReadReq.accesses::total 77360 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu2.icache.ReadReq.missRate::cpu2.inst 0.039762 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu2.icache.ReadReq.missRate::total 0.039762 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu2.icache.ReadReq.avgMissLatency::cpu2.inst 75075.747724 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu2.icache.ReadReq.avgMissLatency::total 75075.747724 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu2.icache.ReadReq.mshrHits::cpu2.inst 671 # number of ReadReq MSHR hits (Count)
|
|
system.cpu2.icache.ReadReq.mshrHits::total 671 # number of ReadReq MSHR hits (Count)
|
|
system.cpu2.icache.ReadReq.mshrMisses::cpu2.inst 2405 # number of ReadReq MSHR misses (Count)
|
|
system.cpu2.icache.ReadReq.mshrMisses::total 2405 # number of ReadReq MSHR misses (Count)
|
|
system.cpu2.icache.ReadReq.mshrMissLatency::cpu2.inst 181425000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu2.icache.ReadReq.mshrMissLatency::total 181425000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu2.icache.ReadReq.mshrMissRate::cpu2.inst 0.031088 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu2.icache.ReadReq.mshrMissRate::total 0.031088 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu2.icache.ReadReq.avgMshrMissLatency::cpu2.inst 75436.590437 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu2.icache.ReadReq.avgMshrMissLatency::total 75436.590437 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu2.icache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.icache.tags.tagsInUse 511.901211 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu2.icache.tags.totalRefs 76689 # Total number of references to valid blocks. (Count)
|
|
system.cpu2.icache.tags.sampledRefs 2405 # Sample count of references to valid blocks. (Count)
|
|
system.cpu2.icache.tags.avgRefs 31.887318 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu2.icache.tags.warmupTick 102500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu2.icache.tags.occupancies::cpu2.inst 511.901211 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu2.icache.tags.avgOccs::cpu2.inst 0.999807 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu2.icache.tags.avgOccs::total 0.999807 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu2.icache.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
|
|
system.cpu2.icache.tags.ageTaskId_1024::4 512 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu2.icache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu2.icache.tags.tagAccesses 157125 # Number of tag accesses (Count)
|
|
system.cpu2.icache.tags.dataAccesses 157125 # Number of data accesses (Count)
|
|
system.cpu2.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
|
|
system.cpu2.iew.squashCycles 6935 # Number of cycles IEW is squashing (Cycle)
|
|
system.cpu2.iew.blockCycles 239699 # Number of cycles IEW is blocking (Cycle)
|
|
system.cpu2.iew.unblockCycles 10275 # Number of cycles IEW is unblocking (Cycle)
|
|
system.cpu2.iew.dispatchedInsts 1016617 # Number of instructions dispatched to IQ (Count)
|
|
system.cpu2.iew.dispSquashedInsts 778 # Number of squashed instructions skipped by dispatch (Count)
|
|
system.cpu2.iew.dispLoadInsts 139792 # Number of dispatched load instructions (Count)
|
|
system.cpu2.iew.dispStoreInsts 61687 # Number of dispatched store instructions (Count)
|
|
system.cpu2.iew.dispNonSpecInsts 122 # Number of dispatched non-speculative instructions (Count)
|
|
system.cpu2.iew.iqFullEvents 1764 # Number of times the IQ has become full, causing a stall (Count)
|
|
system.cpu2.iew.lsqFullEvents 7539 # Number of times the LSQ has become full, causing a stall (Count)
|
|
system.cpu2.iew.memOrderViolationEvents 161 # Number of memory order violations (Count)
|
|
system.cpu2.iew.predictedTakenIncorrect 2091 # Number of branches that were predicted taken incorrectly (Count)
|
|
system.cpu2.iew.predictedNotTakenIncorrect 5474 # Number of branches that were predicted not taken incorrectly (Count)
|
|
system.cpu2.iew.branchMispredicts 7565 # Number of branch mispredicts detected at execute (Count)
|
|
system.cpu2.iew.instsToCommit 890373 # Cumulative count of insts sent to commit (Count)
|
|
system.cpu2.iew.writebackCount 886826 # Cumulative count of insts written-back (Count)
|
|
system.cpu2.iew.producerInst 656522 # Number of instructions producing a value (Count)
|
|
system.cpu2.iew.consumerInst 1183359 # Number of instructions consuming a value (Count)
|
|
system.cpu2.iew.wbRate 1.018953 # Insts written-back per cycle ((Count/Cycle))
|
|
system.cpu2.iew.wbFanout 0.554795 # Average fanout of values written-back ((Count/Count))
|
|
system.cpu2.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
|
|
system.cpu2.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu2.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu2.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu2.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu2.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu2.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu2.itb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu2.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu2.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu2.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu2.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu2.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu2.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu2.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu2.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.lsq0.forwLoads 12526 # Number of loads that had data forwarded from stores (Count)
|
|
system.cpu2.lsq0.squashedLoads 40798 # Number of loads squashed (Count)
|
|
system.cpu2.lsq0.ignoredResponses 148 # Number of memory responses ignored because the instruction is squashed (Count)
|
|
system.cpu2.lsq0.memOrderViolation 161 # Number of memory ordering violations (Count)
|
|
system.cpu2.lsq0.squashedStores 18061 # Number of stores squashed (Count)
|
|
system.cpu2.lsq0.rescheduledLoads 3 # Number of loads that were rescheduled (Count)
|
|
system.cpu2.lsq0.blockedByCache 147 # Number of times an access to memory failed due to the cache being blocked (Count)
|
|
system.cpu2.lsq0.loadToUse::samples 98994 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::mean 13.176526 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::stdev 42.667847 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::0-9 91525 92.46% 92.46% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::10-19 138 0.14% 92.59% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::20-29 1939 1.96% 94.55% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::30-39 85 0.09% 94.64% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::40-49 36 0.04% 94.68% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::50-59 28 0.03% 94.70% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::60-69 34 0.03% 94.74% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::70-79 32 0.03% 94.77% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::80-89 48 0.05% 94.82% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::90-99 113 0.11% 94.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::100-109 64 0.06% 95.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::110-119 52 0.05% 95.05% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::120-129 103 0.10% 95.15% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::130-139 142 0.14% 95.30% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::140-149 1131 1.14% 96.44% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::150-159 226 0.23% 96.67% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::160-169 147 0.15% 96.82% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::170-179 563 0.57% 97.39% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::180-189 151 0.15% 97.54% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::190-199 390 0.39% 97.93% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::200-209 1481 1.50% 99.43% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::210-219 189 0.19% 99.62% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::220-229 60 0.06% 99.68% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::230-239 56 0.06% 99.74% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::240-249 22 0.02% 99.76% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::250-259 28 0.03% 99.79% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::260-269 25 0.03% 99.81% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::270-279 28 0.03% 99.84% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::280-289 13 0.01% 99.85% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::290-299 26 0.03% 99.88% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::overflows 119 0.12% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::max_value 775 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.lsq0.loadToUse::total 98994 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu2.mmu.dtb.rdAccesses 128243 # TLB accesses on read requests (Count)
|
|
system.cpu2.mmu.dtb.wrAccesses 56016 # TLB accesses on write requests (Count)
|
|
system.cpu2.mmu.dtb.rdMisses 635 # TLB misses on read requests (Count)
|
|
system.cpu2.mmu.dtb.wrMisses 176 # TLB misses on write requests (Count)
|
|
system.cpu2.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
|
|
system.cpu2.mmu.itb.wrAccesses 77942 # TLB accesses on write requests (Count)
|
|
system.cpu2.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
|
|
system.cpu2.mmu.itb.wrMisses 857 # TLB misses on write requests (Count)
|
|
system.cpu2.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.power_state.pwrStateResidencyTicks::ON 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu2.rename.squashCycles 6935 # Number of cycles rename is squashing (Cycle)
|
|
system.cpu2.rename.idleCycles 145563 # Number of cycles rename is idle (Cycle)
|
|
system.cpu2.rename.blockCycles 304742 # Number of cycles rename is blocking (Cycle)
|
|
system.cpu2.rename.serializeStallCycles 2186 # count of cycles rename stalled for serializing inst (Cycle)
|
|
system.cpu2.rename.runCycles 148267 # Number of cycles rename is running (Cycle)
|
|
system.cpu2.rename.unblockCycles 83062 # Number of cycles rename is unblocking (Cycle)
|
|
system.cpu2.rename.renamedInsts 1061789 # Number of instructions processed by rename (Count)
|
|
system.cpu2.rename.ROBFullEvents 2060 # Number of times rename has blocked due to ROB full (Count)
|
|
system.cpu2.rename.IQFullEvents 24216 # Number of times rename has blocked due to IQ full (Count)
|
|
system.cpu2.rename.LQFullEvents 4142 # Number of times rename has blocked due to LQ full (Count)
|
|
system.cpu2.rename.SQFullEvents 48304 # Number of times rename has blocked due to SQ full (Count)
|
|
system.cpu2.rename.fullRegistersEvents 5 # Number of times there has been no free registers (Count)
|
|
system.cpu2.rename.renamedOperands 1829992 # Number of destination operands rename has renamed (Count)
|
|
system.cpu2.rename.lookups 3632060 # Number of register rename lookups that rename has made (Count)
|
|
system.cpu2.rename.intLookups 1397255 # Number of integer rename lookups (Count)
|
|
system.cpu2.rename.fpLookups 104678 # Number of floating rename lookups (Count)
|
|
system.cpu2.rename.committedMaps 1216351 # Number of HB maps that are committed (Count)
|
|
system.cpu2.rename.undoneMaps 613641 # Number of HB maps that are undone due to squashing (Count)
|
|
system.cpu2.rename.serializing 67 # count of serializing insts renamed (Count)
|
|
system.cpu2.rename.tempSerializing 54 # count of temporary serializing insts renamed (Count)
|
|
system.cpu2.rename.skidInsts 91477 # count of insts added to the skid buffer (Count)
|
|
system.cpu2.rob.reads 1613677 # The number of ROB reads (Count)
|
|
system.cpu2.rob.writes 2070513 # The number of ROB writes (Count)
|
|
system.cpu2.thread_0.numInsts 361747 # Number of Instructions committed (Count)
|
|
system.cpu2.thread_0.numOps 700651 # Number of Ops committed (Count)
|
|
system.cpu2.thread_0.numMemRefs 0 # Number of Memory References (Count)
|
|
system.cpu2.workload.numSyscalls 81 # Number of system calls (Count)
|
|
system.cpu3.numCycles 466065 # Number of cpu cycles simulated (Cycle)
|
|
system.cpu3.cpi 3.602713 # CPI: cycles per instruction (core level) ((Cycle/Count))
|
|
system.cpu3.ipc 0.277569 # IPC: instructions per cycle (core level) ((Count/Cycle))
|
|
system.cpu3.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
|
|
system.cpu3.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
|
|
system.cpu3.instsAdded 377758 # Number of instructions added to the IQ (excludes non-spec) (Count)
|
|
system.cpu3.nonSpecInstsAdded 162 # Number of non-speculative instructions added to the IQ (Count)
|
|
system.cpu3.instsIssued 334432 # Number of instructions issued (Count)
|
|
system.cpu3.squashedInstsIssued 732 # Number of squashed instructions issued (Count)
|
|
system.cpu3.squashedInstsExamined 126802 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
|
|
system.cpu3.squashedOperandsExamined 237597 # Number of squashed operands that are examined and possibly removed from graph (Count)
|
|
system.cpu3.squashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed (Count)
|
|
system.cpu3.numIssuedDist::samples 318388 # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::mean 1.050391 # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::stdev 2.011626 # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::0 228516 71.77% 71.77% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::1 16453 5.17% 76.94% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::2 15431 4.85% 81.79% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::3 13655 4.29% 86.08% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::4 11852 3.72% 89.80% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::5 10597 3.33% 93.13% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::6 11586 3.64% 96.77% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::7 6141 1.93% 98.69% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::8 4157 1.31% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
|
|
system.cpu3.numIssuedDist::total 318388 # Number of insts issued each cycle (Count)
|
|
system.cpu3.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::IntAlu 4579 73.90% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::IntMult 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::IntDiv 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::FloatAdd 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::FloatCmp 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::FloatCvt 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::FloatMult 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::FloatMultAcc 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::FloatDiv 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::FloatMisc 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::FloatSqrt 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdAdd 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdAddAcc 0 0.00% 73.90% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdAlu 60 0.97% 74.87% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdCmp 0 0.00% 74.87% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdCvt 83 1.34% 76.21% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdMisc 5 0.08% 76.29% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdMult 0 0.00% 76.29% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdMultAcc 0 0.00% 76.29% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdMatMultAcc 0 0.00% 76.29% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdShift 23 0.37% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdShiftAcc 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdDiv 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdSqrt 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatAdd 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatAlu 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatCmp 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatCvt 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatDiv 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatMisc 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatMult 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatMultAcc 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatMatMultAcc 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatSqrt 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdReduceAdd 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdReduceAlu 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdReduceCmp 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatReduceAdd 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdFloatReduceCmp 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdAes 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdAesMix 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdSha1Hash 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdSha1Hash2 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdSha256Hash 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdSha256Hash2 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdShaSigma2 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdShaSigma3 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::SimdPredAlu 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::Matrix 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::MatrixMov 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::MatrixOP 0 0.00% 76.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::MemRead 991 15.99% 92.66% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::MemWrite 376 6.07% 98.72% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::FloatMemRead 43 0.69% 99.42% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::FloatMemWrite 36 0.58% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorIntegerArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorFloatArith 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorFloatConvert 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorIntegerReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorFloatReduce 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorMisc 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorIntegerExtension 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statFuBusy::VectorConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
|
|
system.cpu3.statIssuedInstType_0::No_OpClass 5015 1.50% 1.50% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::IntAlu 249671 74.66% 76.15% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::IntMult 1033 0.31% 76.46% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::IntDiv 2125 0.64% 77.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::FloatAdd 878 0.26% 77.36% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::FloatCmp 0 0.00% 77.36% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::FloatCvt 0 0.00% 77.36% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::FloatMult 0 0.00% 77.36% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::FloatMultAcc 0 0.00% 77.36% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::FloatDiv 0 0.00% 77.36% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::FloatMisc 0 0.00% 77.36% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::FloatSqrt 0 0.00% 77.36% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdAdd 940 0.28% 77.64% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdAddAcc 0 0.00% 77.64% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdAlu 2872 0.86% 78.50% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdCmp 0 0.00% 78.50% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdCvt 2381 0.71% 79.21% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdMisc 1741 0.52% 79.73% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdMult 0 0.00% 79.73% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdMultAcc 0 0.00% 79.73% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 79.73% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdShift 1229 0.37% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdShiftAcc 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdDiv 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdSqrt 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatAdd 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatAlu 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatCmp 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatCvt 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatDiv 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatMisc 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatMult 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdReduceAdd 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdReduceAlu 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdReduceCmp 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdAes 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdAesMix 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdSha1Hash 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdSha256Hash 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdShaSigma2 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdShaSigma3 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::SimdPredAlu 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::Matrix 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::MatrixMov 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::MatrixOP 0 0.00% 80.10% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::MemRead 41530 12.42% 92.52% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::MemWrite 20113 6.01% 98.53% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::FloatMemRead 3330 1.00% 99.53% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::FloatMemWrite 1574 0.47% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorFloatArith 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorMisc 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::VectorConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.statIssuedInstType_0::total 334432 # Number of instructions issued per FU type, per thread (Count)
|
|
system.cpu3.issueRate 0.717565 # Inst issue rate ((Count/Cycle))
|
|
system.cpu3.fuBusy 6196 # FU busy when requested (Count)
|
|
system.cpu3.fuBusyRate 0.018527 # FU busy rate (busy events/executed inst) ((Count/Count))
|
|
system.cpu3.intInstQueueReads 962829 # Number of integer instruction queue reads (Count)
|
|
system.cpu3.intInstQueueWrites 477040 # Number of integer instruction queue writes (Count)
|
|
system.cpu3.intInstQueueWakeupAccesses 311051 # Number of integer instruction queue wakeup accesses (Count)
|
|
system.cpu3.fpInstQueueReads 31351 # Number of floating instruction queue reads (Count)
|
|
system.cpu3.fpInstQueueWrites 27768 # Number of floating instruction queue writes (Count)
|
|
system.cpu3.fpInstQueueWakeupAccesses 14570 # Number of floating instruction queue wakeup accesses (Count)
|
|
system.cpu3.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
|
|
system.cpu3.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
|
|
system.cpu3.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
|
|
system.cpu3.intAluAccesses 319844 # Number of integer alu accesses (Count)
|
|
system.cpu3.fpAluAccesses 15769 # Number of floating point alu accesses (Count)
|
|
system.cpu3.vecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu3.numSquashedInsts 5271 # Number of squashed instructions skipped in execute (Count)
|
|
system.cpu3.numSwp 0 # Number of swp insts executed (Count)
|
|
system.cpu3.timesIdled 1096 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
|
|
system.cpu3.idleCycles 147677 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
|
|
system.cpu3.MemDepUnit__0.insertedLoads 48704 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu3.MemDepUnit__0.insertedStores 24013 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu3.MemDepUnit__0.conflictingLoads 2529 # Number of conflicting loads. (Count)
|
|
system.cpu3.MemDepUnit__0.conflictingStores 2564 # Number of conflicting stores. (Count)
|
|
system.cpu3.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu3.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu3.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu3.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu3.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu3.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu3.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu3.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu3.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
|
|
system.cpu3.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
|
|
system.cpu3.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
|
|
system.cpu3.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
|
|
system.cpu3.branchPred.lookups 46333 # Number of BP lookups (Count)
|
|
system.cpu3.branchPred.condPredicted 38665 # Number of conditional branches predicted (Count)
|
|
system.cpu3.branchPred.condIncorrect 3639 # Number of conditional branches incorrect (Count)
|
|
system.cpu3.branchPred.BTBLookups 19723 # Number of BTB lookups (Count)
|
|
system.cpu3.branchPred.BTBUpdates 2430 # Number of BTB updates (Count)
|
|
system.cpu3.branchPred.BTBHits 18607 # Number of BTB hits (Count)
|
|
system.cpu3.branchPred.BTBHitRatio 0.943416 # BTB Hit Ratio (Ratio)
|
|
system.cpu3.branchPred.RASUsed 2064 # Number of times the RAS was used to get a target. (Count)
|
|
system.cpu3.branchPred.RASIncorrect 3 # Number of incorrect RAS predictions. (Count)
|
|
system.cpu3.branchPred.indirectLookups 1718 # Number of indirect predictor lookups. (Count)
|
|
system.cpu3.branchPred.indirectHits 304 # Number of indirect target hits. (Count)
|
|
system.cpu3.branchPred.indirectMisses 1414 # Number of indirect misses. (Count)
|
|
system.cpu3.branchPred.indirectMispredicted 445 # Number of mispredicted indirect branches. (Count)
|
|
system.cpu3.branchPred.loop_predictor.correct 16164 # Number of times the loop predictor is the provider and the prediction is correct (Count)
|
|
system.cpu3.branchPred.loop_predictor.wrong 5975 # Number of times the loop predictor is the provider and the prediction is wrong (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProviderCorrect 7377 # Number of times TAGE Longest Match is the provider and the prediction is correct (Count)
|
|
system.cpu3.branchPred.tage.altMatchProviderCorrect 529 # Number of times TAGE Alt Match is the provider and the prediction is correct (Count)
|
|
system.cpu3.branchPred.tage.bimodalAltMatchProviderCorrect 207 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is correct (Count)
|
|
system.cpu3.branchPred.tage.bimodalProviderCorrect 11856 # Number of times there are no hits on the TAGE tables and the bimodal prediction is correct (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProviderWrong 739 # Number of times TAGE Longest Match is the provider and the prediction is wrong (Count)
|
|
system.cpu3.branchPred.tage.altMatchProviderWrong 173 # Number of times TAGE Alt Match is the provider and the prediction is wrong (Count)
|
|
system.cpu3.branchPred.tage.bimodalAltMatchProviderWrong 90 # Number of times TAGE Alt Match is the bimodal and it is the provider and the prediction is wrong (Count)
|
|
system.cpu3.branchPred.tage.bimodalProviderWrong 1168 # Number of times there are no hits on the TAGE tables and the bimodal prediction is wrong (Count)
|
|
system.cpu3.branchPred.tage.altMatchProviderWouldHaveHit 215 # Number of times TAGE Longest Match is the provider, the prediction is wrong and Alt Match prediction was correct (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProviderWouldHaveHit 187 # Number of times TAGE Alt Match is the provider, the prediction is wrong and Longest Match prediction was correct (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::0 0 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::1 1770 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::2 2221 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::3 1713 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::4 1448 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::5 1087 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::6 429 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::7 140 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::8 4 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::9 4 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::10 1 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::11 1 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.longestMatchProvider::12 0 # TAGE provider for longest match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::0 3669 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::1 1304 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::2 1367 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::3 1205 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::4 912 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::5 339 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::6 21 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::7 1 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::8 0 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::9 0 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::10 0 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::11 0 # TAGE provider for alt match (Count)
|
|
system.cpu3.branchPred.tage.altMatchProvider::12 0 # TAGE provider for alt match (Count)
|
|
system.cpu3.commit.commitSquashedInsts 125250 # The number of squashed insts skipped by commit (Count)
|
|
system.cpu3.commit.commitNonSpecStalls 87 # The number of times commit has been forced to stall to communicate backwards (Count)
|
|
system.cpu3.commit.branchMispredicts 3246 # The number of times a branch was mispredicted (Count)
|
|
system.cpu3.commit.numCommittedDist::samples 300201 # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::mean 0.836500 # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::stdev 2.036764 # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::0 237119 78.99% 78.99% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::1 14633 4.87% 83.86% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::2 10348 3.45% 87.31% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::3 10839 3.61% 90.92% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::4 4679 1.56% 92.48% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::5 3068 1.02% 93.50% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::6 2436 0.81% 94.31% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::7 2032 0.68% 94.99% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::8 15047 5.01% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.numCommittedDist::total 300201 # Number of insts commited each cycle (Count)
|
|
system.cpu3.commit.amos 0 # Number of atomic instructions committed (Count)
|
|
system.cpu3.commit.membars 58 # Number of memory barriers committed (Count)
|
|
system.cpu3.commit.functionCalls 1211 # Number of function calls committed. (Count)
|
|
system.cpu3.commit.committedInstType_0::No_OpClass 2149 0.86% 0.86% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::IntAlu 189295 75.38% 76.24% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::IntMult 873 0.35% 76.58% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::IntDiv 1937 0.77% 77.36% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::FloatAdd 524 0.21% 77.56% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::FloatCmp 0 0.00% 77.56% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::FloatCvt 0 0.00% 77.56% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::FloatMult 0 0.00% 77.56% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::FloatMultAcc 0 0.00% 77.56% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::FloatDiv 0 0.00% 77.56% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::FloatMisc 0 0.00% 77.56% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::FloatSqrt 0 0.00% 77.56% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdAdd 704 0.28% 77.84% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdAddAcc 0 0.00% 77.84% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdAlu 1882 0.75% 78.59% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdCmp 0 0.00% 78.59% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdCvt 1634 0.65% 79.24% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdMisc 1456 0.58% 79.82% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdMult 0 0.00% 79.82% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdMultAcc 0 0.00% 79.82% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 79.82% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdShift 610 0.24% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdShiftAcc 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdDiv 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdSqrt 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatAdd 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatAlu 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatCmp 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatCvt 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatDiv 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatMisc 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatMult 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdReduceAdd 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdReduceAlu 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdReduceCmp 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdAes 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdAesMix 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdSha1Hash 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdSha256Hash 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdShaSigma2 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdShaSigma3 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::SimdPredAlu 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::Matrix 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::MatrixMov 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::MatrixOP 0 0.00% 80.07% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::MemRead 31666 12.61% 92.68% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::MemWrite 15289 6.09% 98.77% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::FloatMemRead 1826 0.73% 99.49% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::FloatMemWrite 1273 0.51% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorMisc 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::VectorConfig 0 0.00% 100.00% # Class of committed instruction (Count)
|
|
system.cpu3.commit.committedInstType_0::total 251118 # Class of committed instruction (Count)
|
|
system.cpu3.commit.commitEligibleSamples 15047 # number cycles where commit BW limit reached (Cycle)
|
|
system.cpu3.commitStats0.numInsts 129365 # Number of instructions committed (thread level) (Count)
|
|
system.cpu3.commitStats0.numOps 251118 # Number of ops (including micro ops) committed (thread level) (Count)
|
|
system.cpu3.commitStats0.numInstsNotNOP 129365 # Number of instructions committed excluding NOPs or prefetches (Count)
|
|
system.cpu3.commitStats0.numOpsNotNOP 251118 # Number of Ops (including micro ops) Simulated (Count)
|
|
system.cpu3.commitStats0.cpi 3.602713 # CPI: cycles per instruction (thread level) ((Cycle/Count))
|
|
system.cpu3.commitStats0.ipc 0.277569 # IPC: instructions per cycle (thread level) ((Count/Cycle))
|
|
system.cpu3.commitStats0.numMemRefs 50054 # Number of memory references committed (Count)
|
|
system.cpu3.commitStats0.numFpInsts 10396 # Number of float instructions (Count)
|
|
system.cpu3.commitStats0.numIntInsts 241304 # Number of integer instructions (Count)
|
|
system.cpu3.commitStats0.numLoadInsts 33492 # Number of load instructions (Count)
|
|
system.cpu3.commitStats0.numStoreInsts 16562 # Number of store instructions (Count)
|
|
system.cpu3.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
|
|
system.cpu3.commitStats0.committedInstType::No_OpClass 2149 0.86% 0.86% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::IntAlu 189295 75.38% 76.24% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::IntMult 873 0.35% 76.58% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::IntDiv 1937 0.77% 77.36% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::FloatAdd 524 0.21% 77.56% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::FloatCmp 0 0.00% 77.56% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::FloatCvt 0 0.00% 77.56% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::FloatMult 0 0.00% 77.56% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::FloatMultAcc 0 0.00% 77.56% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::FloatDiv 0 0.00% 77.56% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::FloatMisc 0 0.00% 77.56% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::FloatSqrt 0 0.00% 77.56% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdAdd 704 0.28% 77.84% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdAddAcc 0 0.00% 77.84% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdAlu 1882 0.75% 78.59% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdCmp 0 0.00% 78.59% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdCvt 1634 0.65% 79.24% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdMisc 1456 0.58% 79.82% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdMult 0 0.00% 79.82% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdMultAcc 0 0.00% 79.82% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 79.82% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdShift 610 0.24% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdDiv 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdSqrt 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatMult 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdAes 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdAesMix 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::SimdPredAlu 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::Matrix 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::MatrixMov 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::MatrixOP 0 0.00% 80.07% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::MemRead 31666 12.61% 92.68% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::MemWrite 15289 6.09% 98.77% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::FloatMemRead 1826 0.73% 99.49% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::FloatMemWrite 1273 0.51% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorIntegerArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorFloatArith 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorFloatConvert 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorIntegerReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorFloatReduce 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorMisc 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorIntegerExtension 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::VectorConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedInstType::total 251118 # Class of committed instruction. (Count)
|
|
system.cpu3.commitStats0.committedControl::IsControl 25926 # Class of control type instructions committed (Count)
|
|
system.cpu3.commitStats0.committedControl::IsDirectControl 24108 # Class of control type instructions committed (Count)
|
|
system.cpu3.commitStats0.committedControl::IsIndirectControl 1724 # Class of control type instructions committed (Count)
|
|
system.cpu3.commitStats0.committedControl::IsCondControl 22045 # Class of control type instructions committed (Count)
|
|
system.cpu3.commitStats0.committedControl::IsUncondControl 3787 # Class of control type instructions committed (Count)
|
|
system.cpu3.commitStats0.committedControl::IsCall 1211 # Class of control type instructions committed (Count)
|
|
system.cpu3.commitStats0.committedControl::IsReturn 1206 # Class of control type instructions committed (Count)
|
|
system.cpu3.dcache.demandHits::cpu3.data 51746 # number of demand (read+write) hits (Count)
|
|
system.cpu3.dcache.demandHits::total 51746 # number of demand (read+write) hits (Count)
|
|
system.cpu3.dcache.overallHits::cpu3.data 51746 # number of overall hits (Count)
|
|
system.cpu3.dcache.overallHits::total 51746 # number of overall hits (Count)
|
|
system.cpu3.dcache.demandMisses::cpu3.data 4147 # number of demand (read+write) misses (Count)
|
|
system.cpu3.dcache.demandMisses::total 4147 # number of demand (read+write) misses (Count)
|
|
system.cpu3.dcache.overallMisses::cpu3.data 4147 # number of overall misses (Count)
|
|
system.cpu3.dcache.overallMisses::total 4147 # number of overall misses (Count)
|
|
system.cpu3.dcache.demandMissLatency::cpu3.data 327791500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu3.dcache.demandMissLatency::total 327791500 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu3.dcache.overallMissLatency::cpu3.data 327791500 # number of overall miss ticks (Tick)
|
|
system.cpu3.dcache.overallMissLatency::total 327791500 # number of overall miss ticks (Tick)
|
|
system.cpu3.dcache.demandAccesses::cpu3.data 55893 # number of demand (read+write) accesses (Count)
|
|
system.cpu3.dcache.demandAccesses::total 55893 # number of demand (read+write) accesses (Count)
|
|
system.cpu3.dcache.overallAccesses::cpu3.data 55893 # number of overall (read+write) accesses (Count)
|
|
system.cpu3.dcache.overallAccesses::total 55893 # number of overall (read+write) accesses (Count)
|
|
system.cpu3.dcache.demandMissRate::cpu3.data 0.074195 # miss rate for demand accesses (Ratio)
|
|
system.cpu3.dcache.demandMissRate::total 0.074195 # miss rate for demand accesses (Ratio)
|
|
system.cpu3.dcache.overallMissRate::cpu3.data 0.074195 # miss rate for overall accesses (Ratio)
|
|
system.cpu3.dcache.overallMissRate::total 0.074195 # miss rate for overall accesses (Ratio)
|
|
system.cpu3.dcache.demandAvgMissLatency::cpu3.data 79043.043164 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu3.dcache.demandAvgMissLatency::total 79043.043164 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu3.dcache.overallAvgMissLatency::cpu3.data 79043.043164 # average overall miss latency ((Tick/Count))
|
|
system.cpu3.dcache.overallAvgMissLatency::total 79043.043164 # average overall miss latency ((Tick/Count))
|
|
system.cpu3.dcache.blockedCycles::no_mshrs 2756 # number of cycles access was blocked (Cycle)
|
|
system.cpu3.dcache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu3.dcache.blockedCauses::no_mshrs 53 # number of times access was blocked (Count)
|
|
system.cpu3.dcache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu3.dcache.avgBlocked::no_mshrs 52 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu3.dcache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu3.dcache.writebacks::writebacks 542 # number of writebacks (Count)
|
|
system.cpu3.dcache.writebacks::total 542 # number of writebacks (Count)
|
|
system.cpu3.dcache.demandMshrHits::cpu3.data 2251 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu3.dcache.demandMshrHits::total 2251 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu3.dcache.overallMshrHits::cpu3.data 2251 # number of overall MSHR hits (Count)
|
|
system.cpu3.dcache.overallMshrHits::total 2251 # number of overall MSHR hits (Count)
|
|
system.cpu3.dcache.demandMshrMisses::cpu3.data 1896 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu3.dcache.demandMshrMisses::total 1896 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu3.dcache.overallMshrMisses::cpu3.data 1896 # number of overall MSHR misses (Count)
|
|
system.cpu3.dcache.overallMshrMisses::total 1896 # number of overall MSHR misses (Count)
|
|
system.cpu3.dcache.demandMshrMissLatency::cpu3.data 146203500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu3.dcache.demandMshrMissLatency::total 146203500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu3.dcache.overallMshrMissLatency::cpu3.data 146203500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu3.dcache.overallMshrMissLatency::total 146203500 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu3.dcache.demandMshrMissRate::cpu3.data 0.033922 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu3.dcache.demandMshrMissRate::total 0.033922 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu3.dcache.overallMshrMissRate::cpu3.data 0.033922 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu3.dcache.overallMshrMissRate::total 0.033922 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu3.dcache.demandAvgMshrMissLatency::cpu3.data 77111.550633 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu3.dcache.demandAvgMshrMissLatency::total 77111.550633 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu3.dcache.overallAvgMshrMissLatency::cpu3.data 77111.550633 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu3.dcache.overallAvgMshrMissLatency::total 77111.550633 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu3.dcache.replacements 1385 # number of replacements (Count)
|
|
system.cpu3.dcache.LockedRMWReadReq.hits::cpu3.data 27 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu3.dcache.LockedRMWReadReq.hits::total 27 # number of LockedRMWReadReq hits (Count)
|
|
system.cpu3.dcache.LockedRMWReadReq.misses::cpu3.data 2 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu3.dcache.LockedRMWReadReq.misses::total 2 # number of LockedRMWReadReq misses (Count)
|
|
system.cpu3.dcache.LockedRMWReadReq.missLatency::cpu3.data 114000 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu3.dcache.LockedRMWReadReq.missLatency::total 114000 # number of LockedRMWReadReq miss ticks (Tick)
|
|
system.cpu3.dcache.LockedRMWReadReq.accesses::cpu3.data 29 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu3.dcache.LockedRMWReadReq.accesses::total 29 # number of LockedRMWReadReq accesses(hits+misses) (Count)
|
|
system.cpu3.dcache.LockedRMWReadReq.missRate::cpu3.data 0.068966 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu3.dcache.LockedRMWReadReq.missRate::total 0.068966 # miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu3.dcache.LockedRMWReadReq.avgMissLatency::cpu3.data 57000 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu3.dcache.LockedRMWReadReq.avgMissLatency::total 57000 # average LockedRMWReadReq miss latency ((Tick/Count))
|
|
system.cpu3.dcache.LockedRMWReadReq.mshrMisses::cpu3.data 2 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu3.dcache.LockedRMWReadReq.mshrMisses::total 2 # number of LockedRMWReadReq MSHR misses (Count)
|
|
system.cpu3.dcache.LockedRMWReadReq.mshrMissLatency::cpu3.data 345000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu3.dcache.LockedRMWReadReq.mshrMissLatency::total 345000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
|
|
system.cpu3.dcache.LockedRMWReadReq.mshrMissRate::cpu3.data 0.068966 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu3.dcache.LockedRMWReadReq.mshrMissRate::total 0.068966 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
|
|
system.cpu3.dcache.LockedRMWReadReq.avgMshrMissLatency::cpu3.data 172500 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu3.dcache.LockedRMWReadReq.avgMshrMissLatency::total 172500 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu3.dcache.LockedRMWWriteReq.hits::cpu3.data 29 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu3.dcache.LockedRMWWriteReq.hits::total 29 # number of LockedRMWWriteReq hits (Count)
|
|
system.cpu3.dcache.LockedRMWWriteReq.accesses::cpu3.data 29 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu3.dcache.LockedRMWWriteReq.accesses::total 29 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
|
|
system.cpu3.dcache.ReadReq.hits::cpu3.data 35579 # number of ReadReq hits (Count)
|
|
system.cpu3.dcache.ReadReq.hits::total 35579 # number of ReadReq hits (Count)
|
|
system.cpu3.dcache.ReadReq.misses::cpu3.data 3779 # number of ReadReq misses (Count)
|
|
system.cpu3.dcache.ReadReq.misses::total 3779 # number of ReadReq misses (Count)
|
|
system.cpu3.dcache.ReadReq.missLatency::cpu3.data 296146000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu3.dcache.ReadReq.missLatency::total 296146000 # number of ReadReq miss ticks (Tick)
|
|
system.cpu3.dcache.ReadReq.accesses::cpu3.data 39358 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu3.dcache.ReadReq.accesses::total 39358 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu3.dcache.ReadReq.missRate::cpu3.data 0.096016 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu3.dcache.ReadReq.missRate::total 0.096016 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu3.dcache.ReadReq.avgMissLatency::cpu3.data 78366.234454 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu3.dcache.ReadReq.avgMissLatency::total 78366.234454 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu3.dcache.ReadReq.mshrHits::cpu3.data 2249 # number of ReadReq MSHR hits (Count)
|
|
system.cpu3.dcache.ReadReq.mshrHits::total 2249 # number of ReadReq MSHR hits (Count)
|
|
system.cpu3.dcache.ReadReq.mshrMisses::cpu3.data 1530 # number of ReadReq MSHR misses (Count)
|
|
system.cpu3.dcache.ReadReq.mshrMisses::total 1530 # number of ReadReq MSHR misses (Count)
|
|
system.cpu3.dcache.ReadReq.mshrMissLatency::cpu3.data 115061000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu3.dcache.ReadReq.mshrMissLatency::total 115061000 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu3.dcache.ReadReq.mshrMissRate::cpu3.data 0.038874 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu3.dcache.ReadReq.mshrMissRate::total 0.038874 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu3.dcache.ReadReq.avgMshrMissLatency::cpu3.data 75203.267974 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu3.dcache.ReadReq.avgMshrMissLatency::total 75203.267974 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu3.dcache.WriteReq.hits::cpu3.data 16167 # number of WriteReq hits (Count)
|
|
system.cpu3.dcache.WriteReq.hits::total 16167 # number of WriteReq hits (Count)
|
|
system.cpu3.dcache.WriteReq.misses::cpu3.data 368 # number of WriteReq misses (Count)
|
|
system.cpu3.dcache.WriteReq.misses::total 368 # number of WriteReq misses (Count)
|
|
system.cpu3.dcache.WriteReq.missLatency::cpu3.data 31645500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu3.dcache.WriteReq.missLatency::total 31645500 # number of WriteReq miss ticks (Tick)
|
|
system.cpu3.dcache.WriteReq.accesses::cpu3.data 16535 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu3.dcache.WriteReq.accesses::total 16535 # number of WriteReq accesses(hits+misses) (Count)
|
|
system.cpu3.dcache.WriteReq.missRate::cpu3.data 0.022256 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu3.dcache.WriteReq.missRate::total 0.022256 # miss rate for WriteReq accesses (Ratio)
|
|
system.cpu3.dcache.WriteReq.avgMissLatency::cpu3.data 85993.206522 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu3.dcache.WriteReq.avgMissLatency::total 85993.206522 # average WriteReq miss latency ((Tick/Count))
|
|
system.cpu3.dcache.WriteReq.mshrHits::cpu3.data 2 # number of WriteReq MSHR hits (Count)
|
|
system.cpu3.dcache.WriteReq.mshrHits::total 2 # number of WriteReq MSHR hits (Count)
|
|
system.cpu3.dcache.WriteReq.mshrMisses::cpu3.data 366 # number of WriteReq MSHR misses (Count)
|
|
system.cpu3.dcache.WriteReq.mshrMisses::total 366 # number of WriteReq MSHR misses (Count)
|
|
system.cpu3.dcache.WriteReq.mshrMissLatency::cpu3.data 31142500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu3.dcache.WriteReq.mshrMissLatency::total 31142500 # number of WriteReq MSHR miss ticks (Tick)
|
|
system.cpu3.dcache.WriteReq.mshrMissRate::cpu3.data 0.022135 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu3.dcache.WriteReq.mshrMissRate::total 0.022135 # mshr miss rate for WriteReq accesses (Ratio)
|
|
system.cpu3.dcache.WriteReq.avgMshrMissLatency::cpu3.data 85088.797814 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu3.dcache.WriteReq.avgMshrMissLatency::total 85088.797814 # average WriteReq mshr miss latency ((Tick/Count))
|
|
system.cpu3.dcache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.dcache.tags.tagsInUse 511.888394 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu3.dcache.tags.totalRefs 53700 # Total number of references to valid blocks. (Count)
|
|
system.cpu3.dcache.tags.sampledRefs 1897 # Sample count of references to valid blocks. (Count)
|
|
system.cpu3.dcache.tags.avgRefs 28.307855 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu3.dcache.tags.warmupTick 244500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu3.dcache.tags.occupancies::cpu3.data 511.888394 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu3.dcache.tags.avgOccs::cpu3.data 0.999782 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu3.dcache.tags.avgOccs::total 0.999782 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu3.dcache.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
|
|
system.cpu3.dcache.tags.ageTaskId_1024::4 512 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu3.dcache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu3.dcache.tags.tagAccesses 113799 # Number of tag accesses (Count)
|
|
system.cpu3.dcache.tags.dataAccesses 113799 # Number of data accesses (Count)
|
|
system.cpu3.dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.decode.idleCycles 77757 # Number of cycles decode is idle (Cycle)
|
|
system.cpu3.decode.blockedCycles 176508 # Number of cycles decode is blocked (Cycle)
|
|
system.cpu3.decode.runCycles 52791 # Number of cycles decode is running (Cycle)
|
|
system.cpu3.decode.unblockCycles 7856 # Number of cycles decode is unblocking (Cycle)
|
|
system.cpu3.decode.squashCycles 3476 # Number of cycles decode is squashing (Cycle)
|
|
system.cpu3.decode.branchResolved 17421 # Number of times decode resolved a branch (Count)
|
|
system.cpu3.decode.branchMispred 747 # Number of times decode detected a branch misprediction (Count)
|
|
system.cpu3.decode.decodedInsts 409267 # Number of instructions handled by decode (Count)
|
|
system.cpu3.decode.squashedInsts 3688 # Number of squashed instructions handled by decode (Count)
|
|
system.cpu3.dtb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu3.dtb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu3.dtb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu3.dtb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu3.dtb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu3.dtb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu3.dtb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu3.dtb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.dtb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu3.dtb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu3.dtb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu3.dtb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu3.dtb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu3.dtb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu3.dtb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu3.dtb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.executeStats0.numInsts 329161 # Number of executed instructions (Count)
|
|
system.cpu3.executeStats0.numNop 0 # Number of nop insts executed (Count)
|
|
system.cpu3.executeStats0.numBranches 30708 # Number of branches executed (Count)
|
|
system.cpu3.executeStats0.numLoadInsts 43968 # Number of load instructions executed (Count)
|
|
system.cpu3.executeStats0.numStoreInsts 21335 # Number of stores executed (Count)
|
|
system.cpu3.executeStats0.instRate 0.706256 # Inst execution rate ((Count/Cycle))
|
|
system.cpu3.executeStats0.numCCRegReads 178094 # Number of times the CC registers were read (Count)
|
|
system.cpu3.executeStats0.numCCRegWrites 107912 # Number of times the CC registers were written (Count)
|
|
system.cpu3.executeStats0.numFpRegReads 22374 # Number of times the floating registers were read (Count)
|
|
system.cpu3.executeStats0.numFpRegWrites 12006 # Number of times the floating registers were written (Count)
|
|
system.cpu3.executeStats0.numIntRegReads 410651 # Number of times the integer registers were read (Count)
|
|
system.cpu3.executeStats0.numIntRegWrites 241696 # Number of times the integer registers were written (Count)
|
|
system.cpu3.executeStats0.numMemRefs 65303 # Number of memory refs (Count)
|
|
system.cpu3.executeStats0.numMiscRegReads 130241 # Number of times the Misc registers were read (Count)
|
|
system.cpu3.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
|
|
system.cpu3.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
|
|
system.cpu3.fetch.predictedBranches 20975 # Number of branches that fetch has predicted taken (Count)
|
|
system.cpu3.fetch.cycles 226533 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
|
|
system.cpu3.fetch.squashCycles 8418 # Number of cycles fetch has spent squashing (Cycle)
|
|
system.cpu3.fetch.miscStallCycles 761 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
|
|
system.cpu3.fetch.pendingTrapStallCycles 2662 # Number of stall cycles due to pending traps (Cycle)
|
|
system.cpu3.fetch.icacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR (Cycle)
|
|
system.cpu3.fetch.cacheLines 28228 # Number of cache lines fetched (Count)
|
|
system.cpu3.fetch.icacheSquashes 1605 # Number of outstanding Icache misses that were squashed (Count)
|
|
system.cpu3.fetch.nisnDist::samples 318388 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::mean 1.399930 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::stdev 2.832359 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::0 247536 77.75% 77.75% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::1 4279 1.34% 79.09% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::2 4083 1.28% 80.37% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::3 3670 1.15% 81.53% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::4 3171 1.00% 82.52% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::5 5538 1.74% 84.26% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::6 6585 2.07% 86.33% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::7 5826 1.83% 88.16% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::8 37700 11.84% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetch.nisnDist::total 318388 # Number of instructions fetched each cycle (Total) (Count)
|
|
system.cpu3.fetchStats0.numInsts 226533 # Number of instructions fetched (thread level) (Count)
|
|
system.cpu3.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
|
|
system.cpu3.fetchStats0.fetchRate 0.486055 # Number of inst fetches per cycle ((Count/Cycle))
|
|
system.cpu3.fetchStats0.numBranches 46333 # Number of branches fetched (Count)
|
|
system.cpu3.fetchStats0.branchRate 0.099413 # Number of branch fetches per cycle (Ratio)
|
|
system.cpu3.fetchStats0.icacheStallCycles 84188 # ICache total stall cycles (Cycle)
|
|
system.cpu3.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
|
|
system.cpu3.icache.demandHits::cpu3.inst 26048 # number of demand (read+write) hits (Count)
|
|
system.cpu3.icache.demandHits::total 26048 # number of demand (read+write) hits (Count)
|
|
system.cpu3.icache.overallHits::cpu3.inst 26048 # number of overall hits (Count)
|
|
system.cpu3.icache.overallHits::total 26048 # number of overall hits (Count)
|
|
system.cpu3.icache.demandMisses::cpu3.inst 2179 # number of demand (read+write) misses (Count)
|
|
system.cpu3.icache.demandMisses::total 2179 # number of demand (read+write) misses (Count)
|
|
system.cpu3.icache.overallMisses::cpu3.inst 2179 # number of overall misses (Count)
|
|
system.cpu3.icache.overallMisses::total 2179 # number of overall misses (Count)
|
|
system.cpu3.icache.demandMissLatency::cpu3.inst 190603999 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu3.icache.demandMissLatency::total 190603999 # number of demand (read+write) miss ticks (Tick)
|
|
system.cpu3.icache.overallMissLatency::cpu3.inst 190603999 # number of overall miss ticks (Tick)
|
|
system.cpu3.icache.overallMissLatency::total 190603999 # number of overall miss ticks (Tick)
|
|
system.cpu3.icache.demandAccesses::cpu3.inst 28227 # number of demand (read+write) accesses (Count)
|
|
system.cpu3.icache.demandAccesses::total 28227 # number of demand (read+write) accesses (Count)
|
|
system.cpu3.icache.overallAccesses::cpu3.inst 28227 # number of overall (read+write) accesses (Count)
|
|
system.cpu3.icache.overallAccesses::total 28227 # number of overall (read+write) accesses (Count)
|
|
system.cpu3.icache.demandMissRate::cpu3.inst 0.077196 # miss rate for demand accesses (Ratio)
|
|
system.cpu3.icache.demandMissRate::total 0.077196 # miss rate for demand accesses (Ratio)
|
|
system.cpu3.icache.overallMissRate::cpu3.inst 0.077196 # miss rate for overall accesses (Ratio)
|
|
system.cpu3.icache.overallMissRate::total 0.077196 # miss rate for overall accesses (Ratio)
|
|
system.cpu3.icache.demandAvgMissLatency::cpu3.inst 87473.152363 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu3.icache.demandAvgMissLatency::total 87473.152363 # average overall miss latency in ticks ((Tick/Count))
|
|
system.cpu3.icache.overallAvgMissLatency::cpu3.inst 87473.152363 # average overall miss latency ((Tick/Count))
|
|
system.cpu3.icache.overallAvgMissLatency::total 87473.152363 # average overall miss latency ((Tick/Count))
|
|
system.cpu3.icache.blockedCycles::no_mshrs 218 # number of cycles access was blocked (Cycle)
|
|
system.cpu3.icache.blockedCycles::no_targets 416 # number of cycles access was blocked (Cycle)
|
|
system.cpu3.icache.blockedCauses::no_mshrs 4 # number of times access was blocked (Count)
|
|
system.cpu3.icache.blockedCauses::no_targets 1 # number of times access was blocked (Count)
|
|
system.cpu3.icache.avgBlocked::no_mshrs 54.500000 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu3.icache.avgBlocked::no_targets 416 # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu3.icache.writebacks::writebacks 1118 # number of writebacks (Count)
|
|
system.cpu3.icache.writebacks::total 1118 # number of writebacks (Count)
|
|
system.cpu3.icache.demandMshrHits::cpu3.inst 554 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu3.icache.demandMshrHits::total 554 # number of demand (read+write) MSHR hits (Count)
|
|
system.cpu3.icache.overallMshrHits::cpu3.inst 554 # number of overall MSHR hits (Count)
|
|
system.cpu3.icache.overallMshrHits::total 554 # number of overall MSHR hits (Count)
|
|
system.cpu3.icache.demandMshrMisses::cpu3.inst 1625 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu3.icache.demandMshrMisses::total 1625 # number of demand (read+write) MSHR misses (Count)
|
|
system.cpu3.icache.overallMshrMisses::cpu3.inst 1625 # number of overall MSHR misses (Count)
|
|
system.cpu3.icache.overallMshrMisses::total 1625 # number of overall MSHR misses (Count)
|
|
system.cpu3.icache.demandMshrMissLatency::cpu3.inst 143206999 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu3.icache.demandMshrMissLatency::total 143206999 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.cpu3.icache.overallMshrMissLatency::cpu3.inst 143206999 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu3.icache.overallMshrMissLatency::total 143206999 # number of overall MSHR miss ticks (Tick)
|
|
system.cpu3.icache.demandMshrMissRate::cpu3.inst 0.057569 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu3.icache.demandMshrMissRate::total 0.057569 # mshr miss ratio for demand accesses (Ratio)
|
|
system.cpu3.icache.overallMshrMissRate::cpu3.inst 0.057569 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu3.icache.overallMshrMissRate::total 0.057569 # mshr miss ratio for overall accesses (Ratio)
|
|
system.cpu3.icache.demandAvgMshrMissLatency::cpu3.inst 88127.384000 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu3.icache.demandAvgMshrMissLatency::total 88127.384000 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu3.icache.overallAvgMshrMissLatency::cpu3.inst 88127.384000 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu3.icache.overallAvgMshrMissLatency::total 88127.384000 # average overall mshr miss latency ((Tick/Count))
|
|
system.cpu3.icache.replacements 1118 # number of replacements (Count)
|
|
system.cpu3.icache.ReadReq.hits::cpu3.inst 26048 # number of ReadReq hits (Count)
|
|
system.cpu3.icache.ReadReq.hits::total 26048 # number of ReadReq hits (Count)
|
|
system.cpu3.icache.ReadReq.misses::cpu3.inst 2179 # number of ReadReq misses (Count)
|
|
system.cpu3.icache.ReadReq.misses::total 2179 # number of ReadReq misses (Count)
|
|
system.cpu3.icache.ReadReq.missLatency::cpu3.inst 190603999 # number of ReadReq miss ticks (Tick)
|
|
system.cpu3.icache.ReadReq.missLatency::total 190603999 # number of ReadReq miss ticks (Tick)
|
|
system.cpu3.icache.ReadReq.accesses::cpu3.inst 28227 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu3.icache.ReadReq.accesses::total 28227 # number of ReadReq accesses(hits+misses) (Count)
|
|
system.cpu3.icache.ReadReq.missRate::cpu3.inst 0.077196 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu3.icache.ReadReq.missRate::total 0.077196 # miss rate for ReadReq accesses (Ratio)
|
|
system.cpu3.icache.ReadReq.avgMissLatency::cpu3.inst 87473.152363 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu3.icache.ReadReq.avgMissLatency::total 87473.152363 # average ReadReq miss latency ((Tick/Count))
|
|
system.cpu3.icache.ReadReq.mshrHits::cpu3.inst 554 # number of ReadReq MSHR hits (Count)
|
|
system.cpu3.icache.ReadReq.mshrHits::total 554 # number of ReadReq MSHR hits (Count)
|
|
system.cpu3.icache.ReadReq.mshrMisses::cpu3.inst 1625 # number of ReadReq MSHR misses (Count)
|
|
system.cpu3.icache.ReadReq.mshrMisses::total 1625 # number of ReadReq MSHR misses (Count)
|
|
system.cpu3.icache.ReadReq.mshrMissLatency::cpu3.inst 143206999 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu3.icache.ReadReq.mshrMissLatency::total 143206999 # number of ReadReq MSHR miss ticks (Tick)
|
|
system.cpu3.icache.ReadReq.mshrMissRate::cpu3.inst 0.057569 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu3.icache.ReadReq.mshrMissRate::total 0.057569 # mshr miss rate for ReadReq accesses (Ratio)
|
|
system.cpu3.icache.ReadReq.avgMshrMissLatency::cpu3.inst 88127.384000 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu3.icache.ReadReq.avgMshrMissLatency::total 88127.384000 # average ReadReq mshr miss latency ((Tick/Count))
|
|
system.cpu3.icache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.icache.tags.tagsInUse 505.919130 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu3.icache.tags.totalRefs 27673 # Total number of references to valid blocks. (Count)
|
|
system.cpu3.icache.tags.sampledRefs 1625 # Sample count of references to valid blocks. (Count)
|
|
system.cpu3.icache.tags.avgRefs 17.029538 # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu3.icache.tags.warmupTick 109500 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu3.icache.tags.occupancies::cpu3.inst 505.919130 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.cpu3.icache.tags.avgOccs::cpu3.inst 0.988123 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu3.icache.tags.avgOccs::total 0.988123 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.cpu3.icache.tags.occupanciesTaskId::1024 506 # Occupied blocks per task id (Count)
|
|
system.cpu3.icache.tags.ageTaskId_1024::4 506 # Occupied blocks per task id, per block age (Count)
|
|
system.cpu3.icache.tags.ratioOccsTaskId::1024 0.988281 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.cpu3.icache.tags.tagAccesses 58079 # Number of tag accesses (Count)
|
|
system.cpu3.icache.tags.dataAccesses 58079 # Number of data accesses (Count)
|
|
system.cpu3.icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
|
|
system.cpu3.iew.squashCycles 3476 # Number of cycles IEW is squashing (Cycle)
|
|
system.cpu3.iew.blockCycles 106200 # Number of cycles IEW is blocking (Cycle)
|
|
system.cpu3.iew.unblockCycles 3822 # Number of cycles IEW is unblocking (Cycle)
|
|
system.cpu3.iew.dispatchedInsts 377920 # Number of instructions dispatched to IQ (Count)
|
|
system.cpu3.iew.dispSquashedInsts 470 # Number of squashed instructions skipped by dispatch (Count)
|
|
system.cpu3.iew.dispLoadInsts 48704 # Number of dispatched load instructions (Count)
|
|
system.cpu3.iew.dispStoreInsts 24013 # Number of dispatched store instructions (Count)
|
|
system.cpu3.iew.dispNonSpecInsts 54 # Number of dispatched non-speculative instructions (Count)
|
|
system.cpu3.iew.iqFullEvents 614 # Number of times the IQ has become full, causing a stall (Count)
|
|
system.cpu3.iew.lsqFullEvents 2837 # Number of times the LSQ has become full, causing a stall (Count)
|
|
system.cpu3.iew.memOrderViolationEvents 94 # Number of memory order violations (Count)
|
|
system.cpu3.iew.predictedTakenIncorrect 903 # Number of branches that were predicted taken incorrectly (Count)
|
|
system.cpu3.iew.predictedNotTakenIncorrect 2946 # Number of branches that were predicted not taken incorrectly (Count)
|
|
system.cpu3.iew.branchMispredicts 3849 # Number of branch mispredicts detected at execute (Count)
|
|
system.cpu3.iew.instsToCommit 327285 # Cumulative count of insts sent to commit (Count)
|
|
system.cpu3.iew.writebackCount 325621 # Cumulative count of insts written-back (Count)
|
|
system.cpu3.iew.producerInst 238861 # Number of instructions producing a value (Count)
|
|
system.cpu3.iew.consumerInst 427623 # Number of instructions consuming a value (Count)
|
|
system.cpu3.iew.wbRate 0.698660 # Insts written-back per cycle ((Count/Cycle))
|
|
system.cpu3.iew.wbFanout 0.558578 # Average fanout of values written-back ((Count/Count))
|
|
system.cpu3.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
|
|
system.cpu3.itb_walker_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu3.itb_walker_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.cpu3.itb_walker_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.cpu3.itb_walker_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.cpu3.itb_walker_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu3.itb_walker_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.cpu3.itb_walker_cache.replacements 0 # number of replacements (Count)
|
|
system.cpu3.itb_walker_cache.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.itb_walker_cache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
|
|
system.cpu3.itb_walker_cache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
|
|
system.cpu3.itb_walker_cache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
|
|
system.cpu3.itb_walker_cache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
|
|
system.cpu3.itb_walker_cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
|
|
system.cpu3.itb_walker_cache.tags.tagAccesses 0 # Number of tag accesses (Count)
|
|
system.cpu3.itb_walker_cache.tags.dataAccesses 0 # Number of data accesses (Count)
|
|
system.cpu3.itb_walker_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.lsq0.forwLoads 4230 # Number of loads that had data forwarded from stores (Count)
|
|
system.cpu3.lsq0.squashedLoads 15212 # Number of loads squashed (Count)
|
|
system.cpu3.lsq0.ignoredResponses 25 # Number of memory responses ignored because the instruction is squashed (Count)
|
|
system.cpu3.lsq0.memOrderViolation 94 # Number of memory ordering violations (Count)
|
|
system.cpu3.lsq0.squashedStores 7451 # Number of stores squashed (Count)
|
|
system.cpu3.lsq0.rescheduledLoads 1 # Number of loads that were rescheduled (Count)
|
|
system.cpu3.lsq0.blockedByCache 45 # Number of times an access to memory failed due to the cache being blocked (Count)
|
|
system.cpu3.lsq0.loadToUse::samples 33492 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::mean 16.620357 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::stdev 52.226520 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::0-9 30684 91.62% 91.62% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::10-19 27 0.08% 91.70% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::20-29 388 1.16% 92.86% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::30-39 18 0.05% 92.91% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::40-49 5 0.01% 92.92% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::50-59 6 0.02% 92.94% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::60-69 2 0.01% 92.95% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::70-79 6 0.02% 92.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::80-89 8 0.02% 92.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::90-99 7 0.02% 93.01% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::100-109 9 0.03% 93.04% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::110-119 13 0.04% 93.08% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::120-129 36 0.11% 93.18% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::130-139 64 0.19% 93.37% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::140-149 599 1.79% 95.16% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::150-159 149 0.44% 95.61% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::160-169 93 0.28% 95.89% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::170-179 164 0.49% 96.38% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::180-189 80 0.24% 96.61% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::190-199 148 0.44% 97.06% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::200-209 645 1.93% 98.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::210-219 114 0.34% 99.32% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::220-229 55 0.16% 99.49% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::230-239 24 0.07% 99.56% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::240-249 12 0.04% 99.59% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::250-259 23 0.07% 99.66% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::260-269 21 0.06% 99.73% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::270-279 25 0.07% 99.80% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::280-289 7 0.02% 99.82% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::290-299 8 0.02% 99.84% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::overflows 52 0.16% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::max_value 837 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.lsq0.loadToUse::total 33492 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
|
|
system.cpu3.mmu.dtb.rdAccesses 43901 # TLB accesses on read requests (Count)
|
|
system.cpu3.mmu.dtb.wrAccesses 21337 # TLB accesses on write requests (Count)
|
|
system.cpu3.mmu.dtb.rdMisses 403 # TLB misses on read requests (Count)
|
|
system.cpu3.mmu.dtb.wrMisses 104 # TLB misses on write requests (Count)
|
|
system.cpu3.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
|
|
system.cpu3.mmu.itb.wrAccesses 28619 # TLB accesses on write requests (Count)
|
|
system.cpu3.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
|
|
system.cpu3.mmu.itb.wrMisses 591 # TLB misses on write requests (Count)
|
|
system.cpu3.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.power_state.pwrStateResidencyTicks::ON 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.cpu3.rename.squashCycles 3476 # Number of cycles rename is squashing (Cycle)
|
|
system.cpu3.rename.idleCycles 81971 # Number of cycles rename is idle (Cycle)
|
|
system.cpu3.rename.blockCycles 144262 # Number of cycles rename is blocking (Cycle)
|
|
system.cpu3.rename.serializeStallCycles 2392 # count of cycles rename stalled for serializing inst (Cycle)
|
|
system.cpu3.rename.runCycles 55245 # Number of cycles rename is running (Cycle)
|
|
system.cpu3.rename.unblockCycles 31042 # Number of cycles rename is unblocking (Cycle)
|
|
system.cpu3.rename.renamedInsts 397609 # Number of instructions processed by rename (Count)
|
|
system.cpu3.rename.ROBFullEvents 1820 # Number of times rename has blocked due to ROB full (Count)
|
|
system.cpu3.rename.IQFullEvents 7933 # Number of times rename has blocked due to IQ full (Count)
|
|
system.cpu3.rename.LQFullEvents 1173 # Number of times rename has blocked due to LQ full (Count)
|
|
system.cpu3.rename.SQFullEvents 18358 # Number of times rename has blocked due to SQ full (Count)
|
|
system.cpu3.rename.renamedOperands 697269 # Number of destination operands rename has renamed (Count)
|
|
system.cpu3.rename.lookups 1364947 # Number of register rename lookups that rename has made (Count)
|
|
system.cpu3.rename.intLookups 522450 # Number of integer rename lookups (Count)
|
|
system.cpu3.rename.fpLookups 33075 # Number of floating rename lookups (Count)
|
|
system.cpu3.rename.committedMaps 441386 # Number of HB maps that are committed (Count)
|
|
system.cpu3.rename.undoneMaps 255883 # Number of HB maps that are undone due to squashing (Count)
|
|
system.cpu3.rename.serializing 68 # count of serializing insts renamed (Count)
|
|
system.cpu3.rename.tempSerializing 55 # count of temporary serializing insts renamed (Count)
|
|
system.cpu3.rename.skidInsts 37363 # count of insts added to the skid buffer (Count)
|
|
system.cpu3.rob.reads 659481 # The number of ROB reads (Count)
|
|
system.cpu3.rob.writes 771061 # The number of ROB writes (Count)
|
|
system.cpu3.thread_0.numInsts 129365 # Number of Instructions committed (Count)
|
|
system.cpu3.thread_0.numOps 251118 # Number of Ops committed (Count)
|
|
system.cpu3.thread_0.numMemRefs 0 # Number of Memory References (Count)
|
|
system.cpu3.workload.numSyscalls 36 # Number of system calls (Count)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks (Tick)
|
|
system.cpu_voltage_domain.voltage 1 # Voltage in Volts (Volt)
|
|
system.l2.demandHits::cpu0.inst 11 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu0.data 26 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu1.inst 11 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu1.data 26 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu2.inst 452 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu2.data 1665 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu3.inst 129 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::cpu3.data 403 # number of demand (read+write) hits (Count)
|
|
system.l2.demandHits::total 2723 # number of demand (read+write) hits (Count)
|
|
system.l2.overallHits::cpu0.inst 11 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu0.data 26 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu1.inst 11 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu1.data 26 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu2.inst 452 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu2.data 1665 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu3.inst 129 # number of overall hits (Count)
|
|
system.l2.overallHits::cpu3.data 403 # number of overall hits (Count)
|
|
system.l2.overallHits::total 2723 # number of overall hits (Count)
|
|
system.l2.demandMisses::cpu0.inst 564 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu0.data 2484815 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu1.inst 565 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu1.data 2484818 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu2.inst 1945 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu2.data 2830 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu3.inst 1493 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::cpu3.data 1494 # number of demand (read+write) misses (Count)
|
|
system.l2.demandMisses::total 4978524 # number of demand (read+write) misses (Count)
|
|
system.l2.overallMisses::cpu0.inst 564 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu0.data 2484815 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu1.inst 565 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu1.data 2484818 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu2.inst 1945 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu2.data 2830 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu3.inst 1493 # number of overall misses (Count)
|
|
system.l2.overallMisses::cpu3.data 1494 # number of overall misses (Count)
|
|
system.l2.overallMisses::total 4978524 # number of overall misses (Count)
|
|
system.l2.demandMissLatency::cpu0.inst 56369000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu0.data 214106631000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu1.inst 57372000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu1.data 214107351500 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu2.inst 172907000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu2.data 261536500 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu3.inst 139338000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::cpu3.data 139114000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.demandMissLatency::total 429040619000 # number of demand (read+write) miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu0.inst 56369000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu0.data 214106631000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu1.inst 57372000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu1.data 214107351500 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu2.inst 172907000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu2.data 261536500 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu3.inst 139338000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::cpu3.data 139114000 # number of overall miss ticks (Tick)
|
|
system.l2.overallMissLatency::total 429040619000 # number of overall miss ticks (Tick)
|
|
system.l2.demandAccesses::cpu0.inst 575 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu0.data 2484841 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu1.inst 576 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu1.data 2484844 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu2.inst 2397 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu2.data 4495 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu3.inst 1622 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::cpu3.data 1897 # number of demand (read+write) accesses (Count)
|
|
system.l2.demandAccesses::total 4981247 # number of demand (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu0.inst 575 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu0.data 2484841 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu1.inst 576 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu1.data 2484844 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu2.inst 2397 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu2.data 4495 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu3.inst 1622 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::cpu3.data 1897 # number of overall (read+write) accesses (Count)
|
|
system.l2.overallAccesses::total 4981247 # number of overall (read+write) accesses (Count)
|
|
system.l2.demandMissRate::cpu0.inst 0.980870 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu0.data 0.999990 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu1.inst 0.980903 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu1.data 0.999990 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu2.inst 0.811431 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu2.data 0.629588 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu3.inst 0.920469 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::cpu3.data 0.787559 # miss rate for demand accesses (Ratio)
|
|
system.l2.demandMissRate::total 0.999453 # miss rate for demand accesses (Ratio)
|
|
system.l2.overallMissRate::cpu0.inst 0.980870 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu0.data 0.999990 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu1.inst 0.980903 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu1.data 0.999990 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu2.inst 0.811431 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu2.data 0.629588 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu3.inst 0.920469 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::cpu3.data 0.787559 # miss rate for overall accesses (Ratio)
|
|
system.l2.overallMissRate::total 0.999453 # miss rate for overall accesses (Ratio)
|
|
system.l2.demandAvgMissLatency::cpu0.inst 99945.035461 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu0.data 86166.024835 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu1.inst 101543.362832 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu1.data 86166.210765 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu2.inst 88898.200514 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu2.data 92415.724382 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu3.inst 93327.528466 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::cpu3.data 93115.127175 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.demandAvgMissLatency::total 86178.276734 # average overall miss latency in ticks ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu0.inst 99945.035461 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu0.data 86166.024835 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu1.inst 101543.362832 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu1.data 86166.210765 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu2.inst 88898.200514 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu2.data 92415.724382 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu3.inst 93327.528466 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::cpu3.data 93115.127175 # average overall miss latency ((Tick/Count))
|
|
system.l2.overallAvgMissLatency::total 86178.276734 # average overall miss latency ((Tick/Count))
|
|
system.l2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
|
|
system.l2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
|
|
system.l2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
|
|
system.l2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
|
|
system.l2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.l2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
|
|
system.l2.writebacks::writebacks 4952761 # number of writebacks (Count)
|
|
system.l2.writebacks::total 4952761 # number of writebacks (Count)
|
|
system.l2.demandMshrMisses::cpu0.inst 564 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu0.data 2484815 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu1.inst 565 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu1.data 2484818 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu2.inst 1945 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu2.data 2830 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu3.inst 1493 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::cpu3.data 1494 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.demandMshrMisses::total 4978524 # number of demand (read+write) MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu0.inst 564 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu0.data 2484815 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu1.inst 565 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu1.data 2484818 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu2.inst 1945 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu2.data 2830 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu3.inst 1493 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::cpu3.data 1494 # number of overall MSHR misses (Count)
|
|
system.l2.overallMshrMisses::total 4978524 # number of overall MSHR misses (Count)
|
|
system.l2.demandMshrMissLatency::cpu0.inst 50729000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu0.data 189258491000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu1.inst 51722000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu1.data 189259181500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu2.inst 153457000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu2.data 233236500 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu3.inst 124408000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::cpu3.data 124174000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissLatency::total 379255399000 # number of demand (read+write) MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu0.inst 50729000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu0.data 189258491000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu1.inst 51722000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu1.data 189259181500 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu2.inst 153457000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu2.data 233236500 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu3.inst 124408000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::cpu3.data 124174000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.overallMshrMissLatency::total 379255399000 # number of overall MSHR miss ticks (Tick)
|
|
system.l2.demandMshrMissRate::cpu0.inst 0.980870 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu0.data 0.999990 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu1.inst 0.980903 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu1.data 0.999990 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu2.inst 0.811431 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu2.data 0.629588 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu3.inst 0.920469 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::cpu3.data 0.787559 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.demandMshrMissRate::total 0.999453 # mshr miss ratio for demand accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu0.inst 0.980870 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu0.data 0.999990 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu1.inst 0.980903 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu1.data 0.999990 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu2.inst 0.811431 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu2.data 0.629588 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu3.inst 0.920469 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::cpu3.data 0.787559 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.overallMshrMissRate::total 0.999453 # mshr miss ratio for overall accesses (Ratio)
|
|
system.l2.demandAvgMshrMissLatency::cpu0.inst 89945.035461 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu0.data 76166.028859 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu1.inst 91543.362832 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu1.data 76166.214789 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu2.inst 78898.200514 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu2.data 82415.724382 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu3.inst 83327.528466 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::cpu3.data 83115.127175 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.demandAvgMshrMissLatency::total 76178.280751 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu0.inst 89945.035461 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu0.data 76166.028859 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu1.inst 91543.362832 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu1.data 76166.214789 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu2.inst 78898.200514 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu2.data 82415.724382 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu3.inst 83327.528466 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::cpu3.data 83115.127175 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.overallAvgMshrMissLatency::total 76178.280751 # average overall mshr miss latency ((Tick/Count))
|
|
system.l2.replacements 4967160 # number of replacements (Count)
|
|
system.l2.CleanEvict.mshrMisses::writebacks 3 # number of CleanEvict MSHR misses (Count)
|
|
system.l2.CleanEvict.mshrMisses::total 3 # number of CleanEvict MSHR misses (Count)
|
|
system.l2.CleanEvict.mshrMissRate::writebacks inf # mshr miss rate for CleanEvict accesses (Ratio)
|
|
system.l2.CleanEvict.mshrMissRate::total inf # mshr miss rate for CleanEvict accesses (Ratio)
|
|
system.l2.ReadCleanReq.hits::cpu0.inst 11 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.hits::cpu1.inst 11 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.hits::cpu2.inst 452 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.hits::cpu3.inst 129 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.hits::total 603 # number of ReadCleanReq hits (Count)
|
|
system.l2.ReadCleanReq.misses::cpu0.inst 564 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.misses::cpu1.inst 565 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.misses::cpu2.inst 1945 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.misses::cpu3.inst 1493 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.misses::total 4567 # number of ReadCleanReq misses (Count)
|
|
system.l2.ReadCleanReq.missLatency::cpu0.inst 56369000 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.missLatency::cpu1.inst 57372000 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.missLatency::cpu2.inst 172907000 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.missLatency::cpu3.inst 139338000 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.missLatency::total 425986000 # number of ReadCleanReq miss ticks (Tick)
|
|
system.l2.ReadCleanReq.accesses::cpu0.inst 575 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.accesses::cpu1.inst 576 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.accesses::cpu2.inst 2397 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.accesses::cpu3.inst 1622 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.accesses::total 5170 # number of ReadCleanReq accesses(hits+misses) (Count)
|
|
system.l2.ReadCleanReq.missRate::cpu0.inst 0.980870 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.missRate::cpu1.inst 0.980903 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.missRate::cpu2.inst 0.811431 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.missRate::cpu3.inst 0.920469 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.missRate::total 0.883366 # miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.avgMissLatency::cpu0.inst 99945.035461 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMissLatency::cpu1.inst 101543.362832 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMissLatency::cpu2.inst 88898.200514 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMissLatency::cpu3.inst 93327.528466 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMissLatency::total 93274.797460 # average ReadCleanReq miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.mshrMisses::cpu0.inst 564 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMisses::cpu1.inst 565 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMisses::cpu2.inst 1945 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMisses::cpu3.inst 1493 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMisses::total 4567 # number of ReadCleanReq MSHR misses (Count)
|
|
system.l2.ReadCleanReq.mshrMissLatency::cpu0.inst 50729000 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissLatency::cpu1.inst 51722000 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissLatency::cpu2.inst 153457000 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissLatency::cpu3.inst 124408000 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissLatency::total 380316000 # number of ReadCleanReq MSHR miss ticks (Tick)
|
|
system.l2.ReadCleanReq.mshrMissRate::cpu0.inst 0.980870 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.mshrMissRate::cpu1.inst 0.980903 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.mshrMissRate::cpu2.inst 0.811431 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.mshrMissRate::cpu3.inst 0.920469 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.mshrMissRate::total 0.883366 # mshr miss rate for ReadCleanReq accesses (Ratio)
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::cpu0.inst 89945.035461 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::cpu1.inst 91543.362832 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::cpu2.inst 78898.200514 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::cpu3.inst 83327.528466 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadCleanReq.avgMshrMissLatency::total 83274.797460 # average ReadCleanReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.hits::cpu0.data 6 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.hits::cpu1.data 7 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.hits::cpu2.data 77 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.hits::cpu3.data 34 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.hits::total 124 # number of ReadExReq hits (Count)
|
|
system.l2.ReadExReq.misses::cpu0.data 2484087 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.misses::cpu1.data 2484090 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.misses::cpu2.data 637 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.misses::cpu3.data 333 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.misses::total 4969147 # number of ReadExReq misses (Count)
|
|
system.l2.ReadExReq.missLatency::cpu0.data 214041332500 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.missLatency::cpu1.data 214041695500 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.missLatency::cpu2.data 57309000 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.missLatency::cpu3.data 30316500 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.missLatency::total 428170653500 # number of ReadExReq miss ticks (Tick)
|
|
system.l2.ReadExReq.accesses::cpu0.data 2484093 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.accesses::cpu1.data 2484097 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.accesses::cpu2.data 714 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.accesses::cpu3.data 367 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.accesses::total 4969271 # number of ReadExReq accesses(hits+misses) (Count)
|
|
system.l2.ReadExReq.missRate::cpu0.data 0.999998 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.missRate::cpu1.data 0.999997 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.missRate::cpu2.data 0.892157 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.missRate::cpu3.data 0.907357 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.missRate::total 0.999975 # miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.avgMissLatency::cpu0.data 86164.990397 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMissLatency::cpu1.data 86165.032467 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMissLatency::cpu2.data 89967.032967 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMissLatency::cpu3.data 91040.540541 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMissLatency::total 86165.825543 # average ReadExReq miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.mshrMisses::cpu0.data 2484087 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMisses::cpu1.data 2484090 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMisses::cpu2.data 637 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMisses::cpu3.data 333 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMisses::total 4969147 # number of ReadExReq MSHR misses (Count)
|
|
system.l2.ReadExReq.mshrMissLatency::cpu0.data 189200472500 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissLatency::cpu1.data 189200805500 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissLatency::cpu2.data 50939000 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissLatency::cpu3.data 26986500 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissLatency::total 378479203500 # number of ReadExReq MSHR miss ticks (Tick)
|
|
system.l2.ReadExReq.mshrMissRate::cpu0.data 0.999998 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.mshrMissRate::cpu1.data 0.999997 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.mshrMissRate::cpu2.data 0.892157 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.mshrMissRate::cpu3.data 0.907357 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.mshrMissRate::total 0.999975 # mshr miss rate for ReadExReq accesses (Ratio)
|
|
system.l2.ReadExReq.avgMshrMissLatency::cpu0.data 76164.994422 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMshrMissLatency::cpu1.data 76165.036492 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMshrMissLatency::cpu2.data 79967.032967 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMshrMissLatency::cpu3.data 81040.540541 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadExReq.avgMshrMissLatency::total 76165.829568 # average ReadExReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.hits::cpu0.data 20 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.hits::cpu1.data 19 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.hits::cpu2.data 1588 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.hits::cpu3.data 369 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.hits::total 1996 # number of ReadSharedReq hits (Count)
|
|
system.l2.ReadSharedReq.misses::cpu0.data 728 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.misses::cpu1.data 728 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.misses::cpu2.data 2193 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.misses::cpu3.data 1161 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.misses::total 4810 # number of ReadSharedReq misses (Count)
|
|
system.l2.ReadSharedReq.missLatency::cpu0.data 65298500 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.missLatency::cpu1.data 65656000 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.missLatency::cpu2.data 204227500 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.missLatency::cpu3.data 108797500 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.missLatency::total 443979500 # number of ReadSharedReq miss ticks (Tick)
|
|
system.l2.ReadSharedReq.accesses::cpu0.data 748 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.accesses::cpu1.data 747 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.accesses::cpu2.data 3781 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.accesses::cpu3.data 1530 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.accesses::total 6806 # number of ReadSharedReq accesses(hits+misses) (Count)
|
|
system.l2.ReadSharedReq.missRate::cpu0.data 0.973262 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.missRate::cpu1.data 0.974565 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.missRate::cpu2.data 0.580005 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.missRate::cpu3.data 0.758824 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.missRate::total 0.706729 # miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.avgMissLatency::cpu0.data 89695.741758 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMissLatency::cpu1.data 90186.813187 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMissLatency::cpu2.data 93126.994984 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMissLatency::cpu3.data 93710.163652 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMissLatency::total 92303.430353 # average ReadSharedReq miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.mshrMisses::cpu0.data 728 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMisses::cpu1.data 728 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMisses::cpu2.data 2193 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMisses::cpu3.data 1161 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMisses::total 4810 # number of ReadSharedReq MSHR misses (Count)
|
|
system.l2.ReadSharedReq.mshrMissLatency::cpu0.data 58018500 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissLatency::cpu1.data 58376000 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissLatency::cpu2.data 182297500 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissLatency::cpu3.data 97187500 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissLatency::total 395879500 # number of ReadSharedReq MSHR miss ticks (Tick)
|
|
system.l2.ReadSharedReq.mshrMissRate::cpu0.data 0.973262 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.mshrMissRate::cpu1.data 0.974565 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.mshrMissRate::cpu2.data 0.580005 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.mshrMissRate::cpu3.data 0.758824 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.mshrMissRate::total 0.706729 # mshr miss rate for ReadSharedReq accesses (Ratio)
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::cpu0.data 79695.741758 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::cpu1.data 80186.813187 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::cpu2.data 83126.994984 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::cpu3.data 83710.163652 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.ReadSharedReq.avgMshrMissLatency::total 82303.430353 # average ReadSharedReq mshr miss latency ((Tick/Count))
|
|
system.l2.UpgradeReq.hits::cpu0.data 2 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.hits::cpu1.data 2 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.hits::cpu2.data 4 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.hits::cpu3.data 1 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.hits::total 9 # number of UpgradeReq hits (Count)
|
|
system.l2.UpgradeReq.accesses::cpu0.data 2 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.UpgradeReq.accesses::cpu1.data 2 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.UpgradeReq.accesses::cpu2.data 4 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.UpgradeReq.accesses::cpu3.data 1 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.UpgradeReq.accesses::total 9 # number of UpgradeReq accesses(hits+misses) (Count)
|
|
system.l2.WritebackClean.hits::writebacks 3337 # number of WritebackClean hits (Count)
|
|
system.l2.WritebackClean.hits::total 3337 # number of WritebackClean hits (Count)
|
|
system.l2.WritebackClean.accesses::writebacks 3337 # number of WritebackClean accesses(hits+misses) (Count)
|
|
system.l2.WritebackClean.accesses::total 3337 # number of WritebackClean accesses(hits+misses) (Count)
|
|
system.l2.WritebackDirty.hits::writebacks 4968961 # number of WritebackDirty hits (Count)
|
|
system.l2.WritebackDirty.hits::total 4968961 # number of WritebackDirty hits (Count)
|
|
system.l2.WritebackDirty.accesses::writebacks 4968961 # number of WritebackDirty accesses(hits+misses) (Count)
|
|
system.l2.WritebackDirty.accesses::total 4968961 # number of WritebackDirty accesses(hits+misses) (Count)
|
|
system.l2.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.l2.tags.tagsInUse 16369.698562 # Average ticks per tags in use ((Tick/Count))
|
|
system.l2.tags.totalRefs 9958611 # Total number of references to valid blocks. (Count)
|
|
system.l2.tags.sampledRefs 4983544 # Sample count of references to valid blocks. (Count)
|
|
system.l2.tags.avgRefs 1.998299 # Average number of references to valid blocks. ((Count/Count))
|
|
system.l2.tags.warmupTick 77000 # The tick when the warmup percentage was hit. (Tick)
|
|
system.l2.tags.occupancies::writebacks 14.054236 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu0.inst 0.933716 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu0.data 8168.910001 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu1.inst 1.008531 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu1.data 8166.563870 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu2.inst 4.948013 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu2.data 7.336382 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu3.inst 3.111965 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.occupancies::cpu3.data 2.831848 # Average occupied blocks per tick, per requestor ((Count/Tick))
|
|
system.l2.tags.avgOccs::writebacks 0.000858 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu0.inst 0.000057 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu0.data 0.498591 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu1.inst 0.000062 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu1.data 0.498448 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu2.inst 0.000302 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu2.data 0.000448 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu3.inst 0.000190 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::cpu3.data 0.000173 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.avgOccs::total 0.999127 # Average percentage of cache occupancy ((Ratio/Tick))
|
|
system.l2.tags.occupanciesTaskId::1024 16384 # Occupied blocks per task id (Count)
|
|
system.l2.tags.ageTaskId_1024::0 227 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::1 2008 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ageTaskId_1024::2 14149 # Occupied blocks per task id, per block age (Count)
|
|
system.l2.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
|
|
system.l2.tags.tagAccesses 84652472 # Number of tag accesses (Count)
|
|
system.l2.tags.dataAccesses 84652472 # Number of data accesses (Count)
|
|
system.l2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.mem_ctrls.avgPriority_writebacks::samples 4952761.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu0.inst::samples 564.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu0.data::samples 2484815.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu1.inst::samples 565.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu1.data::samples 2484817.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu2.inst::samples 1945.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu2.data::samples 2830.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu3.inst::samples 1493.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.avgPriority_cpu3.data::samples 1494.00 # Average QoS priority value for accepted requests (Count)
|
|
system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (Second)
|
|
system.mem_ctrls.priorityMaxLatency 0.000144283250 # per QoS priority maximum request to response latency (Second)
|
|
system.mem_ctrls.numReadWriteTurnArounds 309475 # Number of turnarounds from READ to WRITE (Count)
|
|
system.mem_ctrls.numWriteReadTurnArounds 309475 # Number of turnarounds from WRITE to READ (Count)
|
|
system.mem_ctrls.numStayReadState 14038531 # Number of times bus staying in READ state (Count)
|
|
system.mem_ctrls.numStayWriteState 4652693 # Number of times bus staying in WRITE state (Count)
|
|
system.mem_ctrls.readReqs 4978523 # Number of read requests accepted (Count)
|
|
system.mem_ctrls.writeReqs 4952761 # Number of write requests accepted (Count)
|
|
system.mem_ctrls.readBursts 4978523 # Number of controller read bursts, including those serviced by the write queue (Count)
|
|
system.mem_ctrls.writeBursts 4952761 # Number of controller write bursts, including those merged in the write queue (Count)
|
|
system.mem_ctrls.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
|
|
system.mem_ctrls.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
|
|
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
|
|
system.mem_ctrls.avgRdQLen 1.34 # Average read queue length when enqueuing ((Count/Tick))
|
|
system.mem_ctrls.avgWrQLen 25.97 # Average write queue length when enqueuing ((Count/Tick))
|
|
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry (Count)
|
|
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry (Count)
|
|
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.readPktSize::6 4978523 # Read request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.writePktSize::6 4952761 # Write request sizes (log2) (Count)
|
|
system.mem_ctrls.rdQLenPdf::0 4317265 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::1 654731 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::2 3489 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::3 1587 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::4 770 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::5 359 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::6 169 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::7 78 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::8 41 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::9 20 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::10 11 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::11 3 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::16 179 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::17 11789 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::18 310545 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::19 320387 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::20 312379 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::21 312883 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::22 316815 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::23 449139 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::24 314425 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::25 356215 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::26 316647 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::27 310907 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::28 343698 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::29 323739 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::30 312151 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::31 330353 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::32 309513 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::33 975 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::34 4 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::35 1 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
|
|
system.mem_ctrls.rdPerTurnAround::samples 309475 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::mean 16.086967 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::gmean 16.006888 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::stdev 19.439303 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::0-511 309471 100.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.rdPerTurnAround::total 309475 # Reads before turning the bus around for writes (Count)
|
|
system.mem_ctrls.wrPerTurnAround::samples 309475 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::mean 16.003668 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::gmean 16.003378 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::stdev 0.101795 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::16 309052 99.86% 99.86% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::17 37 0.01% 99.88% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::18 60 0.02% 99.89% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::19 326 0.11% 100.00% # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.wrPerTurnAround::total 309475 # Writes before turning the bus around for reads (Count)
|
|
system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
|
|
system.mem_ctrls.bytesReadSys 318625472 # Total read bytes from the system interface side (Byte)
|
|
system.mem_ctrls.bytesWrittenSys 316976704 # Total written bytes from the system interface side (Byte)
|
|
system.mem_ctrls.avgRdBWSys 1427497993.91187167 # Average system read bandwidth in Byte/s ((Byte/Second))
|
|
system.mem_ctrls.avgWrBWSys 1420111224.11706352 # Average system write bandwidth in Byte/s ((Byte/Second))
|
|
system.mem_ctrls.totGap 223205529500 # Total gap between requests (Tick)
|
|
system.mem_ctrls.avgGap 22474.99 # Average gap between requests ((Tick/Count))
|
|
system.mem_ctrls.requestorReadBytes::cpu0.inst 36096 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu0.data 159028160 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu1.inst 36160 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu1.data 159028288 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu2.inst 124480 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu2.data 181120 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu3.inst 95552 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorReadBytes::cpu3.data 95616 # Per-requestor bytes read from memory (Byte)
|
|
system.mem_ctrls.requestorWriteBytes::writebacks 316975040 # Per-requestor bytes write to memory (Byte)
|
|
system.mem_ctrls.requestorReadRate::cpu0.inst 161716.410382415750 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu0.data 712474046.568053960800 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu1.inst 162003.141606498044 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu1.data 712474620.030502080917 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu2.inst 557692.230840068543 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu2.data 811449.364152901806 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu3.inst 428089.717554870062 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadRate::cpu3.data 428376.448778952414 # Per-requestor bytes read from memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorWriteRate::writebacks 1420103769.105237483978 # Per-requestor bytes write to memory rate ((Byte/Second))
|
|
system.mem_ctrls.requestorReadAccesses::cpu0.inst 564 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu0.data 2484815 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu1.inst 565 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu1.data 2484817 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu2.inst 1945 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu2.data 2830 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu3.inst 1493 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadAccesses::cpu3.data 1494 # Per-requestor read serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorWriteAccesses::writebacks 4952761 # Per-requestor write serviced memory accesses (Count)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu0.inst 27436500 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu0.data 87942540250 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu1.inst 28398250 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu1.data 87942907500 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu2.inst 73252250 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu2.data 116511000 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu3.inst 62811000 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadTotalLat::cpu3.data 62536750 # Per-requestor read total memory access latency (Tick)
|
|
system.mem_ctrls.requestorWriteTotalLat::writebacks 5639052322000 # Per-requestor write total memory access latency (Tick)
|
|
system.mem_ctrls.requestorReadAvgLat::cpu0.inst 48646.28 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu0.data 35391.99 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu1.inst 50262.39 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu1.data 35392.11 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu2.inst 37661.83 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu2.data 41169.96 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu3.inst 42070.33 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorReadAvgLat::cpu3.data 41858.60 # Per-requestor read average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.requestorWriteAvgLat::writebacks 1138567.42 # Per-requestor write average memory access latency ((Tick/Count))
|
|
system.mem_ctrls.dram.bytesRead::cpu0.inst 36096 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu0.data 159028160 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu1.inst 36160 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu1.data 159028288 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu2.inst 124480 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu2.data 181120 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu3.inst 95552 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::cpu3.data 95616 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesRead::total 318625472 # Number of bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::cpu0.inst 36096 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::cpu1.inst 36160 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::cpu2.inst 124480 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::cpu3.inst 95552 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesInstRead::total 292288 # Number of instructions bytes read from this memory (Byte)
|
|
system.mem_ctrls.dram.bytesWritten::writebacks 316976704 # Number of bytes written to this memory (Byte)
|
|
system.mem_ctrls.dram.bytesWritten::total 316976704 # Number of bytes written to this memory (Byte)
|
|
system.mem_ctrls.dram.numReads::cpu0.inst 564 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu0.data 2484815 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu1.inst 565 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu1.data 2484817 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu2.inst 1945 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu2.data 2830 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu3.inst 1493 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::cpu3.data 1494 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numReads::total 4978523 # Number of read requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numWrites::writebacks 4952761 # Number of write requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.numWrites::total 4952761 # Number of write requests responded to by this memory (Count)
|
|
system.mem_ctrls.dram.bwRead::cpu0.inst 161716 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu0.data 712474047 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu1.inst 162003 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu1.data 712474620 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu2.inst 557692 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu2.data 811449 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu3.inst 428090 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::cpu3.data 428376 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwRead::total 1427497994 # Total read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::cpu0.inst 161716 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::cpu1.inst 162003 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::cpu2.inst 557692 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::cpu3.inst 428090 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwInstRead::total 1309502 # Instruction read bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwWrite::writebacks 1420111224 # Write bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwWrite::total 1420111224 # Write bandwidth from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::writebacks 1420111224 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu0.inst 161716 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu0.data 712474047 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu1.inst 162003 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu1.data 712474620 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu2.inst 557692 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu2.data 811449 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu3.inst 428090 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::cpu3.data 428376 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.bwTotal::total 2847609218 # Total bandwidth to/from this memory ((Byte/Second))
|
|
system.mem_ctrls.dram.readBursts 4978523 # Number of DRAM read bursts (Count)
|
|
system.mem_ctrls.dram.writeBursts 4952735 # Number of DRAM write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::0 311363 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::1 311562 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::2 310331 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::3 310558 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::4 311124 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::5 311758 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::6 311225 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::7 311977 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::8 311815 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::9 311647 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::10 311572 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::11 310523 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::12 310989 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::13 310614 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::14 310719 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankRdBursts::15 310746 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::0 309906 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::1 309959 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::2 308971 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::3 309058 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::4 309489 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::5 310059 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::6 309660 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::7 310374 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::8 310185 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::9 310000 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::10 309691 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::11 308831 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::12 309417 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::13 308939 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::14 308964 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.perBankWrBursts::15 309232 # Per bank write bursts (Count)
|
|
system.mem_ctrls.dram.totQLat 82909087250 # Total ticks spent queuing (Tick)
|
|
system.mem_ctrls.dram.totBusLat 24892615000 # Total ticks spent in databus transfers (Tick)
|
|
system.mem_ctrls.dram.totMemAccLat 176256393500 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
|
|
system.mem_ctrls.dram.avgQLat 16653.35 # Average queueing delay per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.avgBusLat 5000.00 # Average bus latency per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.avgMemAccLat 35403.35 # Average memory access latency per DRAM burst ((Tick/Count))
|
|
system.mem_ctrls.dram.readRowHits 4547961 # Number of row buffer hits during reads (Count)
|
|
system.mem_ctrls.dram.writeRowHits 4600319 # Number of row buffer hits during writes (Count)
|
|
system.mem_ctrls.dram.readRowHitRate 91.35 # Row buffer hit rate for reads (Ratio)
|
|
system.mem_ctrls.dram.writeRowHitRate 92.88 # Row buffer hit rate for writes (Ratio)
|
|
system.mem_ctrls.dram.bytesPerActivate::samples 782975 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::mean 811.773883 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::gmean 685.722080 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::stdev 320.286458 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::0-127 35247 4.50% 4.50% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::128-255 38742 4.95% 9.45% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::256-383 38284 4.89% 14.34% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::384-511 35001 4.47% 18.81% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::512-639 61794 7.89% 26.70% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::640-767 24563 3.14% 29.84% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::768-895 28581 3.65% 33.49% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::896-1023 40061 5.12% 38.61% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::1024-1151 480702 61.39% 100.00% # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesPerActivate::total 782975 # Bytes accessed per row activation (Byte)
|
|
system.mem_ctrls.dram.bytesRead 318625472 # Total bytes read (Byte)
|
|
system.mem_ctrls.dram.bytesWritten 316975040 # Total bytes written (Byte)
|
|
system.mem_ctrls.dram.avgRdBW 1427.497994 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
|
|
system.mem_ctrls.dram.avgWrBW 1420.103769 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
|
|
system.mem_ctrls.dram.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
|
|
system.mem_ctrls.dram.busUtil 22.25 # Data bus utilization in percentage (Ratio)
|
|
system.mem_ctrls.dram.busUtilRead 11.15 # Data bus utilization in percentage for reads (Ratio)
|
|
system.mem_ctrls.dram.busUtilWrite 11.09 # Data bus utilization in percentage for writes (Ratio)
|
|
system.mem_ctrls.dram.pageHitRate 92.12 # Row buffer hit rate, read and write combined (Ratio)
|
|
system.mem_ctrls.dram.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.mem_ctrls.dram.rank0.actEnergy 2795267160 # Energy for activate commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.preEnergy 1485708345 # Energy for precharge commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.readEnergy 17777871720 # Energy for read commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.writeEnergy 12932424720 # Energy for write commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.refreshEnergy 17619270240.000004 # Energy for refresh commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.actBackEnergy 62593959480 # Energy for active background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.preBackEnergy 33000228000 # Energy for precharge background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.totalEnergy 148204729665 # Total energy per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank0.averagePower 663.983180 # Core power per rank (mW) (Watt)
|
|
system.mem_ctrls.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::IDLE 84854240750 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::REF 7453160000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::ACT 130898147250 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.actEnergy 2795195760 # Energy for activate commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.preEnergy 1485681780 # Energy for precharge commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.readEnergy 17768782500 # Energy for read commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.writeEnergy 12920851980 # Energy for write commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.refreshEnergy 17619270240.000004 # Energy for refresh commands per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.actBackEnergy 62521123740 # Energy for active background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.preBackEnergy 33061563360 # Energy for precharge background per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.totalEnergy 148172469360 # Total energy per rank (pJ) (Joule)
|
|
system.mem_ctrls.dram.rank1.averagePower 663.838649 # Core power per rank (mW) (Watt)
|
|
system.mem_ctrls.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::IDLE 85012981500 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::REF 7453160000 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::ACT 130739406500 # Time in different power states (Tick)
|
|
system.mem_ctrls.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
|
|
system.mem_ctrls.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.membus.transDist::ReadResp 9377 # Transaction distribution (Count)
|
|
system.membus.transDist::WritebackDirty 4952761 # Transaction distribution (Count)
|
|
system.membus.transDist::CleanEvict 6526 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadExReq 4969146 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadExResp 4969145 # Transaction distribution (Count)
|
|
system.membus.transDist::ReadSharedReq 9377 # Transaction distribution (Count)
|
|
system.membus.pktCount_system.l2.mem_side_port::system.mem_ctrls.port 14916332 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktCount_system.l2.mem_side_port::total 14916332 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktCount::total 14916332 # Packet count per connected requestor and responder (Count)
|
|
system.membus.pktSize_system.l2.mem_side_port::system.mem_ctrls.port 635602112 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.pktSize_system.l2.mem_side_port::total 635602112 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.pktSize::total 635602112 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.membus.snoops 0 # Total snoops (Count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (Byte)
|
|
system.membus.snoopFanout::samples 4978523 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::0 4978523 100.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
|
|
system.membus.snoopFanout::total 4978523 # Request fanout histogram (Count)
|
|
system.membus.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.membus.reqLayer8.occupancy 29751338000 # Layer occupancy (ticks) (Tick)
|
|
system.membus.reqLayer8.utilization 0.1 # Layer utilization (Ratio)
|
|
system.membus.respLayer1.occupancy 26177067250 # Layer occupancy (ticks) (Tick)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (Ratio)
|
|
system.membus.snoop_filter.totRequests 9937810 # Total number of requests made to the snoop filter. (Count)
|
|
system.membus.snoop_filter.hitSingleRequests 4959287 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
|
|
system.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.tol2bus.transDist::ReadResp 11991 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::WritebackDirty 9921722 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::WritebackClean 3346 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::CleanEvict 19465 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::UpgradeReq 9 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::UpgradeResp 9 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadExReq 4969271 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadExResp 4969269 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadCleanReq 5185 # Transaction distribution (Count)
|
|
system.tol2bus.transDist::ReadSharedReq 6806 # Transaction distribution (Count)
|
|
system.tol2bus.pktCount_system.cpu0.icache.mem_side_port::system.l2.cpu_side_port 1320 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu0.dcache.mem_side_port::system.l2.cpu_side_port 7454013 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu1.icache.mem_side_port::system.l2.cpu_side_port 1323 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu1.dcache.mem_side_port::system.l2.cpu_side_port 7454022 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu2.icache.mem_side_port::system.l2.cpu_side_port 6693 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu2.dcache.mem_side_port::system.l2.cpu_side_port 12981 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu3.icache.mem_side_port::system.l2.cpu_side_port 4365 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount_system.cpu3.dcache.mem_side_port::system.l2.cpu_side_port 5181 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktCount::total 14939898 # Packet count per connected requestor and responder (Count)
|
|
system.tol2bus.pktSize_system.cpu0.icache.mem_side_port::system.l2.cpu_side_port 47552 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu0.dcache.mem_side_port::system.l2.cpu_side_port 317981632 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu1.icache.mem_side_port::system.l2.cpu_side_port 47680 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu1.dcache.mem_side_port::system.l2.cpu_side_port 317982080 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu2.icache.mem_side_port::system.l2.cpu_side_port 274432 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu2.dcache.mem_side_port::system.l2.cpu_side_port 362496 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu3.icache.mem_side_port::system.l2.cpu_side_port 175360 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize_system.cpu3.dcache.mem_side_port::system.l2.cpu_side_port 156096 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.pktSize::total 637027328 # Cumulative packet size per connected requestor and responder (Byte)
|
|
system.tol2bus.snoops 4967175 # Total snoops (Count)
|
|
system.tol2bus.snoopTraffic 316977664 # Total snoop traffic (Byte)
|
|
system.tol2bus.snoopFanout::samples 9948431 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::mean 0.000797 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::stdev 0.028236 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::0 9940514 99.92% 99.92% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::1 7910 0.08% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::2 7 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::5 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::6 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::7 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::8 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::9 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::10 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::11 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::12 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::13 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::14 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::15 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::16 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::max_value 2 # Request fanout histogram (Count)
|
|
system.tol2bus.snoopFanout::total 9948431 # Request fanout histogram (Count)
|
|
system.tol2bus.power_state.pwrStateResidencyTicks::UNDEFINED 223205548000 # Cumulative time (in ticks) in various power states (Tick)
|
|
system.tol2bus.reqLayer0.occupancy 9951629000 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer0.occupancy 865500 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer1.occupancy 3727269483 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer12.occupancy 2437999 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer12.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer13.occupancy 2846499 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer13.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer4.occupancy 867000 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer4.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer5.occupancy 3727273983 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer5.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer8.occupancy 3608498 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer8.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.respLayer9.occupancy 6745498 # Layer occupancy (ticks) (Tick)
|
|
system.tol2bus.respLayer9.utilization 0.0 # Layer utilization (Ratio)
|
|
system.tol2bus.snoop_filter.totRequests 9958644 # Total number of requests made to the snoop filter. (Count)
|
|
system.tol2bus.snoop_filter.hitSingleRequests 4977382 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.hitMultiRequests 29 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.totSnoops 7881 # Total number of snoops made to the snoop filter. (Count)
|
|
system.tol2bus.snoop_filter.hitSingleSnoops 7874 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
|
|
system.tol2bus.snoop_filter.hitMultiSnoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
|
|
system.voltage_domain.voltage 1 # Voltage in Volts (Volt)
|
|
system.workload.inst.arm 0 # number of arm instructions executed (Count)
|
|
system.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
|
|
|
|
---------- End Simulation Statistics ----------
|