63 lines
1.8 KiB
Python
63 lines
1.8 KiB
Python
#!/usr/bin/env python3
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# Minimal SmartEdgeAI gem5 configuration
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import argparse, m5
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from m5.objects import *
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# Parse arguments
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ap = argparse.ArgumentParser()
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ap.add_argument("--cmd", required=True)
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ap.add_argument("--mem", default="16GB")
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ap.add_argument("--l2", default="1MB")
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ap.add_argument("--dvfs", choices=["high","low"], default="high")
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ap.add_argument("--drowsy", type=int, choices=[0,1], default=0)
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ap.add_argument("--core", choices=["big","little","hybrid"], default="big")
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ap.add_argument("--outdir", default="m5out")
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args = ap.parse_args()
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# Create system
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system = System()
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system.clk_domain = SrcClockDomain(clock="2GHz" if args.dvfs == "high" else "1GHz",
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voltage_domain=VoltageDomain())
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system.mem_mode = "timing"
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system.mem_ranges = [AddrRange(args.mem)]
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# Create CPU based on core type
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if args.core == "big":
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system.cpu = O3CPU()
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elif args.core == "little":
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system.cpu = TimingSimpleCPU()
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else: # hybrid
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system.cpu = O3CPU()
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# Create memory bus
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system.membus = SystemXBar()
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# Connect CPU to memory bus directly (no caches for simplicity)
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system.cpu.icache_port = system.membus.cpu_side_ports
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system.cpu.dcache_port = system.membus.cpu_side_ports
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# Create memory controller
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system.mem_ctrl = SimpleMemory()
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system.mem_ctrl.range = system.mem_ranges[0]
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system.mem_ctrl.port = system.membus.mem_side_ports
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# Connect system port
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system.system_port = system.membus.cpu_side_ports
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# Create workload
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process = Process()
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process.executable = args.cmd
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process.cmd = [args.cmd]
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# Assign workload to CPU
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system.cpu.workload = process
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system.cpu.createThreads()
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# Create root and run simulation
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root = Root(full_system=False, system=system)
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m5.instantiate()
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print("[SmartEdgeAI] Starting simulation...")
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exit_event = m5.simulate()
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print(f"[SmartEdgeAI] Exiting @ tick {m5.curTick()} because {exit_event.getCause()}")
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